Monolithic Buck Research Articles

Comparator-Controlled Rectification at Monolithic Buck Converters for Higher Input Voltages

An integrated CMOS buck converter for input voltages up to 20 V is presented. It uses an improved comparator to control the low-side switch for asynchronous rectification. To protect the comparator under high voltage condition without relevant power dissipation (losses), a high-ohmic voltage limiter is used. To overcome the speed limitation resulting for the zero-voltage detection, the comparator exploits small-area input transistors and auto-zero circuitry to combine fast decision and low offset voltage. Simulations show a power consumption of 110 μW of the comparator. The measurements of the whole buck converter show up to 92% efficiency with 330-ns pulses at 314-mA output current for 20-V input voltage and 3.6-V output voltage.

Integration of a Monolithic Buck Converter Power IC and Bondwire Inductors With Ferrite Epoxy Glob Cores

In this letter, we report a concept of integrating a monolithic buck converter power IC with in-package bondwire inductors. The power IC containing all switching devices, driver circuitry, and control logic was designed and fabricated with a standard 0.5-μm CMOS process. Mutliturn bondwires with and without ferrite epoxy glob cores are used as the filter inductor in the buck converter. A prototype system-in-package converter with an output voltage and current of 2.5 V and 120 mA was built to operate at frequencies up to 5 MHz. The power level of the prototype buck converter is scalable by increasing the size of the active power switches.

Digital PWM with variable frequency for monolithic buck converter

Presented is a digital pulse width modulator and dead-time circuit for a buck converter. The circuit allows the characterisation of the power converter over a wide range of operating conditions. It was implemented on a 0.35 µm CMOS process and results were measured at a number of switching frequencies.

Monolithic HCC buck and boost converters with simplified convergence analysis methods

The monolithic hysteresis-current-controlled (HCC) buck and boost converters with simplified convergence analysis methods are presented. The architectures of both converters are very simple and only consist of few components. The convergence condition, which is independent to duty cycle of converters, is derived in this paper. Using this concept to synthesize current-mode converters, the component values of converters will be designed easily. There is no sub-harmonic oscillation in the proposed converters without slope compensation even if the duty cycle greater than 50%. The proposed circuits are implemented into a single chip with TSMC 0.35 μm CMOS DPQM processes and their chip area is only 2.25 mm2, respectively. The maximum power efficiency of proposed converters is measured and described in this paper, too.

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2V. The proposed buck DC–DC converter with a chip area of 0.82mm2 is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2V, with an input voltage of 1.5V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300mW.

Design Issues for Monolithic DC–DC Converters

This paper presents various ideas for integrating different components of dc-dc converter on to a silicon chip. These converters are intended to process power levels up to 0.5W. Techniques for integrating capacitors and design issues for MOS transistors are discussed. The most complicated design issue involves inductors. Expressions for trace resistance and inductance estimation of on-chip planar spiral inductor on top metal layer of CMOS process are compared. These inductors have high series resistance due to low metal trace thickness, capacitive coupling with substrate and other metal traces, and eddy current loss. As an alternative, a CMOS compatible three-dimensional (3-D) surface micromachining technology known as plastic deformation magnetic assembly (PDMA) is used to fabricate high quality inductors with small footprints. Experimental results from a monolithic buck converter using this PDMA inductor are presented. A major conclusion of this work is that the 3-D "post-process" technology is more viable than traditional integrated circuit assembly methods for realizing of micro-power converters.

Low-Voltage-Swing Monolithic dc–dc Conversion

A low-voltage-swing MOSFET gate drive technique is proposed in this paper for enhancing the efficiency characteristics of high-frequency-switching dc-dc converters. The parasitic power dissipation of a dc-dc converter is reduced by lowering the voltage swing of the power transistor gate drivers. A comprehensive circuit model of the parasitic impedances of a monolithic buck converter is presented. Closed-form expressions for the total power dissipation of a low-swing buck converter are proposed. The effect of reducing the MOSFET gate voltage swings is explored with the proposed circuit model. A range of design parameters is evaluated, permitting the development of a design space for full integration of active and passive devices of a low-swing buck converter on the same die, for a target CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 to 0.9 V with a low-swing dc-dc converter based on a 0.18-/spl mu/m CMOS technology. The power dissipation of a low-swing dc-dc converter is reduced by 27.9% as compared to a standard full-swing dc-dc converter.