Modular Exponentiation Research Articles

A novel accelerated implementation of RSA using parallel processing

Past research has evidently proved that public key cryptosystems are usually slower than symmetric key cryptosystems due to the reason that they use one additional cryptographic key and different methods for encryption and decryption. RSA is one of the most common asymmetric key cryptography algorithms. Recent research has focused on speeding up RSA using various techniques. With the introduction of distributed computing, parallelization of algorithms enables them to run on multiple cores concurrently at a time. RSA consists of two resource intensive operations namely Modular Exponentiation of up to 1024-bit exponents and repeated calculation of Greatest common divisor. Thus, RSA lays the perfect base for application of Montgomery Reduction algorithm to optimize the Repeated Modular multiplication in exponentiation. In this paper we proposed a parallel scheme for RSA using a new parallel data structure known as Concurrent Indexed List of character blocks. The aim of our research was to improve the speed of RSA encryption and decryption using parallelism and also make it compatible with leading industry cryptography standards. We have simulated four different approaches namely both parallel and sequential with and without Montgomery. We have also integrated our parallel paradigm with renowned C++ Crypto library and achieved a speed-up of upto four times than sequential approach. Unlike any other previous approaches, our implementation got easily integrated with any external library and thus can be adopted by any other algorithmic scheme.

Cost effective FPGA Implementation of Right-to-Left Modular Exponentiation with NAF-Representation

Modular exponentiation is an exponentiation performed over a modulus. It is useful in computer science, especially in the field of public-key cryptography. Most technological applications of modular arithmetic involve exponentials with very large numbers. In this paper, we propose a high radix reconfigurable implementation for the Right-to-Left Modular Exponentiation with NAF-Representation by exploiting the maximum possible parallelism of the internal operations. The proposed design targeted the ALTERA Cyclone IV FPGA (EP4CGX22CF19C7) along with Quartus II simulation package. The proposed design was evaluated in terms of the maximum operational frequency, the total path delay, the total design area and the total thermal power dissipation. The synthesized results revealed that the proposed high radix architecture implementation has recorded: critical path delay of 25.5 ns, maximum operational frequency of 44.59 MHz, hardware design area (number of logic elements) of 2556 LEs, and total thermal power dissipation estimated as 221.82 mW. Consequently, the proposed modular exponentiation architecture can be efficiently employed by many public key cryptographic mechanisms.

A Practical Collision-Based Power Analysis on RSA Prime Generation and Its Countermeasure

We analyze the security of RSA prime generation implemented on embedded devices by a practical power analysis attack. Unlike previous differential power analysis-based attack on primality tests of RSA prime generation exploiting the deterministic relationship among multiple prime candidates manipulated by consecutive primality tests, we propose a collision-based power analysis attack on the Miller-Rabin test for a single prime candidate which can recover the secret prime with a single attempt by exploiting collision characteristics of simple power analysis resistant modular exponentiation algorithms. Hence, our attack does not require the incremental prime search assumption and is applicable when countermeasures against previous attacks are deployed since it also does not require the assumption of trial divisions with small primes on prime candidates. For a realistic setting, where five 512-bit modular exponentiations are operated on an ARM Cortex-M4 microcontroller as recommended by FIPS 186-4 standard, we successfully recover the secret exponent to an extent that a feasible exhaustive search is needed for the full recovery of the secret prime. This is a first practical result of recovering a full secret of modular exponentiation which manipulates 512-bit RSA primitives with collision-based power analysis in a single attempt, where the previous attack demonstrates the result for 192-bit ECC primitive implementations. We also present a countermeasure against our attack which requires only one additional modular subtraction for the loop of square-and-multiply-always exponentiation algorithm. An experimental result for the effectiveness of our proposed countermeasure is presented.

An Efficient ABE Scheme With Verifiable Outsourced Encryption and Decryption

Attribute-based encryption (ABE) is a promising cryptographic tool for data owner (DO) to realize fine-grained date sharing in the cloud computing. In the encryption of most existing ABE schemes, a substantial number of modular exponentiations are often required; the computational cost of it is growing linearly with the complexity of the access policy. Besides, in the most existing ABE with outsourced decryption, the computation cost of generating transformation key is growing linearly with the number of attributes associated with user private key; these computations are prohibitively high for mobile device users, which becomes a bottleneck limiting its application. To address the above issues, we propose a secure outsourcing algorithm for modular exponentiation in one single untrusted server model and a new method to generate the transformation key. Based on these techniques and Brent Waters's ciphertext-policy ABE scheme, we propose an ABE scheme with verifiable outsourced both encryption and decryption, which can securely outsource encryption and decryption to untrusted encryption service provider (ESP) and decryption service provider (DSP), respectively, leaving only a constant number of simple operations for the DO and eligible users to perform locally. In addition, both DO and the eligible users can check the correctness of results returned from the ESP and the DSP with a probability, respectively. Finally, we provide the experimental evaluation and security analysis of our scheme, which indicates that our construction is suitable for the mobile environment.

DESIGN OF A HIGH SPEED HYBRID TRANSISTOR LOGIC (HTL) MULTIPLIER USING HTL ADDER

Ponte Academic JournalNov 2019, Volume 75, Issue 11 DESIGN OF A HIGH SPEED HYBRID TRANSISTOR LOGIC (HTL) MULTIPLIER USING HTL ADDERAuthor(s): P. Manju ,T. MadhaviJ. Ponte - Nov 2019 - Volume 75 - Issue 11 doi: 10.21506/j.ponte.2019.11.7 Abstract:In cryptographic applications modular multiplications are most widely used. This modular multiplication depends on the addition and shifting operations. While performing iteration operation in modular multiplication, right shift operation with complete word architecture is performed. In the same way arithmetic unit is used in the multiplier to perform the arithmetic operations. While designing arithmetic unit, optimized multipliers are used most widely. Here a high speed hybrid multiplier using hybrid transistor logic adder is presented in this paper. This advanced Montgomery modular multiplication is based on the modular exponentiations to obtain high speed. The Montgomery multiplication uses adequate hardware implementation. The hybrid transistor logic multiplier system not only depends on the modular exponentiations but also depends on the modular multiplication to reduce the delay. Hence compared to Hybrid transistor logic adder system, the hybrid transistor logic multiplier system gives effective results in terms of speed, area and delay. Download full text:Check if you have access through your login credentials or your institution Username Password

Efficient parallel semi-systolic array structure for multiplication and squaring in GF(2<i><sup>m</sup></i>)

In this paper, we develop an efficient parallel semi-systolic array structure to concurrently compute multiplication and squaring operations in the binary extension field, GF(2m), for efficient modular exponentiations. The proposed array is well suited to VLSI implementation that it has a regular structure as well as local communications between its processing elements. The obtained results show that the proposed array structure achieves a significant reduction in area-time (AT) complexity by at least 95.9% over the corresponding existing structures.

A Lightweight and Efficient Secure Hybrid RSA (SHRSA) Messaging Scheme With Four-Layered Authentication Stack

For virtual private network and LAN-to-LAN tunnel sessions, End-to-End security is the main constraint in private messaging scenarios. Internet Protocol Security can negotiate new keys for every communication, but when the key is compromised, it is a problem. Perfect Forward Secrecy is the resolution. In addition, the messaging scheme should be efficient and lightweight for keeping parity with daily needs. The popular Rivest-Shamir-Adleman (RSA) cipher is omnipresent in secure communications but has many scientific problems. So here, in this paper, a lightweight and efficient Secure Hybrid RSA (SHRSA) messaging scheme with four-layered authentication stack is implemented and analyzed. The scheme is resolving the problem of asymptotic very low speed of decryption of RSA, the computational modular exponentiation complexity and partial key exposure vulnerability issues of RSA, and many more. The four-layered authentication stack have eliminated the need of the use of any password, external digital certificates, and a third party for authentication with its own four techniques in a staked way. We have found that in evolutions and analysis of the scheme, it is not only resolving various scientific problems of RSA but also occupying 2%–4% less CPU than main RSA and occupying 1%–3% less memory than main RSA. Its decryption average time has gained 8.858 times compared to the main RSA and gained 2.248 times compared to CRT RSA. We have found that the RSA, CRT-RSA, and SHRSA’s encryption throughput are alike-all are around 6 KB/Sec but decryption throughput of SHRSA has gained 8.5345 times than main RSA and gained 2.1174 times than CRT-RSA. The results obtained have shown us the relevancies of the SHRSA messaging scheme to be integratable as a cipher in Blockchain architectures, cyber-physical systems, and the Internet of Everything.

Fast and Area Efficient Implementation of RSA Algorithm

Abstract Efficient hardware implementations of public-key cryptosystems have been gaining interest in the past few decades. To achieve the goal, a high frequency as well as low latency Rivest-Shamir-Adleman (RSA) cryptosystem is reported in this paper. To configure such cryptosystem shift-add multiplier have been re-constructed and binary digit based modular exponentiation circuitry is proposed. Such exponentiation circuitry has been implemented through binary bit distribution technique, where, most significant bit (MSB) has been discarded for the implementation, owing to increase the operating frequency. The functionality of the reported algorithms were justified and compared in Hardware Description Language (HDL), simulated in Modelsim and synthesized in Xilinx ISE 14.2 platform. The proposed hardware implementation of RSA algorithm has a maximum frequency of operation of 545 MHz and 298 MHz for the bit sizes of 8 and 64 respectively. The proposed method shows improvements in terms of speed as well as in number of Look-up-tables (LUTs). Moreover, application-specific integrated circuit (ASIC) implementation of such cryptosystem of RSA was carried out through Encounter® RTL Compiler v11.10-p005_1 of Cadence® tool.

Lossy Identification Schemes from Decisional RSA

Lossy identification schemes derive tightly secure signature schemes via the Fiat-Shamir transformation. There exist several instantiations of lossy identification schemes by using several cryptographic assumptions. In this paper, we propose a new construction of lossy identification scheme from the decisional RSA assumption which are introduced by Groth. Our lossy identification scheme has efficient response algorithm because it requires no modular exponentiation.

Efficient Fixed-base exponentiation and scalar multiplication based on a multiplicative splitting exponent recoding

Digital signature algorithm (DSA) (resp. ECDSA) involves modular exponentiation (resp. scalar multiplication) of a public and known base by a random one-time exponent. In order to speed up this operation, well-known methods take advantage of the memorization of base powers (resp. base multiples). Best approaches are the Fixed-base radix-R method and the Fixed-base Comb method. In this paper, we present a new approach for storage/online computation trade-off, by using a multiplicative splitting of the digits of the exponent radix-R representation. We adapt classical algorithms for modular exponentiation and scalar multiplication in order to take advantage of the proposed exponent recoding. An analysis of the complexity for practical size shows that our proposed approach involves a lower storage for a given level of online computation. This is confirmed by implementation results showing significant memory saving, up to 3 times for the largest NIST standardized key sizes, compared to the state-of-the-art approaches.

A new VRSA‐based pairing‐free certificateless signature scheme for fog computing

SummaryFog computing is composed of various computers with weak performance instead of servers with strong performance. As history has shown, there has not been a general pairing‐free certificateless signature scheme that is mainly designed with modular exponentiation and modular multiplication that can possess resistance to Type I and Type II adversaries. The lightweight certificateless signature algorithm with low requirements for computing and storage capabilities, which can be practicably implemented in fog computing, needs to be studied. Therefore, a new hard mathematic problem is firstly defined in this paper, which is called variant of RSA problem. Then, a new general pairing‐free certificateless signature scheme is proposed based on the variant of RSA problem and the discrete logarithm problem. Fortunately, the proposed scheme is the first RSA‐based certificateless signature scheme that can possess resistance to Type I and Type II adversaries. A formal security proof is provided to demonstrate that, under adaptively chosen message attacks, the scheme is provably secure against Type I and Type II adversaries in the random oracle model. When compared with other known pairing‐free certificateless signature schemes of the same type, the computation cost of our scheme is slightly higher; however, a higher security level can be achieved.

An IBE Scheme with Verifiable Outsourced Key Generation Based on a Single Server

ABSTRACTIt is well known that private key generation is a computing bottleneck in an identity-based encryption scheme when a large number of users exist. Outsourcing computation can greatly reduce the users’ computational cost, but the existing schemes are all based on two servers, which are not feasible in the real cloud environment. In this paper, we first propose a scheme where the PKG outsources the task of private key generation to a single server, and the results can be verified effectively. Moreover, PKG only needs to execute 1 modular exponentiation, so it is more efficient when compared with previous schemes. Meanwhile, we prove the indistinguishability of the ciphertext and verifiability of the outsourcing results in the security model. Finally, the proposed algorithm is realized in a simulation environment. Theoretical analysis and experimental results show that total computing time of PKG and the server in the outsourced algorithm is far less than that of direct computation.

Fast and Secure Implementation of Modular Exponentiation for Mitigating Fine-Grained Cache Attacks

Constant-time technique is of crucial importance to prevent secrets of cryptographic algorithms from leakage by cache attacks. In this paper, we propose Permute-Scatter-Gather, a novel constant-time method for the modular exponentiation that is used in the RSA cryptosystem. On the basis of the scatter-gather design, our method utilizes pseudo-random permutation to obfuscate memory access patterns. Based on this strategy, the resistance against fine-grained cache attacks is ensured, i.e., providing the higher level of security than the existing scatter-gather implementations. Evaluation shows that our method outperforms the OpenSSL library at most 11% in the mainstream Intel processors.

Chaotic Map-Based Anonymous User Authentication Scheme With User Biometrics and Fuzzy Extractor for Crowdsourcing Internet of Things

The recent proliferation of mobile devices, such as smartphones and wearable devices has given rise to crowdsourcing Internet of Things (IoT) applications. E-healthcare service is one of the important services for the crowdsourcing IoT applications that facilitates remote access or storage of medical server data to the authorized users (for example, doctors, patients, and nurses) via wireless communication. As wireless communication is susceptible to various kinds of threats and attacks, remote user authentication is highly essential for a hazard-free use of these services. In this paper, we aim to propose a new secure three-factor user remote user authentication protocol based on the extended chaotic maps. The three factors involved in the proposed scheme are: 1) smart card; 2) password; and 3) personal biometrics. As the proposed scheme avoids computationally expensive elliptic curve point multiplication or modular exponentiation operation, it is lightweight and efficient. The formal security verification using the widely-accepted verification tool, called the ProVerif 1.93, shows that the presented scheme is secure. In addition, we present the formal security analysis using the both widely accepted real-or-random model and Burrows–Abadi–Needham logic. With the combination of high security and appreciably low communication and computational overheads, our scheme is very much practical for battery limited devices for the healthcare applications as compared to other existing related schemes.

Secure outsourcing algorithms of modular exponentiations with optimal checkability based on a single untrusted cloud server

Modular exponentiation is an expensive discrete-logarithm operation, difficult for resource-constrained users to perform locally. Fortunately, thanks to burgeoning cloud computing, users are willing to securely outsourcing modular exponentiations to cloud servers to reduce computation overhead. In this paper, we contrive a fully verifiable secure outsourcing scheme for modular exponentiation with only a single server, named MExp. MExp not only prevents users’ private information leakage during outsourcing by our new logical division method, but also eliminates collusion attacks occurring in algorithms with two untrusted servers. Moreover, our MExp allows outsourcers to detect any misbehavior with a probability of 1, which shows significant improvement in checkability when compare to other single-server-based schemes. With a view to reducing computation overhead, MExp is extended to multiple modular exponentiations, named M2Exp. The algorithm significantly diminishes the local costs of multiple modular exponentiation calculations and the checkability is still 1. Compared with existing state-of-the-art schemes, MExp and M2Exp have outstanding performance in both efficiency and checkability. Finally, MExp and M2Exp are applied to Cramer–Shoup encryptions and Schnorr signatures.

Privacy-preserving composite modular exponentiation outsourcing with optimal checkability in single untrusted cloud server

Outsourcing computing allows users with resource-constrained devices to outsource their complex computation workloads to cloud servers, which is more economical for cloud customers. However, since users lose direct control of the computation task, possible threats need to be addressed, such as data privacy and the correctness of results. Modular exponentiation is one of the most basic and time-consuming operations but widely applied in the field of cryptography. In this paper, we propose two new and efficient algorithms for secure outsourcing of single and multiple composite modular exponentiations. Unlike the algorithms based on two untrusted servers, we outsource modular exponentiation operation to only a single server, eliminating the possible collusion attack with two servers. Moreover, we put forward a new mathematical division method, which hides the base and exponent of the outsourced data, without exposing sensitive information to the cloud server. In addition, compared with other state-of-the-art algorithms, our scheme shows a remarkable improvement in checkability, enabling the user to detect any misbehavior with the optimal probability close to 1. Finally, we use our proposed algorithms as a subroutine to realize Shamir's Identity-Based Signature Scheme and Identity-Based Multi-Signatures Scheme.

A generic Private Information Retrieval scheme with parallel multi‐exponentiations on multicore processors

SummaryPrivate Information Retrieval (PIR) enables the data owners to share and/or retrieve data on remote repositories without leaking any information as to which a data item is requested. Although it is always possible to download the entire dataset, this is clearly a waste of bandwidth. A fundamental approach in the literature for PIR is exploiting homomorphic cryptosystems. In these approaches, not one but many modular exponentiations need to be computed and multiplied to obtain the desired result. This multi‐exponentiation operation can be implemented by exponentiating the bases to their corresponding exponents one‐by‐one. However, when the operation is considered as a whole, it can be performed in a more efficient way. Although individual exponentiations are pleasingly parallelizable, the combined multi‐exponentiation requires a careful parallel implementation. In this work, we propose a generic tensor‐based PIR scheme and efficient and novel techniques to parallelize multi‐exponentiations on multicore processors with perfect load balance. The experimental results show that our load balancing techniques make a parallel multi‐exponentiation up to %27 faster when the size of the bases and the exponents are 4096 bits and the number of threads is 16.

A Survey of Lattice Attack on Digital Signature Algorithm

Lattice-based cryptography is the use of conjectured hard problems on point lattices in 𝑹𝒏 as the foundation for secure cryptographic systems. The Digital Signature Algorithm (DSA) computes a modular exponentiation with a per-message ephemeral secret. This involves a sequence of modulo square and multiply operations which, if known, leaks few bits of per-message ephemeral secret key which can be used in lattice based attack to obtain the DSA private key. This work surveys most of the major developments in lattice based attack on DSA with their pros and cons.

Computation of the 100 quadrillionth hexadecimal digit of π on a cluster of Intel Xeon Phi processors

Abstract This paper presents the computation of a specific hexadecimal digit of π by using a Bailey–Borwein–Plouffe (BBP)-type formula on a cluster of Intel Xeon Phi processors. The BBP-type formula can be computed using modular exponentiation. We use Montgomery multiplication for the modular multiplication, which is the most time-consuming part of the modular exponentiation. We vectorize multiple modular exponentiations and multiple integer divisions by using Intel Advanced Vector Extensions 512 (Intel AVX-512) instructions. A parallel implementation of the BBP-type formula is presented. The 100 quadrillionth hexadecimal digit of π was computed on a 512-node cluster of Intel Xeon Phi processors with an elapsed time of 641 h 29 min that includes the time required for verification.

From theory to practice: horizontal attacks on protected implementations of modular exponentiations

Nowadays, horizontal or single-shot side-channel attacks against protected implementations of RSA and similar algorithms constitute a theoretic threat against secure devices. Nevertheless, in practice their application remains very difficult not only because of their complexity, but also because of environmental countermeasures integrated by designers that render their application even more difficult. Horizontal side-channel attacks take place in multiple steps. Among them, the most important are the acquisition of a complete trace with a sufficiently high sampling rate, its cutting into regular patterns, the realignment of the obtained patterns, the reduction as far as possible of noise in the acquired trace, the identification of the points of interest and the application of an effective distinguisher. Each of these steps is crucial and leads, if performed without enough attention, to an unsuccessful attack. In this context, this paper introduces effective solutions to efficiently perform all these steps, i.e., practicable means for implementing efficient horizontal attacks.