Modeling And Analysis Of Real-Time And Embedded Research Articles

Combining UML-MARTE and Preemptive Time Petri Nets: An Industrial Case Study

We present an approach for integration of formal methods within an industrial SW process, illustrating results obtained in a real scenario subject to Military Standard 498 (MIL-STD-498). On the one hand, the formal nucleus of preemptive Time Petri Nets (pTPNs) is used to support design and verification activities of the development process; on the other hand, the Unified Modeling Language (UML) profile for Modeling and Analysis of Real-Time and Embedded (MARTE) systems is adopted to manage the documentation process prescribed by MIL-STD-498. The two cores are integrated by providing guidance for translation of UML-MARTE specifications into equivalent pTPN models, with specific reference to concurrency control and synchronization mechanisms. This permits to attain a smooth transition from the standard artifacts of MIL-STD-498 to pTPN models and analyses, facilitating deployment of the formal core of pTPNs with a limited impact on the industrial practice. The experience proves practical feasibility and effectiveness of the approach, comprising a step towards industrial applicability of formal methods and practices.

Towards Formalizing Time-Constrained System Models in TCOZ

This study is concerned with using Unified Modeling Language (UML) model and the UML profile for Modeling and Analysis of Real-Time and Embedded (MARTE) systems to depict a Time-Constrained System (TCS). To perform system formal analysis, TCS models are transformed to Timed Communicating Object Z (TCOZ) specifications. The mapping rules for the modeling elements especially time-related issues are given at meta-model level. Static model, dynamic model and MARTE stereotypes in TCS models can be transformed to TCOZ models respectively. These models are composed together to complete specifications according to some rules. Hence the dependability of the TCS can be checked through the reasoning mechanism in TCOZ. A case study shows the applicability and feasibility of our approach.

Modeling UML sequence diagrams using extended Petri nets

Unified modeling language (UML) sequence diagrams combined with the UML profile for modeling and analysis of real-time and embedded (MARTE) systems are used to represent systems' requirements. To enhance formal analysis abilities, sequence diagrams annotated with MARTE stereotypes are mapped into timed colored Petri nets with inhibitor arcs (TCPNIA). The mapping rules for the fragments of sequence diagrams and MARTE stereotypes are proposed respectively. They are proposed both in graphical and formal forms. The soundness of mapping rules is analyzed. The data related issues are handled through colored properties in TCPNIA models, guard functions and operational functions. A mapping rule for state invariant is proposed based on data related information. Through state invariant, complicated control relations can be expressed. Formal definitions for morphing and substitution in TCPNIA models are given. They provide modular and hierarchical modeling methods for TCPINA models. To show the applicability and feasibility of our method, an application example in vehicular ad hoc networks (VANETs) domain is studied.

An MDE Approach for Automatic Code Generation from UML/MARTE to OpenCL

To reduce the design complexity of OpenCL programming, the approach proposed here generates application code automatically, based on model-driven engineering (MDE) and modeling and analysis of real-time and embedded (MARTE) systems. The aim is to provide application-development resources for nonspecialists in parallel programming, exploiting concepts such as reuse and platform independence.

Design and implementation of real-time EP80579 based embedded system

With the advances in integration of different units such as I/O controllers and network interfaces in a single chip, Intel introduced the low power EP80579 embedded processor. This processor is the first IA based system-on-chip (SoC) with an IA-32 processor core, North and South Bridges, and integrated Accelerator and network interface. In this paper we will show main steps to design a real-time embedded system along with identifying the hardware and software requirements to implement such system. The embedded system introduced in this work will perform several tasks regarding road surface conditions based on multiple sensor readings. The sensor data will be processed in real-time to reconstruct the road profile and provide an estimate for the texture contents of the road surface. The EP80579 SoC will be used in the design of such a system. Modeling will be done with the aid of UML profile for modeling and analysis of real-time and embedded (MARTE) systems.

Specification and verification of time requirements with CCSL and Esterel

The UML Profile for Modeling and Analysis of Real-Time and Embedded (MARTE) systems has recently been adopted by the OMG. Its Time Model extends the informal and simplistic Simple Time package proposed by UML2 and offers a broad range of capabilities required to model real-time systems including discrete/dense and chronometric/logical time. MARTE OMG specification introduces a Time Structure inspired by Time models of the concurrency theory and proposes a new clock constraint specification language (CCSL) to specify, within the context of UML, logical and chronometric time constraints. This paper introduces the formal semantics of a fundamental subset of CCSL clock constraints and proposes a process to use CCSL both as a high-level specification language for UML models and as a golden model to verify the conformance of implementations with the specification. A digital filtering video application is used as a running example to support the discussion. The application is first formally specified with CCSL and the specification is refined based on feedback from our CCSL-dedicated simulator. In a second phase, an Esterel program of the application is considered. This program is instrumented with observers derived from the CCSL specification. Esterel Studio formal verification facilities are then used to check the conformity of the Esterel implementation with the CCSL specification. A specific library of Esterel observers has been built for this purpose.

Performance Evaluation of UML2-Modeled Embedded Streaming Applications with System-Level Simulation

This article presents an efficient method to capture abstract performance model of streaming data real-time embedded systems (RTESs). Unified Modeling Language version 2 (UML2) is used for the performance modeling and as a front-end for a tool framework that enables simulation-based performance evaluation and design-space exploration. The adopted application meta-model in UML resembles the Kahn Process Network (KPN) model and it is targeted at simulation-based performance evaluation. The application workload modeling is done using UML2 activity diagrams, and platform is described with structural UML2 diagrams and model elements. These concepts are defined using a subset of the profile for Modeling and Analysis of Realtime and Embedded (MARTE) systems from OMG and custom stereotype extensions. The goal of the performance modeling and simulation is to achieve early estimates on task response times, processing element, memory, and on-chip network utilizations, among other information that is used for design-space exploration. As a case study, a video codec application on multiple processors is modeled, evaluated, and explored. In comparison to related work, this is the first proposal that defines transformation between UML activity diagrams and streaming data application workload meta models and successfully adopts it for RTES performance evaluation.