Transistor Model Research Articles

An Improved Dual-Gate Compact Model for Carbon Nanotube Field Effect Transistors with a Back-Gate Effect and Circuit Implementation

Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) compact model. The functional relationship between the back-gate voltage (Vbg) and threshold voltage (Vth) is derived. And a voltage reference regulation mechanism is adopted so that the back-gate effect can be accurately reflected in the DC transfer characteristics. The influence of gate voltage and drain voltage on transmission probability is analyzed. Meanwhile, the drain current is optimized by modifying the mobility equation. This compact model is built based on Verilog-A hardware language and supports the Hspice simulation tool. Within the supply voltage of 2 V, the simulation results of the proposed compact model are in good agreement with the measurement results. Finally, based on the compact model, an operational amplifier is designed to verify its correctness and feasibility in analog integrated circuits. When the power supply voltage is 1.8 V, and the load capacitance is 2 pF, the gain is 11.8 dB, and the unit-gain-bandwidth (UGB) is 214 kHz, which proves the efficiency of our compact model.

Incorporation of total ionizing dose effects into a compact model for p-GaN gate high electron mobility transistors

Total ionizing dose (TID) characteristics of p-GaN gate high electron mobility transistors (HEMTs) under different bias conditions are explored in this work. Potential mechanism accounting for the TID response of p-GaN gate HEMTs is analyzed, based on which a TID effects model is developed. The TID effects model describes the relationship among threshold voltage of p-GaN gate HEMTs, total radiation dose, and electric field inside the p-GaN cap layer. Furthermore, an approach incorporating the TID effects model into Advanced Spice Model for HEMT (ASM-HEMT) is proposed, the reliability of which is validated by the well-fitted modeled results in comparison with the measured ones. This approach makes it possible to probe into the impact of TID effects on p-GaN gate HEMTs from the perspective of circuit level, which provides a basis for the follow-up GaN-based circuit design.

Gate-controlled near-surface Josephson junctions

Gate-tunable Josephson junctions are interesting for quantum technology applications, such as gatemon qubits and topological Majorana-based qubits. Furthermore, high-frequency compatible geometries can be utilized for implementing electrically pumped parametric amplifiers. In this paper, we combine processing, measurements, and modeling of near-surface InGaAs Josephson field-effect transistors in order to facilitate circuit simulations of actual non-ideal devices. We developed a compact model using Verilog-A and confirmed the validity of our model by accurately reproducing our measured data by circuit simulations in Advanced Design System. From the circuit simulations, an effective gate-dependent transmission coefficient, with a peak value of ∼ 3.5%, was extracted, mainly limited by contact transparency.

Current-Mode Shadow Filter with Single-Input Multiple-Output Using Current-Controlled Current Conveyors with Controlled Current Gain.

In this paper, a novel current-mode shadow filter employing current-controlled current conveyors (CCCIIs) with controlled current gains is presented. The CCCII-based current-mode shadow filters are resistorless and can offer a number of advantages such as circuit simplicity and electronic tuning capability. The proposed shadow filters offer five filtering functions, i.e., low-pass, high-pass, band-pass, band-stop, and all-pass functions, in the same topology. Furthermore, no component matching condition is required to realize all the transfer functions. The natural frequency and quality factor adjustment is possible by using the CCCII current gains without the need to use external amplifiers, all capacitors are grounded, and the filter terminals offer low-input and high-output impedance. To verify the functionality and feasibility of the new topologies, the proposed circuits were simulated using SPICE and the transistor model process parameters NR100N (NPN) and PR100N (PNP) from AT&T's bipolar arrays ALA400-CBIC-R. The simulation results are consistent with the theory. The CCCII experimental setup was designed using commercially available 2N3904 (NPN) and 2N3906 (PNP) transistors with a supply voltage of ±2.5 V. The measurement results confirm the performance of the designed filters.

Compact Model of a Topological Transistor

Compact Model of a Topological Transistor

Compact Modeling of LDMOS Transistors Over a Wide Temperature Range Including Cryogenics

Compact Modeling of LDMOS Transistors Over a Wide Temperature Range Including Cryogenics

Circuit simulation-based comparison of power electronics devices in a five-level converter for UAV applications

<p>In this paper, the performance of a 5-level cascaded H-bridge inverter in unmanned aerial vehicle (UAV) applications is analized to identify, at the converter design stage, the better device choice depending on different UAV operation scenarios. Considering that regardless of the specific application there are some typical operations, such as take-off, climb, land, cruise, and potential recurring climbs and descents, the results can support the choice by considering the typical working conditions of the specific application where the UAV would be used. The results have been obtained by simulating the H-bridge inverter considering the circuit models of insulated-gate bipolar transistors (IGBTs), GaN high-electron-mobility transistors (HEMTs), and Si and SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) provided by manufacturers. The study has highlighted that the choice of the device depends on the UAV usage, switching frequency, and load conditions. More specifically, considering the typical devices and systems costs in the case of a selective harmonic elimination procedure operating at the fundamental switching frequency, the Si devices should be used. Moreover, the preference for using IGBTs or Si MOSFETs depends on the typical working conditions of the UAV application. In the case of phase-shift carrier modulation technique, at 4 kHz the MOSFET is the best device and the choice between Si and SiC devices depends on the UAV application's main operation scenarios. At 20 kHz the SiC MOSFET is the best device, while at higher frequencies the GaN HEMT cost should be faced to take advantage of its best performance.</p>

Design-Oriented Single-Piece Explicit I-V DC Charge-Based Model for MOS Transistors in Nanometric Technologies

Design-Oriented Single-Piece Explicit <i>I</i>-<i>V</i> DC Charge-Based Model for MOS Transistors in Nanometric Technologies

Gaussian DOS Charge-Based DC Compact Modeling of High-Speed Organic Transistors

Gaussian DOS Charge-Based DC Compact Modeling of High-Speed Organic Transistors

Machine Learning-Assisted Compact Modeling of W-Doped Indium Oxide Channel Transistor for Back-End-of-Line Applications

Machine Learning-Assisted Compact Modeling of W-Doped Indium Oxide Channel Transistor for Back-End-of-Line Applications

Ohmic contact in two-dimensional WS2/Hf2CX2 (X = F/OH) and WS2/graphene/Hf2C heterojunctions

Low-resistance Ohmic contacts are the key to improving the performance of electronic devices. By performing ab initio electronic calculations and quantum transport simulations, we systematically investigate the contact types of the original WS2/Hf2C, the functionalized WS2/Hf2CX2 (X = F/OH), and the graphene-doped WS2/graphene/Hf2C heterojunctions. The obtained results suggest that the strong interfacial coupling occurs in the WS2/Hf2C system, leading to the metallization of the WS2 layer. Functionalization of the Hf2C layer can significantly weaken the interlayer interactions. Thus, the semiconductor characteristics of the WS2 layer can be maintained in the WS2/Hf2CX2 (X = F/OH) and WS2/graphene/Hf2C heterojunctions. Stable Ohmic contacts are formed in these heterojunctions. The heights of the vertical electron Schottky barrier are −0.13 eV, −0.43 eV, and −0.12 eV for WS2/Hf2CF2, WS2/Hf2C(OH)2, and WS2/graphene/Hf2C, respectively. Based on these heterojunctions, we construct a two-probe field-effect transistor model and explore its quantum transport properties. In the lateral direction, all systems form n-type Schottky contacts. This investigation provides a basis for the selection of electrode materials based on WS2 devices.

Review of RF Device Behavior Model: Measurement Techniques, Applications, and Challenges.

This review presents a concise overview of RF (radio frequency) power transistor behavior models, which is crucial for optimizing RF performance in high-frequency applications like wireless communication, radar, and satellites. The paper highlights the significance of accurate modeling in understanding transistor behavior and traces the evolution of behavior modeling techniques. Different behavior modeling strategies, such as LUT (look-up table) based models, polynomial equation-based models, and machine learning based models, are discussed along with their unique characteristics and modeling challenges. The review explores the difference between behavior models and the conventional empirical or physics-based modeling approaches, addressing the challenges of the accurate characterization of transistors at high frequencies and power levels. This paper concludes with an outlook of emerging trends, such as physical models combined with behavior models, shaping the future of RF power transistor modeling for more efficient communication systems.

A unified core model of double-gate and surrounding-gate MOSFETs for circuit simulation

This paper presents a new core compact model of double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs for circuit simulations. The current and the terminal charges are continuous with high computation efficiency and accuracy. Despite its accuracy, it retains the same simplicity of the industry standard transistors models. The drain current is worked out without invoking the charge-sheet approximation exploiting a quadratic symmetric polynomial interpolation of the charge in the channel. Apart this clear approximation, no other simplification is used to work out the drain current, the terminal charges, the potential, and electric field in the channel. The accuracy of the model is shown by comparison with the exact numerical solution and experimental data of the literature.

Low‐frequency noise model development of MoS2 field effect transistor and its analysis with respect to different traps

AbstractIn this paper, an analytical drain current model of double gate MoS2 FET Transistor for low‐frequency noise (LFN) power spectral density is developed, and compared its response with the device simulation of the proposed device structure. The developed low‐frequency noise power spectral density (PSD) model is analyzed with respect to different Trap densities, Oxide thicknesses, and high K‐dielectric materials using the TCAD Device simulation tool. Low‐frequency noise is one of the most important noises in any device since it degrades the device's performance. So, in this paper, we used a unique charge‐control model for analyzing the low‐frequency noise by considering the mobility degradation, trapping, and de‐trapping effects caused by trap densities and device lattice structure. Usually, all the previous studies on drain currents with low frequency are based on fluctuations caused by mobility and carrier variations. In our paper, we even considered the charge density fluctuation to analyze the drain current equation. Using a Charge Control Model, we can compute the parameters like gate capacitance (Cgs, Cgd), channel length modulation, and body effect. While other LFN models like the DC model, small signal model, and hybrid model will focus mainly on the static characteristics of the device such as its DC current–voltage (I‐V) relationship, terminal resistances, and input/output conductance of the devices. All the analytical model results were calibrated with the device simulation and it is observed that both are matches each other. Further, it is observed that with an increase in Trap density, the low‐frequency noise increases and low‐frequency noise is dominant at lower frequencies only (1–10 Hz), and after this frequency range the thermal noise will be the dominant noise factor.

Power losses in the MOSFET transistors of switching-mode converters

The power losses in the MOSFET transistors of switching-mode converters are investigated and analyzed. The results presented in this paper are achieved using software Cadence OrCAD. The simulation model suitable for estimation of energy dissipations in MOSFET transistors is proposed. The power losses as a function of different circuit’s parameters, like switching frequency, power supply voltage and output current are evaluated. The PSpice model of MOSFET transistor “BSC020N03MS” of the company Infineon is used in the presented analysis. Control circuit, which realize the adaptive deadtime (ADT) control technique depending on the load current, is applied to reduce the switching power losses in the MOSFET transistor. Thus, the efficiency of the switching-mode converters can be increased.

Modeling organic negative-transconductance transistors for circuit simulation

Abstract Organic negative-transconductance (NTC) transistors are emerging as a new versatile element of flexible and printed electronics. However, there is no standard model of these transistors available in circuit simulators. This paper introduces the first current–voltage model for organic NTC transistors. The model reflects unique structural features of a state-of-the-art NTC transistor platform, incorporating a p-type, an n-type, and a back-conduction channel into a single heterojunction architecture. The details of modeling approach and development are systematically illustrated. Then, the model is firmly validated by experimental data from a high-performance device. Finally, controllability over the abruptness of inter-regime transitions is emphasized as a key advantage of the model for the accuracy of fitting results. This compact, closed-form, and analytical model covering all regimes of operation bridges the gap between device- and circuit-level perspective of organic NTC transistors, promoting their integration into practical electronics technologies.

Simulation Modelling of Silicon Gated Field Emitter Based Electronic Circuits

Vacuum transistors (VTs) are promising candidates in electronics due to their fast response and ability to function in harsh environments. In this study, several oscillator and logic gate circuit simulations using VTs are demonstrated. Silicon-gated field emitter arrays (Si-GFEAs) with 1000 × 1000 arrays were used experimentally to create a VT model. First, transfer and output characteristics sweeps were measured, and based on those data, an LTspice vacuum transistor (VT) model was developed. Then, the model was used to develop Wein and Ring oscillator circuits. The circuits were analytically simulated using LTspice, where the collector bias voltage was 200 V DC, and the gate bias voltage was 30–40 V DC. The Wein oscillator circuit produced a frequency of 102 kHz with a magnitude of 26 Vpp. The Ring oscillator produced a frequency of 1.14 MHz with a magnitude of 4 Vpp. Furthermore, two logic circuits, NOR and NAND gates, were also demonstrated using LTspice modeling. These simulation results illustrate the feasibility of integrating VTs into functional integrated circuits and provide a design approach for future on-chip vacuum transistors applied in logic or radio-frequency (RF) devices.

The Modeling of GaN-FET Power Devices in SPICE

This paper focuses on the problem of the modeling of FET power transistors made of gallium nitride offered by GaN Systems, Transphorm, and Nexperia. The considered devices have been available on the market since 2014. GaN-FETs are built as a cascade connection of a normally on gallium nitride HEMT and a normally off MOSFET made of silicon. On the manufacturer’s sites, one can find models of these devices for like-SPICE tools in the text form. The main goal of this paper is to evaluate the model’s accuracy by comparing calculation results obtained by the use of the considered models with the authors’ measurement results and datasheet. It has been demonstrated that the GaN Systems model built on controlled sources described by a set of arbitrarily selected mathematical functions more accurately reproduces the basic characteristics of a transistor. On the other hand, the models from Transphorm and Nexperia, which are constructed based on built-in semiconductor device models, more precisely calculate the values of selected functional transistor parameters.

A Surface Potential Model for Metal-Oxide-Semiconductor Transistors Operating near the Threshold Voltage

Device physics and accurate transistor modeling are necessary to reduce the operating voltage near the threshold for power-constrained circuits. Conventional device modeling for metal-oxide-semiconductor (MOS) transistors focuses on operations in either strong or weak inversion regimes, and the electrostatics at gate biases near the threshold voltage is rarely studied. This research proposed an analytical model to describe the distribution of the surface potential along the channel for near-threshold operation. Numerical device simulations were also performed to investigate the electrostatics near the threshold voltage. The numerical simulation with constant carrier mobility showed an overshoot in the transconductance due to decay of the lateral electric field with gate bias. The decay of the lateral electric field was predicted by the proposed analytical surface potential model which considered widening the channel length with flooding of the inversion carriers in the channel and gate overlap regions. The channel length widening effect saturated as the gate bias further increased. Therefore, evident transconductance overshoot was observed near the threshold voltage in short-channel devices.

Analytical modeling of organic permeable-base transistors based on geometrical parametrization

Analytical modeling of organic permeable-base transistors based on geometrical parametrization