Min-sum Algorithm Research Articles

A Polygonal Line Min-Sum Decoding Scheme for Low Density Parity Check Codes

Low-density parity-check (LDPC) codes are widely used as error correction codes in new generation digital TV standards, such as the second generation of terrestrial digital video broadcasting standard (DVB-T2), Advanced Television Systems Committee (ATSC) 3.0, etc. The nonlinear belief propagation (BP) algorithm has excellent decoding performance for LDPC codes, but is often simplified in hardware implementations by linear min-sum (MS) algorithm due to its high complexity. This simplification also leads to over-estimation problems, which can be corrected by adding factors in conventional algorithms (e.g., normalized min-sum (NMS), offset min-sum (OMS), and variable scaling normalized min-sum (VMS) algorithms). However, the correction factors of these modified MS algorithms cannot adapt to different channels and modulations, and the performance needs further improvement. In this paper, the concepts of over-estimation value (OEV) and over-estimation rate (OER) are introduced to describe the over-estimation problem of the MS algorithm. Then, under the guidance of OEV and OER, a polygonal line min-sum (PMS) algorithm with correction factors adapted to different channels and modulations is proposed according to LLR distribution. Following the properties of OEV and OER, PMS algorithm is further simplified into Simplified PMS (SPMS) algorithm. LDPC codes from ATSC 3.0 are adopted in this paper to evaluate SPMS algorithm in comparison with the conventional algorithms. Extensive simulation results show that the SPMS algorithm for ATSC 3.0 LDPC decoder has at most 1.61dB, 0.24dB and 0.36dB gain over NMS, OMS and VMS algorithms respectively when frame error rate (FER) is at 10⁻⁴ level over additive white Gaussian noise (AWGN) channel with QPSK modulation. More importantly, the simulation results show that the SPMS algorithm can achieve much better performance than these modified MS algorithms over AWGN and Rayleigh channel with higher-order modulations or under limited maximum iteration number.

Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing

A practical min-sum algorithm is associated with tree-based comparison units for the check-node operation, being a major bottleneck in designing low-cost and energy-efficient low-density parity-check (LDPC) decoders. In this brief, we present a cost-effective LDPC decoder architecture by changing its internal computing resolution for the power-hungry check-node processing. The proposed mixed-resolution comparison offers significant advantages in terms of both area and energy, while achieving error-correcting performance within 0.3 dB of the previous normalized min-sum (NMS) algorithm for a (1644, 1408) quasi-cyclic LDPC code of the 5G New Radio specifications. Compared to the baseline NMS architecture, the proposed decoder in a 65-nm CMOS technology reduces the hardware complexity and the power consumption by 28.4% and 23.1%, respectively, enhancing the area efficiency by more than 88.2%.

Advanced ISDB-T and ATSC 3.0 LDPC Codes Performance and Complexity Comparison

This paper presents a comparative performance and complexity analysis of the advanced ISDB-T and ATSC 3.0 Low-Density Parity-Check (LDPC) codes using the Sum-Product Algorithm and Min-Sum Algorithm LDPC decoders. The performance value for each of the code rates of the LDPC codes over an additive white Gaussian noise (AWGN) channel and Rayleigh fading channel is presented. The mathematical representation of each of the SPA and MSA decoders is presented along with the calculated and measured numerical complexity values.

Reconfigurable Low-Density Parity-Check (LDPC) Decoder for Multi-Standard 60 GHz Wireless Local Area Networks

In this study, a reconfigurable low-density parity-check (LDPC) decoder is designed with good hardware sharing for IEEE 802.15.3c, 802.11ad, and 802.11ay standards. This architecture flexibly supports 12 types of parity-check matrix. The switching network adopts an architecture that can flexibly switch between different inputs and achieves a low hardware complexity. The check node unit adopts a switchable 8/16/32 reconfigurable structure to match different row weights at different code rates and uses the normalised probability min-sum algorithm to simplify the structure of searching for the minimum value. Finally, the chip is implemented using the TSMC 40 nm CMOS process, based on the IEEE 802.11ad standard decoder, extended to support the IEEE 802.15.3c standard, and upwardly compatible with the next-generation advanced standard IEEE 802.11ay. The chip core size was 1.312 mm × 1.312 mm, the operating frequency was 117 MHz when the maximum number of iterations was five with the power consumption of 57.1 mW, and the throughput of 5.24 Gbps and 3.90 Gbsp was in the IEEE 802.11ad and 802.5.3c standards, respectively.

High-Performance and Low-Complexity Decoding Algorithms for 5G Low-Density Parity-Check Codes

The development of the Fifth Generation (5G) New Radio (NR) provides several significant advantages when compared to the fourth generation (4G) Long Term Evolution (LTE) in mobile communications. Due to the outstanding characteristics of Low-Density Parity-Check (LDPC) codes such as high decoding performance, high throughput, low complexity, they have been accepted as the standard codes for the 5G NR. In this paper, we propose two LDPC decoding algorithms: Hybrid Offset Min-Sum (HOMS) and Variable Offset Min-Sum (VOMS), which are aimed at improving the error correction performance. The main idea of the HOMS/VOMS algorithm is to apply modified factors to both variable-nodes and check-nodes updated processing in order to compensate the extrinsic messages overestimation of the MS-based algorithms and increase the protection ability for degree-1 variable-nodes. The simulation results show that at the Bit-Error-Rate (BER) of 10-5, the proposed HOMS/VOMS algorithm achieves the decoding gain up to 0.2 dB compared to the Offset Min-Sum (OMS) algorithm, with a slight increase in decoding complexity.

Neural Layered Decoding of 5G LDPC Codes

In this letter, we propose various low-complexity neural layered min-sum (NLMS) algorithms to improve the decoding performance of the fifth generation (5G) new radio (NR) low-density parity-check (LDPC) codes. Our proposals are based on the computationally-efficient normalized offset min-sum (NOMS) approach for the layered belief propagation (LBP). The main novelty of our proposals is a deep neural network (DNN) that implements the layered mode decoding and that additionally learns the normalization and the offset parameters of the NOMS scheme. The schemes that we propose use the DNN as well as adaptation and filtering for estimating the optimum values of these parameters. We show by simulation that our proposed decoders achieve a significant computational benefit compared to the standard (non-neural) LBP decoder without an appreciable performance penalty.

High performance binary LDPC-coded OFDM systems over indoor PLC channels

Power line communication (PLC) technology is actually among the most renowned technologies for home environments due to their low-cost installation opportunities. In this study, the bit error rate (BER) performances of binary low-density parity check (LDPC) coded orthogonal frequency-division multiplexing (OFDM) systems have been considered over indoor PLC channels. Performances comparison of diverse soft and hard decision LDPC decoder schemes such as Min-Sum (MS), weighted bit flipping (WBF), gradient descent bit-flip (GDBF), noisy gradient descent bit-flip (NGDBF) and its few variants including the single-bit NGDBF (S-NGDBF), multi-bit NGDBF (M-NGDBF) and smoothed-multi-bit NGDBF (SM-NGDBF) decoders were examined in the modeled network. To evaluate the BER performance analyses three different PLC channel scenarios were generated by using new and more realistic PLC channel model proposal were also employed. All of the simulations performed in Canete’s PLC channel model showed that remarkable performance improvement can be achieved by using short-length LDPC codes. Especially, the improvements are striking when the MS or SM-NGDBF decoding algorithms are employed on the receiver side.

A Low-Complexity Decoder With Non-Uniform Quantization for Recursive BMST Codes

Recursive block Markov superposition transmission (rBMST) can be used to construct high-performance spatially coupled codes. When used in power-limited scenarios, low-complexity quantized decoders are required for the rBMST codes. In this letter, we introduce an efficient decoder for rBMST codes by incorporating non-uniform quantization (NUQ) into the threshold attenuated min-sum algorithm (TAMSA). The resulting decoder is referred to as the NUQ-TAMSA. We use the hierarchical dynamic quantization algorithm to design the non-uniform quantizer. To show the effectiveness of the NUQ-TAMSA, we carry out comprehensive comparisons. Our results show that, for low-resolution quantization, performance gains as large as 0.3 dB can be obtained with the NUQ-TAMSA. Numerical results also show that, for a wide range of coding rates, 5-bits non-uniform quantization is sufficient for NUQ-TAMSA to approach the performances of the floating-point based TAMSA.

NOLD: A neural-network optimized low-resolution decoder for LDPC codes

The min-sum (MS) algorithm can decode Low-density parity-check (LDPC) codes with low computational complexity at the cost of slight performance loss. It is an effective way to realize hardware implementation of the min-sum decoder by quantizing the floating belief messages (i.e., check-to-variable messages and variable-to-check messages) into low-resolution (i.e., 2–4 bits) versions. However, such a way can lead to severe performance degradation due to the finite precision effect. In this paper, we propose a neural-network optimized low-resolution decoding (NOLD) algorithm for LDPC codes to deal with the problem. Specifically, the optimization of decoding parameters (i.e., scaling factors and quantization step) is achieved in a hybrid way, in which we concatenate a NOLD decoder with a customized neural network. All learnable parameters associated with the decoding parameters are assigned to each neuron in the proposed method. What's more, we design a new activation function whose outputs are close to the employed quantizer ones when network parameters are finally optimized off-line. Finally, the performance of the proposed method is verified by numerous experiments. For the case of 2-bit decoding, the proposed approach significantly outperforms several conventional decoders at the expense of slightly increased off-line training time. Besides, the proposed method with 4-bit quantization incurs only 0.1 dB performance loss compared with the floating min-sum decoder at the coded bit-error-rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−5</sup> . Moreover, we show that the proposed NOLD decoder works over a wide range of channel conditions for regular and irregular LDPC codes. Simulation code for reproductive results is publicly available <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> .

Node-Subset Scheduling with a Subset-Reset Mechanism for the Decoding Algorithm of Nonbinary LDPC Codes

For the conventional extended min-sum (EMS) algorithm, all check nodes update their check-to-variable (C2V) messages in every iteration. Selected scheduling, which reduces the number of check nodes for message updating in one iteration, can effectively reduce the complexity of the decoding algorithm, but it also lead to some performance degradation. With the introduction of a metric based on node stability, we propose stability-based node-subset scheduling (SNS) for the EMS algorithm, which can improve the performance of node-subset scheduling (NS). Second, to further improve the decoding performance of SNS while maintaining low complexity, we propose the SNS-EMS algorithm with a subset-reset mechanism (RSNS-EMS) based on the abnormal stability found in the processing node subset, which will cause the estimated codeword to fail to converge. The RSNS-EMS algorithm enhances performance through a sliding window detection and reset mechanism, and it resets the elements in the processing node subset to force all check nodes to update new messages when abnormal stability is detected. The simulation results show that the proposed algorithm can reduce complexity by approximately 25% with negligible performance degradation.

Selection-based Low-cost Check Node Operation for Extended Min-Sum Algorithm

Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

Reduced-complexity offset min-sum check node unit for layered 5G LDPC decoder

This paper presents a novel approach for the reduced-complexity Min-Sum (MS) decoding of low density parity check (LDPC) codes in the partially parallel layered decoder architecture, which contains a large number of serial check node processors. Reduced complexity is obtained by using the variant of the single-minimum Offset Min-Sum (smOMS) algorithm that approximates a second minimum with the addition of the variable weight parameter to the minimum value. Although the reduced-complexity MS algorithms primarily reduce hardware resources in fully parallel implementations, the results showed that a considerable reduction can be obtained if serial check node processors are used. The paper also proposes a better subminimum estimation for irregular codes from 5G new radio (5G NR). The method uses smaller subminimum estimation weights in check nodes with a higher degree and higher weights in check nodes with a smaller degree, which leads to the significant improvement in the SNR performance. Additionally, it is shown that SNR performance can be further improved by applying offset before minimum calculation, which differs from conventional Min-Sum approaches.

Enhanced Quasi-Maximum Likelihood Decoding Based on 2D Modified Min-Sum Algorithm for 5G LDPC Codes

We propose a two-dimensional modified min-sum algorithm for the LDPC codes in the fifth generation (5G) networks standard to approach the error performance of the sum-product algorithm (SPA). In the proposed decoding algorithm, we adopt a partial self-correction method followed by message amplification to improve the reliability of the variable-to-check (V2C) messages. To further approach the performance of the maximum likelihood decoding for 5G short LDPC codes, we propose an enhanced quasi-maximum likelihood (EQML) decoding method. The proposed decoding method performs multiple rounds of decoding tests once the first decoding attempt fails, where the decoder inputs of the selected unreliable variable nodes are modified in each decoding test. A novel node selection method based on the sign fluctuation of V2C messages is proposed for the EQML decoding method. We also present a partial pruning stopping (PPS) rule to reduce the decoding complexity by deactivating part of the decoding tests once a valid codeword is found. A lower bound on the error performance is also derived by using the semi-analytical method. Simulation results show that the EQML decoding method outperforms the SPA with the same decoding complexity and other QML decoding methods, and it approaches the Polyanskiy-Poor-Verdu bound within 0.4 dB.

Optimization and Hardware Implementation of Learning Assisted Min-Sum Decoders for Polar Codes

Polar codes have received a lot of attention due to their capacity-achieving performance and low complexity. This paper proposes a novel scaling offset min-sum (SOMS) algorithm and adapts the offset min-sum (OMS) algorithm for polar codes, and both algorithms are improved via learning. For all message updates, conventional min-sum decoding algorithms use the same scaling factor or offset, which is usually obtained by numerical simulations. By modeling the data flow of min-sum algorithms as a deep neural network, the parameters used in the message passing updates of min-sum decoders can be different for each message update, and are obtained by training and optimizing the corresponding deep neural network. The simulation results show that the proposed SOMS algorithm based on deep learning performs better than all existing BP-based algorithms. Moreover, this paper presents an efficient hardware architecture of the proposed SOMS algorithm. The K-Means clustering algorithm is applied to reduce the number of possible parameters of the neural network, leading to reduced energy consumption and memory requirement with negligible error performance degradation. The proposed architecture of the SOMS algorithm for a (256,128) polar code is implemented and validated on the Xilinx Artix-7 field-programmable gate array.

Efficient Implementation of a Threshold Modified Min-Sum Algorithm for LDPC Decoders

In this brief, we present a hardware efficient implementation of a threshold modified min-sum algorithm (MSA) to improve the performance of a low density parity-check (LDPC) decoder. The proposed architecture introduces a novel lookup table based threshold attenuation technique, called threshold attenuated MSA (TAMSA). The proposed TAMSA implementation is shown to improve bit error rate (BER) performance compared to the conventional AMSA and MSA. Furthermore, a layered version of the TAMSA implementation is investigated to reduce hardware cost. Utilizing circuit optimization techniques, including a parallel computing structure, the proposed layered TAMSA field-programmable gate array (FPGA) implementation results show that the modified architecture requires no extra circuit power or circuit area compared to conventional AMSA, and only 0.07% extra leaf cells compared to conventional MSA.

A Threshold-Based Min-Sum Algorithm to Lower the Error Floors of Quantized LDPC Decoders

For decoding low-density parity-check (LDPC) codes, the attenuated min-sum algorithm (AMSA) and the offset min-sum algorithm (OMSA) can outperform the conventional min-sum algorithm (MSA) at low signal-to-noise-ratios (SNRs), i.e., in the “waterfall region” of the bit error rate curve. This paper demonstrates that, for quantized decoders, MSA actually outperforms AMSA and OMSA in the “error floor” region, and that all three algorithms suffer from a relatively high error floor. This motivates the introduction of a modified MSA that is designed to outperform MSA, AMSA, and OMSA across all SNRs. The new algorithm is based on the assumption that trapping sets are the major cause of the error floor for quantized LDPC decoders. A performance estimation tool based on trapping sets is used to verify the effectiveness of the new algorithm and also to guide parameter selection. We also show that the implementation complexity of the new algorithm is only slightly higher than that of AMSA or OMSA. Finally, the simulated performance of the new algorithm, using several classes of LDPC codes (including spatially coupled LDPC codes), is shown to outperform MSA, AMSA, and OMSA across all SNRs.

A 75-Gb/s/mm2 and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm

This article presents a high-throughput and low-routing complexity low-density parity check (LDPC) decoder design based on a novel second minimum approximation min-sum (SAMS) algorithm. The routing congestion is mitigated by reducing the required interconnections in the critical path of the routing network. The implementation and postlayout results with 28-nm 1P9M CMOS process show that the proposed design can achieve a throughput of 10.5 Gb/s for a millimeter-wave 60-GHz baseband system while satisfying the low bit error rate (BER) requirements (10−7). The proposed design reduces the wiring in the routing network by 21% and improves the area by 12% compared to the conventional min-sum (MS) and normalized MS (NMS) algorithm. Additional hardware optimizations are obtained by considering the internal message passing resolution based on the BER and signal-to-noise ratio (SNR) requirements for a practical baseband system. The power consumption is efficiently reduced by the employment of a shared address generator that exploits the degree of parallelism to reduce the switching activity on a group of memory elements. The LDPC decoder is implemented with a core area of 0.14 mm2, power consumption of 81 mW at 312.5 MHz, and the area and power efficiency of 75 Gb/s/mm2 and 10.2 pJ/bit, respectively.

Min-Sum Algorithm Using Multi-Edge-Type Normalized Scheme for ATSC 3.0 LDPC Decoders

To offer commercial LDPC decoders with better performance, in this paper, multi-edge-type (MET) normalized scheme is proposed to improve the performance of traditional min-sum algorithm (MSA) and its modified versions. With respect to sum-product algorithm (SPA), we firstly analyze and find out that the degradations of convergence in different edge types are distinct in MSA theoretically. To compensate the different degradations above, proposed MET-normalized scheme is used in normalized min-sum algorithm (MET-NMSA). In addition, MET-based density evolution (MET-DE) is also presented to search optimized MET-scaling factors for MET-NMSA. To further verify the validity of MET-normalized scheme, Advanced Television Systems Committee (ATSC) 3.0 LDPC codes are used to evaluate MET-NMSA in comparison with the conventional algorithms, i.e., normalized min-sum algorithm (NMSA), offset min-sum algorithm (OMSA) and variable-scaling normalized min-sum algorithm (VS-NMSA). Extensive simulation results show that MET-NMSA for ATSC 3.0 LDPC decoders has at most 1.53dB, 0.21dB and 0.35dB gain over NMSA, OMSA and VS-NMSA respectively when frame error rate (FER) is at 10-4 level over additive white Gaussian noise (AWGN) channels using QPSK modulation.

Low latency LDPC hard‐decision algorithm for 5G NR

In this study, the authors demonstrate the potential of hard-decision algorithm in industrial 5G NR channel coding. This study aims to show different forward error correction algorithms that can be expected in the context of cloud radio access network. Based on low density parity check (LDPC) min-sum (MS) algorithm, an improved hard-decision algorithm is proposed. The decoding process and performances are shown and compared with MS algorithm. To identify the advantage of this proposal, a test bench is launched in Cisco server using X86 chipset. Its results show a good trade-off between latency and performance.