Miller Capacitance Research Articles

Design and performance investigation of tunnel-FET based energy efficient approximate and accurate adders targeted towards low power IoT nodes

Abstract The proliferation of IoT enabled SoCs in state-of-the-art consumer electronics has necessitated the use of beyond CMOS devices for the energy efficient computations and sensing design space. In the low supply voltage (VDD) regime, Tunnel FETs (TFETs) have shown serious potential at VDD less than 0.5 V. However, the inherent structure, characteristic interband tunneling and enhance Miller capacitance in TFETs do not allow the conventional CMOS logic design styles to be universally used for TFET based logic circuits. In this paper, we propose three energy efficient and novel TFET based accurate adder circuits namely, Static Energy Recovery Full adder (SERF), Complementary and Level Restoring Carry Logic Full adder (CLRCL) and Balanced Restoring Carry Logic full adder (BRCL) based on constituent TFET based functional units which do not use the CMOS design style. Further, novel approximate adders have been developed for energy efficient implementation in IoT nodes. The BRCL adder consumes approximately 60% less area and 85.36% and 89.6% less energy in comparison to SERF and CLRCL respectively. The approximate adders in the best and worst case facilitate approximately 92% and 75% savings in area and consumes 71% less power than the BRCL adder. When compared to the standard UMC 45 nm bulk MOSFET based designs, the TFET based accurate adders operate at 25% less energy while the approximate adders consume 40% less. All the circuit simulations have been performed using Spectre Simulator of Cadence and device characterization using 2D-TCAD tool.

Study of A Heterojunction Double Gate Ferroelectric p-n-i-n Tunnel FET combining analytical modeling and TCAD simulation

A short channel Heterojunction Double Gate Ferroelectric p-n-i-n Tunnel Field Effect Transistor structure is proposed in this article to alleviate undesirable ambipolarity and Miller Capacitance and has a steeper subthreshold swing with improvement in ON state current compared to other conventional TFET structures. This work develops a physics based relevant analytical model of surface potential with the effect of gate fringing field and inclusive source and channel depletion region, drain current model, terminal charge and capacitance model to investigate its transient performance for the impact of ferroelectric polarization according to the Miller Ferroelectric polarization model. The proposed device is also validated using the SILVACO ATLAS device simulator, which yields a good agreement with the model, establishing its reliability and acceptability. The device achieves a steeper subthreshold of 31.3 mV/decade, an improved ON current∼5.9 x 10−4A/μmand enhanced transconductance∼0.105 ms as well as a very low energy delay product (EDP)∼4.07 x 10−3Js with hysteresis free operation at a low supply voltage∼0.5 V in a 40 nm technology node, making it desirable for ultra-low power analog and logic applications.

High‐speed, two‐stage operational transconductance amplifier without Miller capacitor, suitable for large capacitive load

AbstractA two‐stage Class A‐AB operational transconductance amplifier with low power consumption, high slew rate, and high bandwidth is introduced for handling large capacitive loads. Unlike the conventional two‐stage operational transconductance amplifiers that use a Miller capacitor, compensation is provided by the load capacitor (CL) at the output node. The proposed two‐stage amplifier maintains a 45° phase margin (PM) over any load capacitance. This is achieved through a MOSFET‐based RC network at the output node. Dual nMOS/pMOS differential stages drive output directly, improving both SR+ and SR−. Post‐layout simulation results with a capacitive load of 100 pF (CL) demonstrate that the proposed operational transconductance amplifier has a DC gain of 60.1 dB, an excellent average slew rate of 20.3 V/µs, a gain‐bandwidth product of 10.6 MHz, an average 1% settling time of 122.2 ns and a PM of 76.6°, while consuming only 103.5 µW. Reducing the CL to 10 pF reduces the PM to 47.6°, while increasing the gain‐bandwidth and average slew rate to 82.9 MHz and 142.6 V/µs respectively.

A three-stage single-miller CMOS OTA with no lower load capacitor limit

This work proposes a Single Miller Capacitor (SMC) compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors with a zero minimum load capacitor. The proposed three-stage OTA does not require a minimum load capacitor for OTA to be stable. The proposed work uses two different feed-forward transconductors to enhance the small-signal and large-signal performances of the OTA. This OTA achieves more than 70° phase margin and more than 10dB gain margin with a load capacitor range of 0 to 500pF and consumes less quiescent current. The proposed OTA uses a smaller SMC of 2pF to drive a wide range of load capacitors. Furthermore, it saves the active area of the chip. The proposed OTA is simulated in a cadence virtuoso tool using UMC 90nm CMOS technology with BSIM4 MOSFETs.

Dynamic switching operation of diamond MOSFETs with NO2 p-type doping and Al2O3 gate insulation and passivation

Diamond metal–oxide–semiconductor field-effect transistor (MOSFET) exhibited durable and stable dynamic switching characteristics at an unprecedentedly high voltage of −105 V. Switching turn-on and turn-off times were measured to be 7.64 and 4.93 ns, respectively, with a corresponding total switching loss of 20.03 pJ for a load resistance of 50 Ω. No Miller effect was observed due to the low Miller capacitance of 11 pF/mm. This study suggests the potentiality of diamond MOSFETs in prospective high-voltage, high-speed applications.

A two‐step sizing method for multistage Op Amps based on behavioral initial sizing followed by Spice‐in‐the‐loop refining

AbstractAnalog integrated circuit sizing is a laborious process that requires many times of iteration with Spice simulations. Even by applying the method, it still requires iterations and test assignment of device values (and biasings) in each iteration until reaching a satisfactory sizing result. When facing a design of multiple‐stage circuits (such as multiple‐stage operational amplifier [Op Amp]), sizing becomes more challenging due to the requirement on pole‐zero placement in order to achieve a better high‐frequency performance. Simulation‐in‐the‐loop method has been the dominating means taken by a great many of existing circuit sizer, but they suffer from intolerable runtime while lacking the possibility of offering insight or design knowledge acquisition. On the other hand, behavioral‐level synthesis methods, although intuitive and fast, suffer from accuracy loss due to the adoption of simplified device models and significantly condensed design equations. However, a proper combination of these two types of methods could lead to a lucrative research territory, yet it demands a methodological development for efficient deployment in practice, namely, implementation easy, less runtime, and guaranteed sizing quality. In this paper, we propose a two‐step method that takes the advantage of behavioral synthesis (in the first step) that is capable of fast and broader coverage of design space then makes correction (in the second step) on sizing refining by Spice simulation. Due to the profiling knowledge acquired on the design space in the first step, it can avoid blindness of the optimization landscape that is faced by many simulation‐centric methods which could easily get trapped in local optima. Conducted experiments over eight three‐stage Op Amps with different compensation configurations, including nested Miller capacitor (NMC), NMC with feedforward path (NMCF), NMC with feedforward path and nulling resistor (NMCFNR), NMC with nulling resistor (NMCNR), double pole‐zero cancellation (DPZC), transconductance with capacitances feedback compensation (TCFC), impedance adapting compensation (IAC), active feedback frequency compensation (AFFC), have validated that the proposed method can successfully generate qualified sizing results, offering an opportunity to compare fairly what merit a specific compensation strategy could possibly have.

A Wideband Hybrid Envelope Tracking Supply Modulator with Slew-Rate-Enhanced Linear Amplifier

A wideband hybrid envelope tracking supply modulator (HETSM) with a slew-rate-enhanced linear amplifier (LA) is described in this work. The proposed slew-rate enhancement (SRE) structure introduces a parallel auxiliary current path directly to the gate of the class-AB output stage, significantly accelerating the charging and discharging processes of the Miller capacitor without modifying the operating point of the remaining LA. The current delivered via this supplementary path shows a rapid increase, with changes in input voltage, culminating in diminished quiescent current levels. The supply modulator is fabricated in a 180 nm CMOS process. The measurement results show that HETSM is able to track a 100 MHz, 16QAM signal accurately, achieving the maximum efficiency of 87.4% at a 5.12 W output power, with a load that consists of a 5 Ω resistor and a paralleled 100 pF capacitor. The proposed LA realizes a slew rate of −1857/+1239 V/μs and a bandwidth of 226.6 MHz under a 24 mA quiescent current.

The collector current model of the IGBT based on the gate charge

In this study, a dynamic and static collector current (IC) model of the IGBT based on the gate charge is proposed. The gate charge could be easily obtained by measuring the voltage across the gate mirror circuit capacitance, and the transconductance obtained from the IC–VGE curve is mainly used. This model does not need the device structure parameters such as doping concentration, length, and thickness, thus is low cost and highly convenient. First, the gate charge is derived by integrating the currents of the variable capacitors CGE and CGC during the turn-on and turn-off transients, and an analytical relationship between the dynamic IC and QG is researched. Second, a static collector current IC is established, and the gate charge is obtained through current integration during the period of the Miller capacitance plateau. The influence of the temperature on the static transconductance is studied, and the accuracy of the static current model is improved. Finally, the performance of the model is optimized with various voltages, temperatures, and currents. The experimental results reveal that the proposed model achieves a collector current error of less than 5.6 % under various operating conditions, which verifies the accuracy of the proposed model.

Miller capacitance reduction in negative capacitance TFETs

ABSTRACT A dielectric stacked hetero-gate topology is proposed to reduce the Miller capacitance in a negative capacitance double gate TFET. An analytical charge-based model is introduced for the analysis of the terminal capacitance behaviour of the device. Charge and capacitance models are developed using the surface potential modelling approach by solving the Poisson Equation. The proposed closed-form charge model is SPICE-compatible and can be used for circuit simulations. The model accuracy is validated by combining one-dimensional Landau–Khalatnikov equation with the two-dimensional simulations of the double gate stacked-hetero-gate tunnel field effect transistor. The model shows excellent agreement with device simulations. The proposed topology exhibits Miller capacitance reduction of 30% which results in the gain band width product improvement of 43% more than the stacked homo-gate counterpart.

Insights into dynamic switching behavior and electric field distribution of depletion-mode GaN HEMT with bonding pad over active layout

Bonding pad over active (BPOA) layout, which stacks traditional horizontal structure pad electrodes vertically above the active area, is an area-effective device architecture and packaging-enabled solution for GaN-based high electron mobility transistors (HEMTs). In this work, the dynamic switching and electric field distribution of such layout, as well as associated capacitance–voltage and trapping characteristics, are comprehensively studied on D-mode GaN-on-sapphire HEMT by performing numerical simulations. In terms of different pad electrodes covering the active area, BPOA is composed of various structures such as gate-related and drain-related BPOAs (i.e. G-BPOA and D-BPOA), among which G-BPOA exhibits inferior switching characteristics due to the additional introduction of Miller capacitance that prolongs the device switching, while breakdown voltage of D-BPOA is 400–900 V lower than other BPOA counterparts due to the interplay between D-BPOA and the drain electrode. Furthermore, the effects of trap capture cross section and trap density on switching characteristics are evaluated. These results highlight the differences in electrical characteristics of various structures within the BPOA layout, and provide valuable insights into BPOA device design and performance improvement.

Novel majority carrier accumulation insulated gate bipolar transistor with Schottky junction

Insulated gate bipolar transistor (IGBT) is the core of modern power semiconductor device, and has been widely used due to its excellent electrical characteristics. A novel majority carrier accumulation mode IGBT with Schottky junction contact gate semiconductor layer (AC-SCG IGBT) is proposed and investigated by TCAD simulation in this article. When the AC-SCG IGBT is in the on-state, a forward bias is applied to the gate. Due to the very low forward voltage drop (<i>V</i><sub>F</sub>) of the Schottky barrier diode, the potential of the gate semiconductor layer is almost equal to the gate potential, which can accumulate a large number of majority carrier electrons in the drift region. In addition to the electrons existing, these accumulated electrons increase the conductivity of the drift region, thus significantly reducing <i>V</i><sub>F</sub>. Therefore, the doping concentration of the drift region is not limited by <i>V</i><sub>F</sub>. The lightly doped drift region can make AC-SCG IGBT have a higher breakdown voltage (BV). Moreover, it also reduces the barrier capacitance in the turn-off process, thus the overall Miller capacitance is small, which can quickly turn off and reduce the turn-off time (<i>T</i><sub>off</sub>) and turn-off loss (<i>E</i><sub>off</sub>). The simulation results indicate that at the BV of 600 V, the <i>V</i><sub>F</sub> of 0.84 V for the proposed AC-SCG IGBT is reduced by 46.2% compared with that for the conventional IGBT (<i>V</i><sub>F</sub> of 1.56 V). The <i>E</i><sub>off</sub> of the AC-SCG IGBT (0.77 mJ/cm<sup>2</sup>) is reduced by 52.5% compared with that for the conventional IGBT (1.62 mJ/cm<sup>2</sup>), and the <i>T</i><sub>off</sub> (155.8–222.7 ns) is reduced by 30%. The contradiction between <i>V</i><sub>F</sub> and <i>E</i><sub>off</sub> is eliminated. In addition, the proposed AC-SCG IGBT has a better anti-latch-up capability and is coupled with its higher BV, so it has a larger forward biased safe operating area (FBSOA). The proposed novel structure meets the development requirements for future IGBT device performance, and has great significance for guiding the development of the power semiconductor device field.

Recycling folded cascode two-stage CMOS amplifier

In this work, we propose a highly efficient two-stage CMOS amplifier that is based on an improved recycling folded cascode design. The circuit was simulated using TSMC 0.18 μm and HSPICE circuit simulator at a voltage of 1.8 V. The first stage of the circuit utilizes a supper recycling folded cascode design, while the second stage employs a simple cascode amplifier. Additionally, we have utilized a small 1 pF Miller capacitor to stabilize the amplifier response. Based on simulation results, the proposed amplifier demonstrates a DC gain of 110 dB, GBW of 15 MHz, and power consumption of 359 μW. Finally, we conducted Monte Carlo simulations to verify the robustness of the proposed circuit against the process, temperature, supply voltage, and device dimension mismatch variations.

Two-port feedback analysis on Miller-compensated amplifiers

In this paper, various Miller-compensated amplifiers are analyzed by using the two-port feedback analysis together with the root-locus diagram. The proposed analysis solves problems of Miller theorem/approximation that fail to predict a pole-splitting and that require an impractical assumption that an initial lower frequency pole before connecting a Miller capacitor in a two-stage amplifier should be associated with the input of the amplifier. Since the proposed analysis sheds light on how the closed-loop poles originate from the open-loop poles in the s-plane, it allows the association of the closed-loop poles with the circuit components and thus provides a design insight for frequency compensation. The circuits analyzed are two-stage Miller-compensated amplifiers with and without a current buffer and a three-stage nested Miller-compensated amplifier.

Four stage CMOS operational amplifier, frequency compensated via active miller network

AbstractA four‐stage CMOS operational amplifier is proposed in this work. The designed amplifier is frequency compensated via two differential blocks and two Miller capacitors. Unlike well‐known frequency compensation methods, the proposed compensation leaves the output node while exploiting extremely smaller capacitors compared to conventional approaches. The presented approach is modeled symbolically and realized at the circuit level via the Hspice circuit simulator and 0.18 μm CMOS technology. Good agreements between two separate simulation paths verify the validity and accuracy of the proposed approach. Ample simulation results are reported to investigate the proposed amplifier regarding parameter mismatches. According to the simulation results, the proposed four‐stage amplifier is an excellent candidate to be used in larger systems such as data converters, modulators, and sensors while it shows more than 169 dB as DC‐gain, 10 MHz as unity gain frequency with power consumption less than 500 μW.

Gate Driver Design in 180 nm SOI CMOS Process for Heterogeneous Integration Inside SiC Power Module

This paper presents the design and test results of a non-isolated single-channel gate driver for heterogeneous integration inside a SiC power module. The driver is designed on a 180 nm silicon-on-insulator (SOI) CMOS process that can safely operate up to 175 degrees C, most likely even beyond this figure, to survive at the expected junction temperature. The gate driver consists of four pull–up (PMOS) slices and four pull-down (NMOS) slices placed in parallel as the current sourcing and sinking components. Each slice can be activated individually through a controller block, making the gate driver’s drive strength variable. To mitigate the parasitic turn-on effect due to the Miller capacitor, an active Miller clamping circuit is integrated with the driver without overly compromising the device’s switching performance. Under-voltage lockout (UVLO) is another key feature of this driver that ensures the system is protected against bias supply failure. A desaturation detection scheme is also integrated with the gate driver as a system protection feature to detect excessive current flowing through the power devices. The gate driver die area is approximately 5.4 mm x 3.3 mm with a pad area of 100 μm x 100 μm suitable for wire bonding inside the module.

Circuit design of a three-stage CMOS amplifier by circuit theory and analysis miller compensation network

This paper establishes a single Miller capacitor-based frequency compensation network for a three-stage amplifier. Nodal equations are solved symbolically and a linear transfer function is obtained. Poles and zeros formulations are extracted while circuit-level implementation is suggested and simulated using 0.18 μm CMOS technology. The compensation network shares the Miller capacitor at two negative loops simultaneously leading to improving frequency response. According to the simulation results, theoretical linear calculations are in acceptable agreement. The proposed amplifier shows 115 dB, 151 MHz, and 55 as DC gain, GBW, and PM respectively while consuming 320 μW as power dissipation.

DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs

In this paper, electrical characteristics of a complementary tunneling field effect transistor (CTFET) is studied computationally for the first time. The design of CTFET is carried with 3D vertically stacked channels (multiple) of n-TFET on top of the p-TFET with gate-all-around (GAA) nanosheet SiGe options. The CTFET technology (using CFETs) is examined for emerging technology nodes as a potential alternative to conventional TFETs. Here, the device level design of CTFET is strictly monitored with DC characteristic behavior under the influence of process variability conditions (traps and temperature). The performance analysis is extended to analyze the scalability of CTFET under critical dimensions (n- to p-TFET separation, nanosheet pitch, and so on), and find that it is highly scalable. The circuit analysis of CTFET-inverter show high-noise margin (NM) and voltage gains compared to the conventional strained-Si GAA-TFETs at the supply range (V D D) from 0.7 ≥ V D D ≥ 0.2 V. In addition, the CTFET-inverter circuit performance is analyzed with miller capacitance, power delay product, and intrinsic delay, respectively. Improved circuit performance, followed by 12.5% and 21.5% improvements in low and high NMs (NML and NMH) are seen in CTFETs compared to conventional TFETs.

Operational Transconductance Amplifier Designed with Experimental Omega-Gate Nanowire SOI MOSFETs

The nanowire omega-gate technology is one of the possible technologies to replace the FinFET one in the semiconductor chip market. The omega-gate nanowire SOI MOSFET is considered a triple plus gate device, near the gate-all-around performance (figure 1) [1]. Due to the omega gate structure this device presents a better gate to channel electrostatic coupling than the FinFET devices, resulting in a greater immunity to short channel effects [1,2].The Operational Transconductance Amplifier (OTA) is a frequently used analog block in the integrated circuits. The studied OTA consists in a two-stage amplifier, where the first stage is a differential amplifier with active load and the second one is a common source amplifier, as can be seen in figure 2. This analog block is biased through the current source and the bias current is mirrored for each stage. In addition, negative feedback is used between the first and second stages with a compensation capacitor (miller capacitor) in order to stabilize the amplifier response.In this work, an OTA circuit is designed with SOI omega-gate nanowire experimental transistors. In order to find the best device to be used in the project, some measurements were carried out of several nanowire devices with different channel lengths (ranging from 20 nm to 200 nm). The schematic structure of the measured devices is presented in figure 3 [2]. Basic device parameters such as: transconductance (gm), output conductance (gd), Early voltage (VEA), threshold voltage (VT), transistor efficiency (gm/ID) and subthreshold slope (SS) were analyzed.The model of the experimental omega-gate transistors was performed using the Look Up Table (LUT) method. The capacitance measurements of the nanowire transistor were also considered, to simulate the frequency responses more faithfully. The simulator used to design the OTA circuit was Cadence using the Verilog-A language. It was obtained the main figure of merit of this block like voltage gain (Av), gain-bandwidth product (GBW), phase margin and power.A transistor efficiency (gm/ID) near 8 V-1 was chosen in order to compare the performance of OTA designed with omega-gate nanowire devices (NW-OTA) of this work with anothers OTAs designed with triple gate FinFETs (FinFET-OTA) and with nanosheets (NS-OTA) from the literature (Table 1) [3,4].Table 1 shows that the phase margin is close to 60o in all cases, ensuring the stability of the circuit. The NW-OTA presents higher voltage gain compared to FinFET-OTA due to the better gate to channel coupling. The NS-OTA presents the highest voltage gain of all cases, but it is the more expensive technology [4]. When GBW is analyzed for all 3 designs, the NW-OTA shows better results than the NS-OTA, using the same load capacitance of 200fF, thanks to the lower miller capacitance (Cc) required to keep the frequency behavior. The FinFET-OTA shows the best result in relation to GBW, but the FinFET-OTA project doesn’t consider a load capacitance, making the comparison unfair [3].Figure 4 shows the gain and phase of the OTA using a SOI omega-gate nanowire transistors.In summary, the OTA designed with SOI omega-gate nanowire technology presents a better performance than FinFET one, can be implemented in a smaller area on the chip (smaller Cc capacitor and smaller number of fins in parallel) and it is a cheaper option compared to nanosheet one. Figure 1

A Low-Power Capacitorless LDO Regulator with Transient Enhancement Structure

In this paper, a portable low-power low dropout regulator (LDO) with no output capacitance has been designed in 0.18-[Formula: see text]m CMOS technology. In this paper, a PMOS power transistor is used and combined with an overshoot and undershoot suppression circuit to improve the transient response of the circuit. A modified Class-AB operational transconductance amplifier (OTA) is used to reduce power consumption and act as an error amplifier to eliminate low frequency poles. At the same time, a super source follower and a Miller capacitor are used for frequency compensation of the system. Finally, the system can provide a stable voltage for a load step from 0.2 to 25[Formula: see text]mA in 500[Formula: see text]ns edge-time for 140[Formula: see text]pF-load capacitance. The test results show that the circuit achieves a good voltage regulation rate and high transient response.

A 2.4 GHz low-power and compact 3-bit active phase shifter utilizing miller capacitance

A low-power and compact 3-bit active phase shifter is designed and implemented in a 22 nm FDSOI CMOS process. A modified inverter-based topology, which takes advantage of miller capacitance, is used to create a compact and low-power solution, resulting in ∼10× and ∼90× reduction in the power and chip area, respectively, for a given phase shift, compared to the standard inverter-based topology. At the same time, the proposed phase shifter exhibits less sensitivity to device mismatch. The proposed design measures ∼0.004 mm2, consumes 1.8 mW, and delivers up to 65°of phase shift with RMS phase and amplitude error of 3.85°and ±0.34 dB, respectively. The measured die-to-die variation is also confined to ±6.2°, which is <10% of the full range.