Microprocessor Chip Research Articles

Large-scale photonic network with squeezed vacuum states for molecular vibronic spectroscopy

Although molecular vibronic spectra generation is pivotal for chemical analysis, tackling such exponentially complex tasks on classical computers remains inefficient. Quantum simulation, though theoretically promising, faces technological challenges in experimentally extracting vibronic spectra for molecules with multiple modes. Here, we propose a nontrivial algorithm to generate the vibronic spectra using states with zero displacements (squeezed vacuum states) coupled to a linear optical network, offering ease of experimental implementation. We also fabricate an integrated quantum photonic microprocessor chip as a versatile simulation platform containing 16 modes of single-mode squeezed vacuum states and a fully programmable interferometer network. Molecular vibronic spectra of formic acid and thymine under the Condon approximation are simulated using the quantum microprocessor chip with high reconstructed fidelity ( > 92%). Furthermore, vibronic spectra of naphthalene, phenanthrene, and benzene under the non-Condon approximation are also experimentally simulated. Such demonstrations could pave the way for solving complicated quantum chemistry problems involving vibronic spectra and computational tasks beyond the reach of classical computers.

A comparative study of security features of national identity cards in five countries: India, Brazil, South Africa, Malaysia, and the Philippines = Badania porównawcze zabezpieczeń w dokumentach osobistych używanych w pięciu krajach: Indiach, Brazylii, Południowej Afryce, Malezji i Filipinach

This article discusses the security features of national identity cards of different countries in order to compare and help understand the application and uniqueness of these features. national identity cards are security documents provided with embedded security features to prevent their counterfeiting and misuse. These features include holograms, microprinting, anti-photocopying properties, QR codes, and ghost images. A security document is a medium necessary to prove a person’s identity as an unique individual in the civil and legal sense. This article analyzes a comparative study of national identity cards used in five countries: India, Brazil, South Africa, Malaysia, and the Philippines. The study was based on a collective set of 22 security features, such as ghost images, QR codes, tactile engravings, microprocessor chips, guilloches, holograms, and anti-photocopying features. The results showed that the lowest number of security features appears in the Brazilian identity card (8), followed in increasing order by India (10), Malaysia (12), the Philippines (12), and South Africa (14). Moreover, the article discusses the prevalence of security features, along with the need for and the methods to implement their improvement. The study aims to identify a security feature or a combination of features that would make the security document in question safer. This could assist countries around the world in curbing the prevalence of fraud and identity theft by improving and strengthening their identification systems.

Numerical Investigation of Heat Transfer and Development in Spherical Condensation Droplets.

This study establishes thermodynamic assumptions regarding the growth of condensation droplets and a mathematical formulation of droplet energy functionals. A model of the gas-liquid interface condensation rate based on kinetic theory is derived to clarify the relationship between condensation conditions and intermediate variables. The energy functional of a droplet, derived using the principle of least action, partially elucidates the inherent self-organizing growth laws of condensed droplets, enabling predictive modeling of the droplet's growth. Considering the effects of the condensation environment and droplet heat transfer mechanisms on droplet growth dynamics, we divide the process into three distinct stages, marked by critical thresholds of 105 nm3 and 1010 nm3. Our model effectively explains why the observed contact angle fails to reach the expected Wenzel contact angle. This research presents a detailed analysis of the factors affecting surface condensation and heat transfer. The predictions of our model have an error rate of less than 3% error compared to baseline experiments. Consequently, these insights can significantly contribute to and improve the design of condensation heat transfer surfaces for the phase-change heat sinks in microprocessor chips.

Design and demonstration of an ultra-thin planar microscale capillary pumped loop for electronics thermal management

With new requirements for enhanced thermal management, the minimum size of modern compact electronic devices and the maximum allowable processing speeds of the underlying microprocessor chips have become fundamentally limited by Joule heating. Miniaturizing a conventional loop heat pipe (LHP) or capillary pumped loop (CPL) to enable an ultra-thin high-heat-flux thermal transport system can lead to a paradigm shift in electronics thermal management. However, the complex thermodynamics of a CPL flow loop and the altered behavior of surface tension forces and thermal transport effects at small length scales pose several challenges to the actual implementation of a planar microscale CPL. Here we report on the design aspects of a micro-CPL device fabricated on a 500μm-thick silicon wafer, and experimentally examine the process of evaporation and two-phase flow in the device. An optical study of liquid evaporation in two distinct planar evaporator topologies during device startup reveals the critical roles played by enhanced surface tension forces and increased parasitic heat flows. Critical microfluidic device design aspects that can ensure the successful startup and operation of these ultra-thin thermal management devices are thereby revealed. Device evaporation experiments reveal successful device startup under evaporative heat fluxes of 10–20 W/cm2.

Optimization of the Thermally Conductive Low-k Polymer Dielectrics Based on Multisource Free-Volume Effects.

Polymers/polymer matrix composites possessing low dielectric constants (low-k polymer dielectrics) contribute to the advance of electronics, for instance, microprocessor chips, mobile phone antennas, and data communication terminals. However, the intrinsic long-chain structural characteristic results in poor thermal conductivities, which draw heat accumulation and undermine the outstanding low-k performance of polymers. Herein, multisource free-volume effects that combine two novel kinds of extra free volume with the known in-cage free volume of polyhedral oligomeric silsesquioxanes (POSSs) are discussed to reduce the capacity for dielectric constant reduction. The multisource free-volume effects of POSSs are associated with the thermal conductive network formed by the hexagonal boron nitride (BN) in the polymer matrix. The results show a decent balance between low-k performance (dielectric constant is 2.08 at 1 MHz and 1.98 at 10 GHz) and thermal conductivity (0.555 W m-1 K-1, 4.91 times the matrix). The results provide a new idea to maximize the free-volume effects of POSSs to optimize dielectric properties together with other desired performances for the dielectrics.

Crossing Number of Infinite Family of Extension Kochol's Periodic Graphs

At this time, technology is developing very quickly and is increasingly sophisticated. This technological development is certainly closely related to the development of computer technology. A computer is able to control a series of electronic devices using an IC chip that can be filled with programs and logic called microprocessor technology. A microprocessor is a digital component of the VLSI (Very Large Scale Integration) type with very high circuit complexity that is capable of carrying out the functions of a CPU (Central Processing Unit). Among many applications, the problem of crossing number very interesting and important because of its application in the optimization of chip are required in a circuit layout of VLSI. Crossing number used to obtain the lower bound on the amount of chip area of VLSI devices like microprocessor and memory chips additionally, crossings in the circuit layout could cause short circuit and therefore worth minimized independent of the chip area consideration. Some graph can be seen as built by small pieces. A principal tool used in construction of crossing-critical graphs are tiles. In the tile concept, tiles can be arranged by gluing one tile to another in a linear or circular fashion. The series of tiles with circular fashion form an infinite graph family. In this way, the intersection number of this family of graphs can be determined. In this research, has been formed an infinite family graphs The graph formed by gluing together many copies of the tile in circular fashion, where the tile consists of identical tile sections. The results obtained show that the graph has 3-crossing-critical of a graph.

Design and Simulation of a System-in-Package Chip for Combined Navigation.

This paper proposes a system-in-package combination navigation chip. We used wire bonding, chip stacking, surface mount, and other processes to integrate satellite navigation chips, inertial navigation chips, microprocessor chips, and separation devices. Finally, we realized the hardware requirements for combined navigation in a 20 mm × 20 mm chip. Further, we performed a multi-physics simulation analysis of the package design. For antenna signals, the insertion loss was greater than -1 dB@1 GHz and the return loss was less than -10 dB@1 GHz. The amplitude of these noises of the signal between the MCU and the IMU was approximately 20%, and the maximum value of the coupling coefficient between signal lines on the top surface was 13.4174%. The ninth mode of the power plane yielded a maximum voltage of 55 mV, and all power delivery networks had a DC voltage drop of less than 2%. The highest temperature in the microsystem was approximately 42 °C. These results show that our design performed well in terms of signal, power, and thermal performance.

Low Power Adders for Efficient Image Processing Applications

In the world of digitalization, low-power circuits are necessary for building fast operating processors. Additionally, low-power circuits consume less energy and the lifetime of the electronic devices can extended to the maximum. Adders are significantly used in digital image processing techniques and for many Very Large-Scale Integration (VLSI) applications. Due to this, demand for creating efficient adders has become high in recent years. Using approximate adders is much more convenient than exact adders and the results of approximation adders are better than exact adders. Approximation adders can be executed for many signal-processing applications and are mainly considered for image-processing applications. SESA and SEDA are very good in providing efficiently lower energy when compared to other mirror adder circuits and are cost-efficient. Improvements and further extensions of the proposed model can easily make for building efficient microprocessor chips and these adders are used in next-generation electronic devices.

Multiscale modeling of lubrication flows under rarefied gas conditions

We present a multiscale method for simulating non-equilibrium lubrication flows. The effect of low pressure or tiny lubricating geometries that gives rise to rarefied gas effects means that standard Navier–Stokes solutions are invalid, while the large lateral size of the systems that need to be investigated is computationally prohibitive for Boltzmann solutions, such as the direct simulation Monte Carlo method (DSMC). The multiscale method we propose is applicable to time-varying, low-speed, rarefied gas flows in quasi-3D geometries that are now becoming important in various applications, such as next-generation microprocessor chip manufacturing, aerospace, sealing technologies and MEMS devices. Our multiscale simulation method provides accurate solutions, with errors of less than 1% compared to the DSMC benchmark results when all modeling conditions are met. It also shows computational gains over DSMC that increase when the lateral size of the systems increases, reaching 2–3 orders of magnitude even for relatively small systems, making it an effective tool for simulation-based design.

Study of forced convection turbulent flow over a heated microprocessor chip

Study of forced convection turbulent flow over a heated microprocessor chip

Interview With Prof. Sung-Mo (Steve) Kang

Nicola Nicolici: Good afternoon. Let me welcome Prof. Kang from the University of California at Santa Cruz (UC Santa Cruz). Prof. Kang is an electrical engineer, scientist, professor, author, inventor, and entrepreneur. Currently, he is a distinguished professor emeritus at UC Santa Cruz. He has contributed extensively to the fields of computer-aided design for electronic circuits and systems. He holds 15 U.S. patents, has published over 500 articles, and has won numerous awards for his achievements. He has led the development of the world’s first 32-bit microprocessor chip, Bellmac-32, as a technical supervisor at ATT Bell Labs, Murray Hill, NJ, USA, and has designed satellite-based private communication networks as a member of technical staff.

Silicone-Based Thermally Conductive Gel Fabrication via Hybridization of Low-Melting-Point Alloy-Hexagonal Boron Nitride-Graphene Oxide.

Thermal contact resistance between the microprocessor chip and the heat sink has long been a focus of thermal management research in electronics. Thermally conductive gel, as a thermal interface material for efficient heat transfer between high-power components and heat sinks, can effectively reduce heat accumulation in electronic components. To reduce the interface thermal resistance of thermally conductive gel, hexagonal boron nitride and graphene oxide were hybridized with a low-melting-point alloy in the presence of a surface modifier, humic acid, to obtain a hybrid filler. The results showed that at the nanoscale, the low-melting-point alloy was homogeneously composited and encapsulated in hexagonal boron nitride and graphene oxide, which reduced its melting range. When the temperature reached the melting point of the low-melting-point alloy, the hybrid powder exhibited surface wettability. The thermal conductivity of the thermally conductive gel prepared with the hybrid filler increased to 2.18 W/(m·K), while the corresponding thermal contact resistance could be as low as 0.024 °C/W. Furthermore, the thermal interface material maintained its excellent electric insulation performance, which is necessary for electronic device applications.

Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability

The IBM Z computing platform is optimized for processing vast amounts of data and transactions with low latency in a highly virtualized and secured environment with sustained processor utilization of over 90%. The platform and its microprocessor chip are designed to deliver consistent system performance, throughput, and response times under all conditions. The innovative cache architecture of the IBM Telum Processor provides low latency, large capacity, and reliable L2 caches. Based on a novel horizontal cache persistence algorithm, these L2 caches also serves as system wide L3 and L4 caches delivering optimal enterprise application performance. When built into an IBM z16 system, these architectural features deliver 11% per-core performance improvement over the prior z15 hardware, running real-world enterprise applications.

Formation of a management strategy for innovation and investment activities of an enterprise

The influence of single failures on the operation of digital devices is considered. Single events and their classification are considered. A generalized function for ensuring fault tolerance in the design of integrated circuits is introduced. The implementation of these methods is shown on the example of a microprocessor chip.

Design of Power and Area Efficient Carry Skip Adder and FIR filter Implementation

Adders are used in processing units such as Arithmetic and Logic Units (ALUs) as an essential building block, and in many blocks of microprocessor chips critical path, adders occupy an important place. Hence reducing power, area and increasing the speed of adders are significantly important. This paper proposes a modified structure of Carry Skip Adder (CSKA) with a reduction in consumption of power and area without affecting the speed when compared with the conventional adder structures. In order to get better effectiveness of the modified CSKA by including concatenation, incrementation schemes, and variable latency for the proposed hybrid structure, which reduces the power utilized without affecting the operating speed of the adder. The modified structure in CSKA helps in improving the slack time, which further reduces the voltage with the parallel structure. Experimental results show that the 32-bit implementation of the proposed adder has a significant power reduction of 42% and 38.3%, area reduction of 27%, and 18.3% with respect to Conventional CSKA and CI CSKA adder with a little over ahead in delay. The proposed adder is used to implement a 5-tap FIR filter which shows a significant reduction in power consumption and area.

Mental health education information analysis system for pre-school students

The traditional information analysis system has low accuracy and effect on the information analysis of preschool children's mental health education. Therefore, an information analysis system of preschool students' mental health education based on big data is proposed. In the hardware part, CISC microprocessor and MCS-51 single chip microcomputer are designed. The software part establishes the functional module of the system, designs a database based on big data, and analyzes the mental health education information of preschool children. The performance test results show that the accuracy of the information analysis index of the design system is high, and the information analysis effect of preschool children's mental health education is good, which is very worthy of popularization.

High-Resolution Imaging of Human Cancer Proteins Using Microprocessor Materials.

Mutations in tumor suppressor genes, such as Tumor Protein 53 (TP53), are heavily implicated in aggressive cancers giving rise to gain- and loss-of-function phenotypes. While individual domains of the p53 protein have been studied extensively, structural information for full-length p53 remains incomplete. Functionalized microprocessor chips (microchips) with properties amenable to electron microscopy permitted us to visualize complete p53 assemblies for the first time. The new structures revealed p53 in an inactive dimeric state independent of DNA binding. Residues located at the protein-protein interface corresponded with modification sites in cancer-related hot spots. Changes in these regions may amplify the toxic effects of clinical mutations. Taken together, these results contribute advances in technology and imaging approaches to decode native protein models in different states of activation.

Bluetooth Based Agrobot Used to Spray the Pesticides

Abstract: The agricultural robot, or Agrobot, that was created here is meant to spray pesticides on the crops. The purpose of a Bluetooth device is to enable mobile phone remote control of a robot. Because it is dangerous for people to be close to the sprayer when deadly chemicals are being sprayed over agricultural fields, this remote-operated sprayer was created so that it can be used from a safelocation. For wireless communication across short distances, there is a protocol called Bluetooth. A cell phone can be used to control agricultural equipment including machines for spreading urea, sowing seeds, and pulling weeds with the use of a Bluetooth device connectedto an embedded system. This straightforward technique is made to spray liquid pesticides in this regard. As a machine control unit that receives command signals from the mobile phone, the Bluetooth device interfaced with embedded systemis created. The moving mechanism is covered with this control circuit, its power supply, rechargeable batteries, and other devices, including DC motors. This mechanism can be controlled using a cell phone using an android application or an app placed on any smart phone. With the aid of this programme, users can wirelessly send commands through Bluetooth to the control system. The robot's movement can be controlled by a Bluetooth device connected to an 89C51 microprocessor chip. The mechanism is moved by two DC motors that are each individually controlled by an H Bridge IC.When necessary, liquid pesticide can be sprayed from the vehicle holding a small liquid tank over its chassis using a liquid pumping motor attached to the tanker's body. This pumping motor is likewise operated by the same cell phone.

46 An Engineers Perspective on Sensor Development and Future Applications in Livestock

Abstract Sensors are essential to collect a wide range of high-fidelity and reproducible data from livestock farms. On one hand, commercial cameras are capable of recording large videos for post-processing and analysis on edge computers. On the other hand, a variety of electronic sensors and microprocessor chips are commercially available to track the posture and movement of animals in livestock farms. There are inherent tradeoffs in developing and adopting the above sensors, including issues with handling the big data, effective noise filtering, computing at the edge, on-farm resiliency, power usage, and infrastructure costs. In this talk, we will discuss these tradeoffs while understanding the needs of different livestock farms in the context of our research in sensor technologies.

Atomistic simulation toward real-scale microprocessor circuits

A highly efficient and novel atomistic simulation framework is first established for the thermal and mechanical behaviors of a whole microprocessor chip or its constituent functional modules, important for the performance and reliability of high-end microprocessor circuits. The largest simulated module contains about 55.3 thousand nano-transistors with around 107 billion atoms. Traditionally, the macroscopic continuous methods are difficult to treat nanoscale factors such as doping, thin dielectric layer, surface and interface in the nano-transistor devices, while the microscopic quantum mechanics method can only calculate one or several nano-transistors. This proposed simulation method realizes the integrated treatment of the above nanoscale factors and complex gate layout by coupling multiple interatomic potential models for different materials and designing efficient parallel algorithms, and bridges the mesoscale simulation gap between the aforementioned macroscopic and microscopic methods. The development provides the first atomic-scale simulation framework for predicting and modulating the thermal behavior of a microprocessor circuit or its functional module, which paves an exciting way to the atomic-resolution design of novel high-performance microprocessor chips in the post-Moore era.