Microelectronic Assemblies Research Articles

Simplifying finite elements analysis of four-point bending tests for flip chip microcomponents

PurposeThe purpose of this study is to propose a simplifying approach for modelling a reliability test. Modelling the reliability tests of printed circuit board (PCB)/microelectronic component assemblies requires the adoption of several simplifying assumptions. This study introduces and validates simplified assumptions for modeling a four-point bend test on a PCB/wafer-level chip scale packaging assembly.Design/methodology/approachIn this study, simplifying assumptions were used. These involved substituting dynamic imposed displacement loading with an equivalent static loading, replacing the spherical shape of the interconnections with simplified shapes (cylindrical and cubic) and transitioning from a three-dimensional modelling approach to an equivalent two-dimensional model. The validity of these simplifications was confirmed through both quantitative and qualitative comparisons of the numerical results obtained. The maximum principal plastic strain in the solder balls and copper pads served as the criteria for comparison.FindingsThe simplified hypotheses were validated through quantitative and qualitative comparisons of the results from various models. Consequently, it was determined that the replacement of dynamic loading with equivalent static loading had no significant impact on the results. Similarly, substituting the spherical shape of interconnections with an equivalent shape and transitioning from a three-dimensional approach to a two-dimensional one did not substantially affect the precision of the obtained results.Originality/valueThis study serves as a valuable resource for researchers seeking to model accelerated reliability tests, particularly in the context of four-point bending tests. The results obtained in this study will assist other researchers in streamlining their numerical models, thereby reducing calculation costs through the utilization of the simplified hypotheses introduced and validated herein.

Eliminate Costly Component Out Of Pocket Defect Condition during Microelectronic Component Packaging/Shipping/Handling

High value devices used in microwave modules and other microelectronic assemblies have become increasingly thin and susceptible to “Component Out Of Pocket” (COOP) conditions that can occur during packaging, shipping, and customer handling. This defect condition is especially problematic for automated assembly which strives to be touch-free and efficient with orderly device presentation. COOP is a major contributor to “Cost Of Poor Quality” (COPQ) within the business. A funded study into COOP conditions was conducted and a dozen root causes were identified. It was discovered that traditional “waffle packs” have mechanical issues related to flatness tolerances with respect to the waffle tray and lid. The addition of a standard clip further contributes to the issue, both of which are key root causes of the costly “Component Out Of Pocket” (COOP) condition. A novel Lid-Clip System (LCS2) was engineered to compensate for those mechanical issues, bringing robust captivation and preservation of devices in waffle tray pockets. Static dissipative material for lid and clip was selected to provide unparalleled ESD Class 000 protection for high value devices with the lowest voltage susceptibility thresholds.

Investigation of stress relaxation in SAC305 with micro-Raman spectroscopy

In the paper, μ-Raman spectroscopy is applied as non-destructive test method to access the creep in chip interconnection materials. To develop the method, a silicon test chip is soldered onto a copper substrate using SAC305 and the strain of the silicon crystal in the top surface of the chip is measured time dependent after assembly by the Raman shift. The in-plane stress in silicon crystal decreased exponentially within several days after soldering. To access the strain in the solder material a finite element model was calibrated based on the experimental data applying the Anand creep model and fitting its parameter. The analysis reveals the applicability of μ-Raman measurement to assess creep within interconnect material in microelectronic assemblies.

Eliminate Costly Component Out Of Pocket Defect Condition during Microelectronic Component Packaging/Shipping/Handling

Abstract High value devices used in microwave modules and other microelectronic assemblies have become increasingly thin and susceptible to “Component Out Of Pocket” (COOP) conditions that can occur during packaging, shipping, and customer handling. This defect condition is especially problematic for automated assembly which strives to be touch-free and efficient with orderly device presentation. COOP is a major contributor to “Cost Of Poor Quality” (COPQ) within the business. A funded study into COOP conditions was conducted and a dozen root causes were identified. It was discovered that traditional “waffle packs” have mechanical issues related to flatness tolerances with respect to the waffle tray and lid. The addition of a standard clip further contributes to the issue, both of which are key root causes of the costly “Component Out Of Pocket” (COOP) condition. A novel Lid-Clip System (LCS2) was engineered to compensate for those mechanical issues, bringing robust captivation and preservation of devices in waffle tray pockets. Static dissipative material for lid and clip was selected to provide unparalleled ESD Class 000 protection for high value devices with the lowest voltage susceptibility thresholds.

Role of Nominal Stress State on Cyclic Fatigue Durability of SAC305 Grain-Scale Solder Joints

Abstract Solder joints in micro-electronic assemblies experience a multiaxial combination of extensional and shear loads due to combinations of thermal expansion mismatch and flexure of printed circuit assemblies during thermal cycling or during vibrational loading of constrained printed circuit assemblies. Although a significant amount of research has been conducted to study cyclic fatigue failures of solder joints under pure-shear loading, most of the current literature on cyclic tensile loading of solders is on long dog-boned monolithic solder coupons. Unfortunately, such specimens do not capture the critical interactions between key microscale morphological features (such as grain orientation, grain boundaries, intermetallic compounds, and substrates) that are believed to play important roles in the fatigue of functional solder joints under life-cycle loading. Therefore, this paper uses a combination of experiments and finite element analysis to investigate the differences in mechanisms of cyclic fatigue damage in Sn-3.0Ag-0.5Cu (SAC305) few-grained (oligocrystalline) microscale solder joints under shear, tensile and multiaxial loading modes at room temperature. Cyclic fatigue durability test results indicate that tensile loads are more detrimental compared to shear loads. Tensile versus shear loading modes are found to cause distinctly different combinations of interfacial damage versus internal damage in the bulk of the solder (transgranular and intergranular damage), which correlates with the differences observed in the resulting fatigue durability. The test results also confirm that the traditional approach of assuming a power-law dependence on equivalent deviatoric strain amplitude is inadequate for modeling cyclic fatigue durability of solder interconnects experiencing multiaxial loading. Instead, multiaxial fatigue damage results are seen to be affected not only by the cyclic equivalent strain amplitudes but also by the severity of the stress-triaxiality, as hypothesized in models such as Chaboche model.

Strength and Isothermal Fatigue Resistance of SnBi/SnAgCu Joints Reflowed at Low Temperatures

Abstract Soldered micro-electronics assemblies may have to survive a variety of mechanical loads in repeated drops, cyclic bending, or vibration. A very large body of work has addressed the isothermal fatigue performance of SnAgCu solder joints. This work offers a general assessment of the achievable performance of so-called hybrid solder joints formed by soldering with eutectic SnBi or SnBiAg to SnAgCu bumps on area array components. This allows for soldering at much lower temperatures than with SnAgCu alone, but the deformation and damage properties of the resulting structures depend strongly on details of the design and process. A peak reflow temperature of 175 °C was shown to be sufficient to ensure that the life of the joints remains limited by fatigue of the unmixed SnAgCu near the component. However, a higher effective stiffness of the mixed region near the substrate means that the life will be lower by 45%.

Effect of Elevated Temperatures on SAC305 Solder Alloy Thermal Interface Material in a Microelectronic Assembly

In microelectronics assemblies, Thermal Interface Materials (TIMs) are vital to the reliability of the devices in operation. Some electronic devices operate in elevated temperature environments such as military and industrial applications. Hence, the need to evaluate the reliability of such devices at elevated temperatures. Tin-Silver-Copper lead-free solder TIMs have been used during the assembly process of some electronic devices operating under harsh temperature environments. In this study, the reliability of SAC305 lead-free solder TIM was considered at elevated temperatures ranging from 100 oC to 200 oC at 25 oC interval, and aged for about an hour. ANSYS finite element analysis software was employed for the design and evaluation of SAC305 lead-free solder model. The findings of the investigation demonstrated that the higher the harsh temperature environment, the lower the reliability of the SAC305 solder TIM. In addition, the highest fatigue life (36735 or 4.2 years) was recorded at 100 oC, while 200 oC recorded the lowest fatigue life (1014 or 0.12 years). The fatigue life is an indication of the lifespan of the TIM when in operation. This research will be beneficial to engineers assembling microelectronic products. Keywords— elevated temperature; fatigue life; microelectronics; reliability; SAC305 solder

Low-Temperature Processing of Electronic Materials Using Uniform Microwave Fields

This article presents the recent literature on the unique and surprising capability of microwave energy to effect chemical reactions at lower temperatures. These lower processing temperatures provide improved thermomechanical properties of organic and inorganic material combinations used in microelectronic assemblies. Variable-frequency microwave (VFM) technology eliminates arcing and produces the large and highly uniform fields necessary for use in high-volume manufacturing. Wafer coatings of polyimide thermoplastics can be fully polymerized 100-200°C lower with VFM than with thermal ovens, which lowers stress and warpage. VFM curing of thermoset adhesives for underfill, bonding, and package assembly can be done well below the usually inviolate “ultimate” glass transition temperature without vitrification and in less time. The unique kinetics and thermodynamics of microwave energy produce high chemical reactivity even after the high-viscosity thermoset gelation point. VFM-cured thermosets are highly uniform with less stress and warpage even on large substrates and panels. Field uniformity and penetration depth produce better adhesion and higher fracture strength. The lower process temperatures inherently produce more stable and reliable final products and allow for less costly low-temperature build materials and temperature-sensitive device designs. The anneal and activation process temperatures of implanted ions in silicon can also be reduced by half with VFM, which results in nearly zero dopant diffusion and high-quality SPE regrowth and low numbers of defect sites.

Breakthrough instruments and products: Biocompatible epoxies for medical device manufacturing.

This article discusses the use of biocompatible, two-part epoxies in medical devices. When used as adhesive encapsulants, these products improve the ruggedness of wire-bonded, chip-on-board microelectronic assemblies. Biocompatible products from Master Bond include EP42HT-2MED and the enhanced EP42HT-4AOMed Black product.

Interfacial reactions and mechanical properties of Sn–3.0Ag–0.5Cu solder with pure Pd or Pd(P) layers containing thin-Au/Pd/Ni(P) surface-finished PCBs during aging

The microelectronics packaging industry, although rapidly growing, faces several challenges including 3-D integration, issues with multifunctional capability, and fluctuating input/output (I/O) density, among others. Better-performing microelectronics assemblies for mitigating these challenges require alloys with superior solderability and minimal metallization layer thickness. To this end, in this study, we investigated two kinds of electroless-nickel electroless-palladium immersion gold (ENEPIG) with 0.3 μm Ni, 0.1 μm pure Pd or Pd-phosphorous (Pd(P)), and 0.1 μm Au layers plated on a printed circuit board (PCB) substrate. To analyze the effects of the pure Pd and Pd(P) layers in the thin ENEPIG, we evaluated the interfacial reactions and mechanical properties of the SAC305 solder with a pure Pd or Pd(P) layer in the thin ENEPIG joints after aging at 150 °C. Needle-type and chunky-type (Cu,Ni)6Sn5 IMCs were formed at the interfaces of the pure Pd and Pd(P) joints, respectively. The (Cu,Ni)6Sn5 IMC of the pure Pd joint was thinner than that of the Pd(P) joint after reflowing and aging for 100 h. However, the total IMC of the Pd(P) joint was thinner than that of the pure Pd joint from 250 to 1000 h. In a low-speed shear test, the shear strength of the Pd(P) joint was higher than that of the pure Pd joint for the entire aging time. Most fractures occurred at the Sn-rich surface with a ductile mode, regardless of the different substrates and aging times. After high-speed shear testing, the shear strength of the pure Pd joint was higher than that of the Pd(P) joint until aging for 100 h. After aging for 250 h, the shear strength of the Pd(P) joint was higher than that of the pure Pd joint. The results for brittle fracture rate were similar to those for high-speed shear strength. Hence, Pd(P) joints are expected to demonstrate higher reliabilities than pure Pd joints after long aging treatment.

Fatigue Behavior of SAC-Bi and SAC305 Solder Joints With Aging

Reliability of microelectronic assemblies is typically limited by the fatigue failure of one of the interconnected solder joints. The fatigue behavior of the lead-free solder joints doped with bismuth under different stress loading and aging conditions is not yet understood. This article investigates the effect of adding bismuth on the mechanical reliability of SAC alloys considering different loading and aging conditions. The fatigue behavior and shear strength of individual SAC305 (Sn–3.0Ag–0.5Cu) and SAC-Q (Sn–3.4Ag–0.5Cu–3.3Bi) solder joints are examined and compared. A unique experiment is designed to test the individual solder joints using a micromechanical testing system. The results show that the fatigue life and shear strength of SAC-Q with Bi are much higher than SAC305 regardless of the aging and stress conditions. It was also found that increasing stress amplitude leads to a decrease in the fatigue life for both alloys. The aging time has a negative effect on the fatigue life and shear strength of both alloys. The impact of aging on SAC-Q solder joints is significantly less than that for SAC305. Microstructure analysis shows a substantial amount of precipitates coarsening with aging for SAC305 compared with SAC-Q. Hysteresis loop analysis shows that increasing the cycling stress amplitude and aging time leads to an increase in the work per cycle and plastic strain. Common fatigue models, such as Morrow energy model and Coffin–Manson model, fail to predict the life considering the effect of aging; aging affects the constants of both models.

Effects of Ni and Cu Antisite Substitution on the Phase Stability of CuGa2 from Liquid Ga/Cu–Ni Interfacial Reaction

Ga and Ga-based alloys have received significant attention for applications in the liquid state and also for their potential as a bonding material in microelectronic assemblies. This study investigates the phase stability of the CuGa2 phase as a product of the interfacial reaction between liquid Ga and Cu-10Ni substrates at room temperature. In the binary Ga-Cu system, CuGa2 is decomposed into liquid Ga and Cu9Ga4 as the temperature increases to around 260 °C, which prevents the widespread application of this alloy. In contrast to CuGa2 grown from a pure Cu substrate, CuGa2 from the Cu-10Ni substrate shows an increase in the decomposition temperature during heating from 25 to 300 °C. According to our first-principle calculations, there is only a minor difference in the total free energy between Ni solute at the Cu sublattice and the Ga sublattice in the tetragonal CuGa2 crystal structure. This result indicates that both of the sublattices can accommodate the dilute Ni solute with comparable probability. Regardless of the sublattice where the Ni impurities are located, the presence of diluted Ni in the matrix stabilizes the CuGa2 system by inducing some localized Ni 3d states at energy levels near the Fermi level. It is also shown that the formation of Cu antisite defects, which also stabilizes CuGa2, is preferable if the CuGa2 matrix is grown on a Ni-containing substrate.

Effects of Thermal Cycling on Creep of SnAgCu Solder Joints

The long-term life of properly optimized high-end microelectronics assemblies is commonly limited by fatigue of the solder joints. The most credible assessments of this rely on modeling-based extrapolation and generalization of accelerated test results. As the validity of extrapolations to long-term service can rarely if ever be verified experimentally, there is a strong need for mechanistically justified models. The models all rely on predictions of stresses, strains, and perhaps functions of those versus time and temperature in cycling. Finite-element-based predictions of these require the assumption of relatively complex constitutive relations capable of predicting inelastic strain rates under continuously varying stresses and temperatures. These are usually extracted from a series of creep or stress relaxation experiments and generalized under the implicit assumption that the inelastic deformation is dominated by dislocation creep. However, the resulting constitutive relations were recently shown to be strongly misleading. It was suggested that this is a result of the inelastic deformation at the stresses and temperatures of primary concern actually being dominated by dislocation core diffusion. This paper lends further support for this picture, showing additional contributions from diffusion on cycling induced dislocation structures to make for ongoing, usually nonmonotonic, variations in deformation rates from cycle to cycle. These effects are certain to have major consequences for modeling. In fact, it has been argued that the combination of wrong constitutive relations with a wrong damage function has led to a partial cancellation of errors across a limited parameter range, but that this cannot be counted on for more detailed predictions of accelerated test results and does not allow for interpretation of such results in terms of even qualitative trends in service.

Thermal state of electronic assemblies equipped with an array of heaters and coolers (HACs) subjected to natural convection

In this study, the thermal state of microelectronic assemblies equipped with an array of heaters and coolers (HACs) subjected to the natural convection is described. According to the intended electronics application, a 3×3 array of distinct heat sources and a 2×2 array of distinct coolers are connected on one perpendicular wall of the rectangular module. The rectangular enclosure is entirely occupied by porous material permeated with a water-Cu nanofluid. The Brinkman and Forchheimer extended Darcy flow model is employed to model the fluid flow within the porous material. 3D Navier-Stokes and energy equations are solved numerically based on the finite volume discretization technique. Thermal state and flow field are analyzed, regarding the wide range of considered parameters namely, the Darcy number, the rectangular module side aspect ratio, the Rayleigh number and the nanoparticles volume fraction. The outcomes expose that the overall Nusselt number intensifies by mixing the Cu powder nanoparticles into the base fluid and with an increase in the Rayleigh number. The heat transfer attains its maximum when the side aspect ratio of the module assumes values between 1.5 and 2. This work helps to improve thermoregulation of electronic assemblies via nanofluid saturated porous media.

Influence of Interfacial Intermetallic Growth on the Mechanical Properties of Sn-37Pb Solder Joints under Extreme Temperature Thermal Shock

Solder joints in thermally uncontrolled microelectronic assemblies have to be exposed to extreme temperature environments during deep space exploration. In this study, extreme temperature thermal shock test from −196 °C to 150 °C was performed on quad flat package (QFP) assembled with Sn-37Pb solder joints to investigate the evolution and growth behavior of interfacial intermetallic compounds (IMCs) and their effect on the pull strength and fracture behavior of Sn-37Pb solder joints under extreme temperature environment. Both the scallop-type (Cu, Ni)6Sn5 IMCs at the Cu lead side and the needle-type (Ni, Cu)3Sn4 IMCs at the Ni-P layer side changed to plane-type IMCs during extreme temperature thermal shock. A thin layer of Cu3Sn IMCs was formed between the Cu lead and (Cu, Ni)6Sn5 IMC layer after 150 cycles. The growth of the interfacial IMCs at the lead side and the Ni-P layer side was dominated by bulk diffusion and grain-boundary diffusion, respectively. The pull strength was reduced about 31.54% after 300 cycles. With increasing thermal shock cycles, the fracture mechanism changed from ductile fracture to mixed ductile–brittle fracture, which can be attributed to the thickening of the interfacial IMCs, and the stress concentration near the interface caused by interfacial IMC growth.

Additive Manufacturing for Multi-chip Modules

Abstract The implementation of microelectronics, also known as multi-chip modules (MCM), is extensive in automotive, downhole and aerospace applications. MCMs have already demonstrated high-temperature performance, step improvement in reliability, and the potential to reduce product cost through miniaturization and integration of more functions. However, there are barriers preventing wider adoption of MCM technology in downhole applications. High non-recurring expenditures (NRE) charges increase development costs. Long substrate lead times prolong the time to market. Lengthy design iterations make it difficult to apply lean startup methodology to accelerate innovation. The main factor that leads to high NRE and long lead times is the complexity of substrate manufacturing processes. Together with assembly, MCM manufacturing comprises at least 11 steps, 6 different materials, 10 or more different machines, and requires a minimum of 6 supporting employees. A new concept proposes a simplified process to reduce labor and expenses. With best implementation, this process would require only a single machine capable of cycling through 3-step process of dispensing, placement and cure. Despite the dramatically simplified process, the constructional complexity of circuits can still be very high, such as a 3D multilayer MCM. In this paper, this concept was evaluated, micro-dispensing equipment was used to create basic circuitry blocks. Different materials to create conductive traces, isolation layers and wire bond replacement were evaluated. High-temperature aging tests were conducted to monitor the electrical and mechanical performance under thermal stress. The feasibility of dispensing fine features using dispensing and jetting methods are presented in the study. Conductors are a critical part in microelectronic assemblies because they create interconnects and thermal dissipation paths for microelectronics. Three different conductor materials were tested for their dispensability, resistance, continuity at temperature, and coefficients of thermal expansion (CTE) compatibility with different materials under thermal cycling. For dielectric materials, the requirements were to create various assembly constructs. The characterization included dispensability, electrical insulation, breakdown voltage, high-temperature performance, and the effects of CTE. Different approaches with different materials were tested for feasibility for wire bonding replacement. The application needs fine feature size with medium resistance lines. Consequently, the criteria for the material selection are fine particle size and medium sheet resistance. For high-power devices where heavy-gauge wires were used, jet dispensing is applicable. For other application with regular wire diameters, direct write is used. The over-all tests demonstrated the feasibility of using dispensed materials to replace wire bonds, which brings better reliability for shock and vibration, as compared to traditional wire bonds. The reliability of this approach requires a set of optimally matched conductive and dielectric materials. Three conductive materials (A, B and C) and three dielectric materials (D, E and F) were evaluated in this study. Tested conductive epoxy A can be used for attachment of SMT components with non-tin terminals, short traces, and wire bonding replacement for 25-μm wires, but it is not ideal for fine lines(<65um). Tested conductive epoxy B can be used for fine traces (58μm), and wire bonding replacement for 25-μm wires. The resistance of that material is not ideal. Nano-silver paste can be used for long traces, heavy-gauge wire bonding replacement, pads/polygons, the sheet resistance is equivalent to 0.5Oz Cu. For dielectrics, epoxy C can be used for crossovers, dielectric layers, and components staking. Epoxy D can be used for die edge insulation, but it is not ideal. Epoxy E can be used for crossovers and components staking. Epoxy F can be used for encapsulation and components staking. The wire bonding replacement concept structure is established with the dielectric forming the insulation around die edge, then the conductive wires dispensed on top of it. Feasibility was confirmed, a proof-of-concept was built, and some level of thermal stress was tested on the samples. Particle size and viscosity are critical to achieve fine features for micro-dispensing conductors and dielectrics. Periodic evaluations must be conducted to follow up on industry's progress with materials.

Predicting delamination in multilayer composite circuit boards with bonded microelectronic components

The present work developed a mixed-mode cohesive zone model (CZM) with a mode I failure criterion to predict the delamination bending loads of multilayer, composite printed circuit boards (PCBs) assembled with soldered ball grid array (BGA) components that were reinforced with an underfill epoxy adhesive. Two different delamination modes were observed in these microelectronic assemblies: delamination at the interface between the solder mask and the first conducting layer of the PCB, and PCB subsurface delamination at the interface between the epoxy and glass fibers of one of the prepreg layers. The cohesive parameters for each of the two crack paths were obtained from fracture tests of bending test specimens consisting of PCB substrates bonded with the underfill adhesive. The model provided relatively accurate predictions of the crack paths and the bending strength of the actual underfilled BGA-PCB assemblies for a range of adhesive fillet sizes, PCB stiffnesses, and strain rates.

High-Temperature Reliability of Wire Bonds on Thick Film

Abstract In a harsh environment, wire-bonded interconnects are critical for overall reliability of microelectronic assemblies. Aluminum is the dominating metallization of the die wire bonding pads and aluminum wires are used to achieve monometallic bonding system on die side. On the substrate side, a monometallic connection is not readily available and typically involves expensive aluminum thin-film deposition or labor-intensive bonding tabs. Nickel-palladium-gold galvanic or electro-less plating stacks are also used to improve bondability and reliability of non-monometallic Al wire bonds on the substrate side. However, these plating stacks do not perform well after excursions above 330°C that are needed for the attachment of die and passives prior to wire bonding. At these temperatures, both palladium and nickel diffuse through the gold and form surface oxides that degrade wire bondability. In monometallic wire-bonding schemes, in addition to aluminum wires gold wires within same assembly are often also needed, for example, when some die is only available with gold-plated bond pads, or to connect substrates to gold-plated pins of hybrid housings. A universal substrate metallization, compatible with aluminum wire and gold wire, is therefore desirable. Thin-film substrates produced by sequential deposition and etching of gold metal, barrier metals, then aluminum metal is a good working solution, but it can be as much as ten times more expensive than other types of substrates. Printed thick-film metallization, a well-established technology, have been widely used for hybrid substrates. Silver-based thick films are inexpensive and capable of accepting aluminum and gold bonds. However, the silver-aluminum bonds are seldom used because of intermetallic formation and subsequent degradation triggered by multiple factors like temperature, humidity, and the presence of halogens. Pd and Pt are often added to the Ag thick films to decrease this effect, but potential usability and the reliability of these formulations in extreme temperature environments is not well researched. For this study, samples of Pt/Ag thick-film metallization were printed on Al2O3 substrates, and 25-um and 250-um aluminum wires and 50-um gold wires were wedge bonded in daisy chain to the substrate. The test vehicles were subjected to high-temperature testing at 260°C and 280°C. Thermal cycling tests from −20°C to 280°C were also performed. Mechanical and electrical characterizations of the wire bonds were conducted periodically. These tests included resistance and pull-strength measurements. Failure analysis of the bond joints was performed to understand the results of the tests. The 250-um Al wire and 25-um Al wire showed no significant changes until a critical time-at-temperature was reached. After reaching this temperature, the wire/substrate interface resistance rapidly increased to values as high as 40 Ohms for the 25-um Al wires. However, the pull strength remained within standard throughout the tests of up to 1200 hours. The relationship between time to failure and the temperature is presented in the paper. There was a four times life increase of bonds with every 20°C. With gold wires, no dramatic increase of bond resistance was observed, only a slight increase with time. The pull strength of Au wires remained stable throughout the time at high temperature. The tested Ag/Pt thick film metallization was found to be compatible with bonding of the gold wires and the aluminum wires for high-temperature applications up to an Arrhenius equivalent of 800 hours at 260°C. Additionally, Parylene HT coating was vapor-deposited on one set of 250-um Al wire-bonding samples. This set of samples demonstrated doubling of its useful life as compared to the uncoated samples.

Encapsulation of Microelectronic Assemblies for use in Harsh Environments

Abstract Microelectronic systems that are intended for use in high shock and vibration environments are encapsulated to achieve stable and reliable operation. The physical design of the electronic assembly, the material properties of the encapsulant, and the magnitude and frequency of the inertial loading must all be factored into the system design. Overall robustness to shock and vibration are improved by minimizing the physical size and mass of the system, which increases its stiffness and reduces the magnitude of the inertial forces that must be supported. This work describes the development of an encapsulation process and facilities that are optimized for building high-reliability microelectronic systems that range between one and five cubic centimeters in volume. Finite Element Analysis (FEA) is used to ensure that sensitive components are not overstressed by the encapsulant as a result of residual curing stresses and inertial loading effects. Computational Fluid Dynamics (CFD) software is used to model the filling process, with the objective of identifying locations prone to void formation. The CFD models are validated via cross sectioning mechanical replicas of the system and by encapsulating enclosures fitted with viewing windows to allow sequential photographs of the progression of the fill frontier. During fabrication, the encapsulant is dispensed under vacuum while being observed with a stereoscopic microscope. An essential component of the process is characterization of the encapsulant materials. Coefficient of thermal expansion and cure shrinkage of the encapsulant are determined by casting a sample onto a thin metal strip and extracting stress parameters with equations of a bimetallic strip. The surface energies of the encapsulant on materials in the system are measured by a modified sessile drop technique in which the material is dispensed on a coupon, cured and then measured with a profilometer. These tests are performed on each lot of material when received and periodically afterwards to monitor the condition of inventory. This paper provides a detailed description of the design process and facilities using examples from representative products.

High temperature ageing of microelectronics assemblies with SAC solder joints

In some applications, electronic systems are expected to operate at high ambient temperature (e.g. 150°C). In this paper, we investigate the failure mechanism and microstructure evolution of solder-free (SAC) solder joints at a maximum temperature of 175°C. It is found that no new failure mechanisms are triggered, and that ageing tests for solder can be accelerated at 175°C. In particular, the growth rate of the interfacial intermetallic compound (IMC) is found to be consistent with that observed at lower temperatures.