MESFET Research Articles

SILICON-ON-INSULATOR MESFETS AT THE 45NM NODE

Metal-semiconductor field-effect-transistors (MESFETs) have been fabricated using a commercially available 45nm silicon-on-insulator (SOI) CMOS foundry with no changes to the process flow. Depending upon the layout dimensions, these n-channel, depletion mode devices can be designed for high current drive (IDSAT≥ 100mA/mm ), high operating frequency (fmax> 35 GHz ) or enhanced breakdown voltage (VBD> 25 V ). The design flexibility provided by the SOI MESFETs, coupled with the high performance of ULSI CMOS at the 45nm node will enable a variety of analog, RF and mixed signal applications.

A Threshold Voltage Simulation of Hydrogen-Terminated Diamond MESFETs

In this paper, the threshold voltage of diamond film-based metal-semiconductor field effect transistors (MESFETs) has been simulated using Silvaco TCAD tools. The drain current (Id) versus gate voltage (Vg) relationship, and the distribution of acceptors in diamond surface conduction layer were also investigated. From the simulation results, it was found that the gate length contributed the most to the threshold voltage, while the doping depth almost had no impact on the threshold voltage value.

Gallium oxide (Ga2O3) metal-semiconductor field-effect transistors on single-crystal β-Ga2O3 (010) substrates

We report a demonstration of single-crystal gallium oxide (Ga2O3) metal-semiconductor field-effect transistors (MESFETs). A Sn-doped Ga2O3 layer was grown on a semi-insulating β-Ga2O3 (010) substrate by molecular-beam epitaxy. We fabricated a circular MESFET with a gate length of 4 μm and a source–drain spacing of 20 μm. The device showed an ideal transistor action represented by the drain current modulation due to the gate voltage (VGS) swing. A complete drain current pinch-off characteristic was also obtained for VGS < −20 V, and the three-terminal off-state breakdown voltage was over 250 V. A low drain leakage current of 3 μA at the off-state led to a high on/off drain current ratio of about 10 000. These device characteristics obtained at the early stage indicate the great potential of Ga2O3-based electrical devices for future power device applications.

High-performance CdSe nanobelt based MESFETs and their application in photodetection

High performance metal–semiconductor field-effect transistors (MESFETs) based on single n-CdSe nanobelts (NBs) have been fabricated and applied as photodetectors. Au is used as the gate metal, which formed a good Schottky contact with the CdSe NB with a rectification ratio of about 2 × 108. The CdSe NB MESFETs exhibit a near-zero threshold voltage (−0.55 V), low subthreshold swing (60.4 mV per dec), no clearly observed current hysteresis, and the highest on/off current ratio (5 × 108) reported so far for NW/NB MESFETs. We have also investigated the photoresponse properties of these MESFETs. Typical CdSe NB MESFET based photodetectors have high current responsivity (∼1.4 × 103 A W−1), high gain (∼2.7 × 103), and fast photoresponse speed (the rise time and the decay time are about 35 and 60 μs, respectively.) under a gate voltage of −1 V. All these results show that the CdSe NB based MESFETs can be promising candidates for both electronic and opto-electronic nanodevices.

Effects of gate-buffer combined with a p-type spacer structure on silicon carbide metal semiconductor field-effect transistors

An improved structure of silicon carbide metal—semiconductor field-effect transistors (MESFET) is proposed for high power microwave applications. Numerical models for the physical and electrical mechanisms of the device are presented, and the static and dynamic electrical performances are analysed. By comparison with the conventional structure, the proposed structure exhibits a superior frequency response while possessing better DC characteristics. A p-type spacer layer, inserted between the oxide and the channel, is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge. Meanwhile, a lightly doped n-type buffer layer under the gate reduces depletion in the channel, resulting in an increase in the output current and a reduction in the gate-capacitance. The structural parameter dependences of the device performance are discussed, and an optimized design is obtained. The results show that the maximum saturation current density of 325 mA/mm is yielded, compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET, leading to an increase of 79% in the output power density. In addition, improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET, respectively.

Effects of the improved hetero-material-gate approach on sub-micron silicon carbide metal-semiconductor field-effect transistor

Based on the device operation mechanism and physical model, effects of the improved hetero-material-gate (HMG) approach on deep sub-micron silicon carbide (SiC) metal-semiconductor field-effect transistor (MESFET) are analyzed. By comparing with the conventional MESFET, it is shown that the improved HMG approach induces a multi-stepped distribution of the potential in the channel, leading to an enhanced electric field at the source. Meanwhile, the position of the maximum of the channel potential is changed to the drain side compared with the dual-material-gate (DMG) device, thus the carriers in the channel are accelerated more efficiently and the variation of potential caused by drain voltage is eliminated to a certain degree, resulting in a better restraint in short-channel effect. Also, different technological parameters are designed to study the dependence of the device performance and an optimization plan is obtained, leading to a decreased sub-threshold swing. In addition, asymmetric gate structures are designed for high power application, achieving an improved distribution of the electric field at the gate edge and an enhanced breakdown voltage of the small scale device.

Fabrication and electrical property of individual ZnO nanowire based mesfet

A metal-semiconductor field effect transistor was constructed with a ZnO nanowire by nanomanipulation and electrical properties were measured by a semiconductor characterization system. The contacts between ZnO nanowire and Ta source/drain electrodes were Ohmic, while Schottky barrier was formed between ZnO and the tungsten probe working as the gate. This MESFET was demonstrated to be depletion mode and the transconductance maximum was -2.1pA/V with the gate voltage of -5V. Moreover, the corresponding threshold voltage reduced by 1.37V as the source-drain voltage increased from 0V to 3V. The results indicated that these devices could be used as storage components.

Influence of Source/Drain Residual Implant Lattice Damage Traps on Silicon Carbide Metal Semiconductor Field-Effect Transistor Drain I-V Characteristics

Abstract 4H-SiC n-channel power metal semiconductor field-effect transistors (MESFETs) with nitrogen n+-implanted source/drain ohmic contact regions, with and without p-buffer layer fabricated on semi-insulating substrates exhibited hysteresis in the drain I-V characteristics of both types of devices at 300 K and 480 K due to traps. However, thermal spectroscopic measurements could detect the traps only in the devices without p-buffer. Device simulation and optical admittance spectroscopy (OAS) are used to resolve the discrepancy in the initial experimental characterization results. Device simulations and OAS suggest that, in addition to the semi-insulating (SI) substrate traps, acceptor traps due to source/drain residual implant lattice damage contribute to the hysteresis observed in the drain I-V characteristics of the devices. Simulations suggest these traps are contained in the lateral straggle of the implanted source and drain regions since the drain current largely flows between the un-gated edges of the source and drain through the volume of lateral straggle traps. Since hysteresis in I-V curves is a manifestation of the presence of defects in devices and since defects degrade carrier mobility and hence device performance, efforts should be made to minimize the source/drain lateral straggle implant damage.

New 4H silicon carbide metal semiconductor field-effect transistor with a buffer layer between the gate and the channel layer

A new 4H silicon carbide metal semiconductor field-effect transistor (4H-SiC MESFET) structure with a buffer layer between the gate and the channel layer is proposed in this paper for high power microwave applications. The physics-based analytical models for calculating the performance of the proposed device are obtained by solving one- and two-dimensional Poisson's equations. In the models, we take into account not only two regions under the gate but also a third high field region between the gate and the drain which is usually omitted. The direct-current and the alternating-current performances for the proposed 4H-SiC MESFET with a buffer layer of 0.2 μm are calculated. The calculated results are in good agreement with the experimental data. The current is larger than that of the conventional structure. The cutoff frequency (fT) and the maximum oscillation frequency (fmax) are 20.4 GHz and 101.6 GHz, respectively, which are higher than 7.8 GHz and 45.3 GHz of the conventional structure. Therefore, the proposed 4H-SiC MESFET structure has better power and microwave performances than the conventional structure.

Surface channel MESFETs on hydrogenated diamond

Metal–semiconductor field effect transistors (MESFETs) based on hydrogen terminated diamond were fabricated according to different layouts. Aluminum gates were used on single crystal and low-roughness polycrystalline diamond substrates while gold was used for ohmic contacts. Hydrogen terminated layers were deeply investigated by means of Hall bars and transfer length structures. Room temperature Hall and field effect mobility values in excess of 100 cm2 V−1 s−1 were measured on commercial and single crystal epitaxial growth (100) plates by using the same hydrogenation process. Hydrogen induced two-dimensional hole gas resulted in sheet resistances essentially stable and repeatable depending on the substrate quality. Self-aligned 400 nm gate length FETs on single crystal substrates showed current density and transconductance values >100 mA mm−1 and >40 mS mm−1, respectively. Devices with gate length LG = 200 nm showed fMax = 26.4 GHz and fT = 13.2 GHz whereas those fabricated on polycrystalline diamond, with the same gate geometry, exceeded fMax = 23 GHz and fT = 7 GHz. This work focused on the optimization of a self-aligned gate structure with respect to the fixed drain-to-source structure with which we observed higher frequency values; the new structure resulted in improvement of DC characteristics, better impedance matching and a reduction in the fMax/fT ratio.

A novel 4H–SiC SOI-MESFET with a modified breakdown voltage mechanism for improving the electrical performance

In this paper, we present the unique features exhibited by a novel 4H–SiC silicon-on-insulator (SOI) metal–semiconductor field effect transistor (MESFET) in which the active layer consists of an insulator region (ISOI-MESFET). The key idea in this work is to make the dominant breakdown voltage mechanism to be controlled by the channel breakdown and not by the gate breakdown as a result of a high electric field at the edge of the gate near the drain. We investigate the improvement in device performance with two-dimensional and two-carrier device simulation. Our simulation results show that the breakdown voltage of the ISOI-MESFET is higher than the conventional bulk-MESFET (CB-MESFET) and conventional 4H–SiC SOI-MESFET (CSOI-MESFET). In this study, we have shown that the saturation current of the proposed structure is larger than the CB-MESFET. Also, the cut-off frequency and maximum oscillation frequency of the ISOI-MESFET improve compared to the CB-MESFET. Therefore, the ISOI-MESFET has superior dc and RF performance compared to the similar device based on the conventional structures.

Operating mechanism of the organic metal-semiconductor field-effect transistor (OMESFET)

Organic metal-semiconductor field-effect transistors (OMESFETs) were fabricated with a polycrystalline organic semiconductor (pentacene) and characterized in order to systematically analyze their operation mechanism. Impedance measurements confirmed full depletion of the thick pentacene film (1 μ m) due to the low doping concentration of unintentional doping (typically less than 10 14 cm −3 ). The necessity of developing a specific device model for OMESFET is emphasized as the classical (inorganic) MESFET theory based on the depletion modulation is not applicable to a fully-depleted organic semiconductor. By means of joint electrical measurements and numerical simulation, it is pointed out that the gate voltage controls the bulk distribution of injected carriers, so that the competition between the gate and drain currents is critical for determining the operation mode. Finally, the geometrical effect is investigated with comparing a number of transistors with various channel widths and lengths.

A novel 4H–SiC MESFET with modified channel depletion region for high power and high frequency applications

In this paper, a novel 4H–SiC metal semiconductor field effect transistor (MESFET) with modified depletion region is introduced. The key idea in this work is modifying the depletion region in the channel for improving the electrical performances. The proposed structure consists of upper and lower gates. Also, the lower gate is divided into a number (N) of smaller step-shaped sections. Therefore, we have called the proposed structure multiple-recessed 4H–SiC MESFET (MR-MESFET). DC and RF characteristics of the MR-MESFET structure with various lower gate segments are analyzed by 2D numerical simulation. The simulated results show that as the number of the lower gate sections increases, the channel depletion region is modified and the drain current ( I D) enhances. Also, by increasing the number of the lower gate sections, the breakdown voltage ( V BR) enhances, too. Improvement of the I D and V BR leads to a further increase in the output power density of the device. Also, cut-off frequency ( f T), maximum oscillation frequency ( f max), and maximum available gain (MAG) improvements are achieved for the MR-MESFET structure with further number of the lower gate sections. The results show that the MR-MESFET structure with higher number of the lower gate segments has superior electrical characteristics and performances in comparison with the MR-MESFET structure with fewer number of the lower gate sections.

Flexible logic gates composed of high performance GaAs-nanowire-based MESFETs withMHz-dynamic operations

High performance NOT, NAND and NOR logic gates composed of GaAs-nanowire(NW)-based metal–semiconductor field-effect transistors (MESFETs) were constructed onflexible plastics through a noble top-down route. The representative GaAs-NW-basedMESFETs exhibited superior electrical characteristics such as a high mobility (∼3300 cm2 V − 1 s − 1), largeIon/Ioff ratio (∼108) and smallsubthreshold swing (∼70 mV/dec). The NOT, NAND and NOR logic gates showed a maximum voltage gain of 108 and logicswings of 97–99%. All of the logic gates successfully retained their electrical characteristicsduring 2000 bending cycles. Furthermore, the logic gates were well operated by square-wavesignals of up to 100 MHz under various strain conditions. The high performancesdemonstrated in this study open the way to the realization of high speed flexible logicdevices.

Top-Gate ZnO Nanowire Transistors and Integrated Circuits with Ultrathin Self-Assembled Monolayer Gate Dielectric

A novel approach for the fabrication of transistors and circuits based on individual single-crystalline ZnO nanowires synthesized by a low-temperature hydrothermal method is reported. The gate dielectric of these transistors is a self-assembled monolayer that has a thickness of 2 nm and efficiently isolates the ZnO nanowire from the top-gate electrodes. Inverters fabricated on a single ZnO nanowire operate with frequencies up to 1 MHz. Compared with metal-semiconductor field-effect transistors, in which the isolation of the gate electrode from the carrier channel relies solely on the depletion layer in the semiconductor, the self-assembled monolayer dielectric leads to a reduction of the gate current by more than 3 orders of magnitude.

Investigation of the novel attributes in double recessed gate SiC MESFETs at drain side

In this paper, the potential impact of drain side-double recessed gate (DS-DRG) on silicon carbide (SiC)-based metal semiconductor field effect transistors (MESFETs) is studied. We investigate the device performance focusing on breakdown voltage, threshold voltage, drain current and dc output conductance with two-dimensional and two-carrier device simulation. Our simulation results demonstrate that the channel thickness under the gate in the drain side is an important factor in the breakdown voltage. Also, the positive shift in the threshold voltage for the DS-DRG structure is larger in comparison with that for the source side-double recessed gate (SS-DRG) SiC MESFET. The saturated drain current for the DS-DRG structure is larger compared to that for the SS-DRG structure. The maximum dc output conductance in the DS-DRG structure is smaller than that in the SS-DRG structure.

A novel double-recessed 4H-SiC MESFET with partly undoped space region

In this paper, a novel double-recessed 4H-SiC metal semiconductor field effect transistor (MESFET) with partly undoped space region (DRUS-MESFET) is introduced. The key idea in this work is to improve the DC and RF characteristics of the device by introducing an undoped space region. Using two-dimensional and two-carrier device simulation, we demonstrate that breakdown voltage ( V BR) increases from 109 V in conventional double recessed MESFET (DR-MESFET) structure to 144.5 V in the DRUS-MESFET structure due to the modified channel electric field distribution of the proposed structure. The maximum output power density of the DRUS-MESFET structure is about 25.4% larger than that of the DR-MESFET structure. Furthermore, lower gate–drain capacitance ( C GD), higher cut-off frequency ( f T), larger maximum available gain (MAG), and higher maximum oscillation frequency ( f max) are achieved for the DRUS-MESFET structure. The results show that the f max and f T of the proposed structure improve 95.6% and 13.07% respectively, compared with that of the DR-MESFET structure. Also, the MAG of the DRUS-MESET is 4.5 dB higher than that of the DR-MESFET structure at 40 GHz. The results show that the DRUS-MESFET structure has superior electrical characteristics and performances in comparison with the DR-MESFET structure.

Traps in 4H-SiC Field-Effect Transistors Characterized by Capacitance- and Current-Mode Deep-Level Transient Spectroscopy

Traps in SiC long-gate metal–semiconductor field-effect transistors (FATFETs) at different wafer positions have been characterized by deep-level transient spectroscopy (DLTS) based on capacitance (C-DLTS) or current (I-DLTS). Two major electron traps, Z1/2 and V1/2, of energies 0.68 eV and 0.91 eV, respectively, are found mainly in the SiC buffer layer, and several hole-like traps appear in the surface or interface regions. In some regions of the wafer, an electron trap EH6/7 of energy 1.77 eV is prominent. Trap EH6/7 as well as the hole-like traps are not uniformly distributed on the wafer.

Monolithic Integration of Ultrafast Photodetector and MESFET in the GaN Material System

We have fabricated and characterized ultrafast metal–semiconductor–metal (MSM) photodetectors integrated with metal–semiconductor–field-effect-transistors (MESFETs) integrated in coplanar strip lines in the GaN/AlN/SiC material system. We recorded electrical transients of the single photodetector as short as 0.9 ps wide by optoelectric pump–probe measurements using 360-nm-wavelength and 100-fs-duration laser pulses. Electric photoresponse transients of the photodetector with 6-mV peak amplitude were amplified by the MESFET, resulting in 4-ps-wide and 35-mV peak amplitude signals. This monolithically integrated optoelectronic circuit is presented as a potential candidate for high-speed ultraviolet optoelectronics. <?Pub _bookmark="" Command="[Quick Mark]"?>

Justification of the stabilization method for a mathematical model of charge transport in semiconductors

An initial boundary value problem for a quasilinear system of equations is studied and effectively applied to numerically determine, by the stabilization method, stationary solutions of a hydrodynamic model describing the motion of electrons in the silicon transistor MESFET (metal semiconductor field effect transistor).