Metal-oxide Resistive Random Access Memory Research Articles

A cold-electrode metal–oxide resistive random access memory

To reduce the leakage and power consumption of metal–oxide resistive random access memory (RRAM), we propose and fabricate a cold-electrode (CE) RRAM (CE-RRAM) by extending the mechanism of cold-source FETs. First-principles calculations show that the n-Si/TiN composite CE can filter electrons with energy within the Si bandgap, which contribute to leakage current. A n-Si/TiN/HfOx/Pt CE-RRAM with low leakage current and large on/off current ratio was designed and fabricated. Comparative analysis with conventional RRAM demonstrates over a 100-fold reduction in leakage current in a high resistance state and a tenfold improvement in the Ion/Ioff ratio. Additionally, the CE-RRAM effectively suppresses the overshoot effect in terminal I–V characteristics and exhibits good endurance, maintaining a 100 Ion/Ioff ratio after 104 cycles. Furthermore, even after 104 s at 100 °C, the state remains unchanged. Moreover, the CE-RRAM demonstrates its multi-level storage capability.

A Study on Unified Modelling Approach for Memristor: Next Generation Semiconductor Devices

This research investigates the voltage-current (V-I) characteristics of three distinct memristor models, each representing a unique composition and behaviour. The model, denoted as TiN-TiOx-HfOx-Pt-Bilayered Memristor model, is a compact representation designed for Metal–Oxide Resistive Random Access Memory (RRAM). Matlab tool is used for the simulation to analyse V-I characteristics of Memristor. Through comprehensive analysis and simulations, we aim to provide a detailed insight into the intrinsic behaviours of the memristor models. Understanding the V-I characteristics of these models is crucial for their potential applications in emerging memory technologies. This Study elaborate the mathematical modelling of memristor with the outcome untuned V-I Characteristics - DC Switching characteristics. The findings contribute to the broader field of memristor research, fostering advancements in electronic memory devices and computational systems

Oscillatory Circuits With a Real Non-Volatile Stanford Memristor Model

Stanford memristor model is a widely used model that accurately characterizes real non-volatile metal-oxide resistive random access memory (RRAM) devices with bipolar switching characteristics. The paper studies for the first time the dynamics and bifurcations in a class of nonlinear oscillators with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">real non-volatile memristor devices</i> obeying Stanford model. This is in contrast with papers in the literature considering oscillators with ideal, abstract, or artificial memristor models, that are unable to describe physical memristors implemented in nanotechnology. One main new idea in the paper is to use the memristor as a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">programmable nonlinear resistor</i> . Namely, two principal modes of operation are considered. 1) Analogue transient phase: the oscillator is designed so that in the transient oscillations the voltage on the memristor is below threshold, hence the main memristor state variable, i.e., the gap of the insulating material, is almost constant and the memristor behaves as a static nonlinear resistor. 2) Programming phase: the nonlinear characteristic of the memristor, which depends on the gap, can be changed via the application of voltages above threshold. The paper studies nonlinear oscillations in the transient phase for a fixed gap as well as the bifurcations phenomena displayed when the gap is varied. The paper also discusses the differences between the approach in the paper and those to design other memristor oscillators with non-volatile memristors.

Physics-Based Stochastic Three-Dimensional Modeling for Metal–Oxide Resistive Random Access Memory

In this work, a fully physics-based stochastic 3-D modeling of metal–oxide-based resistive random access memory (RRAM) device has been conducted. In contrast to general 1-D or 2-D modeling of RRAM devices, 3-D modeling is able to provide a picture of the evolution of the 3-D random distributions of oxygen vacancies and temperature inside the device during the forming and SET/RESET processes. The modeling confirms that a tunneling gap between the top electrode (TE) which serves as an oxygen ion reservoir and the tip of the conductive filament may form at a high resistive state, which is assumed in the frequently used compact models of RRAM devices. The modeling shows that the sites with high temperature are concentrated in a cylindrical region at the center of the RRAM device, running from the inert bottom electrode to the TE. The modeling can reproduce both typical current-voltage characteristics of metal–oxide RRAM devices in forming and RESET and SET operations under a dc voltage sweep and the modulation of RRAM conductance by SET/RESET pulses.

Empirical metal-oxide RRAM device endurance and retention model for deep learning simulations

Memristive devices including resistive random access memory (RRAM) cells are promising nanoscale low-power components projected to facilitate significant improvement in power and speed of Deep Learning (DL) accelerators, if structured in crossbar architectures. However, these devices possess non-ideal endurance and retention properties, which should be modeled efficiently. In this paper, we propose a novel generalized empirical metal-oxide RRAM endurance and retention model for use in large-scale DL simulations. To the best of our knowledge, the proposed model is the first to unify retention-endurance modeling while taking into account time, energy, SET-RESET cycles, device size, and temperature. We compare the model to state-of-the-art and demonstrate its versatility by applying it to experimental data from fabricated devices. Furthermore, we use the model for CIFAR-10 dataset classification using a large-scale deep memristive neural network (DMNN) implementing the MobileNetV2 architecture. Our results show that, even when ignoring other device non-idealities, retention and endurance losses significantly affect the performance of DL networks. Our proposed model and its DL simulations are made publicly available.

A simplified method to determine carrier transport mechanisms of metal-oxide resistive random access memory (RRAM) devices

The current carrier transport mechanism in non-linear resistance states of the current–voltage (I–V) curves of the resistance changing or resistive switching (RS) based random access memory (RRAM) devices would help to understand the physics behind the resistive switching phenomena. The non-linear portion of the I–V curves are most commonly categorized by three different types of conduction mechanisms, the space charge limit current (SCLC), the Schottky emission (SE) and the Poole-Frenkel (P-F) effect respectively. In this study, the current–voltage curves of the RS devices limited to the non-linear region were plotted on a log–log scale with the purpose of distinguishing the dominant current conduction mechanisms. Each of the I–V curves narrowed to the non-linear region were re-plotted for SCLC at the scale of I vs. V2, for SE at the scale of ln I vs. √V and for P-F at the scale of ln I/V vs. √V. The linear fitting lines were plotted and calculated for each one using linear fitting techniques. The slopes of the fitting lines were found respect to the scales using linear fitting equations. The conduction mechanisms of the devices were determined numerically using the degree of linearity of the slopes. Finally, the offered method was applied to TiO2 based resistive switching device.

Recent Progress in Solution-Based Metal Oxide Resistive Switching Devices.

Metal oxide resistive switching memories have been a crucial component for the requirements of the Internet of Things, which demands ultra-low power and high-density devices with new computing principles, exploiting low cost green products and technologies. Most of the reported resistive switching devices use conventional methods (physical and chemical vapor deposition), which are quite expensive due to their up-scale production. Solution-processing methods have been improved, being now a reliable technology that offers many advantages for resistive random-access memory (RRAM) such as high versatility, large area uniformity, transparency, low-cost and a simple fabrication of two-terminal structures. Solution-based metal oxide RRAM devices are emergent and promising non-volatile memories for future electronics. In this review, a brief history of non-volatile memories is highlighted as well as the present status of solution-based metal oxide resistive random-access memory (S-RRAM). Then, a focus on describing the solution synthesis parameters of S-RRAMs which induce a massive influence in the overall performance of these devices is discussed. Next, a precise analysis is performed on the metal oxide thin film and electrode interface and the recent advances on S-RRAM that will allow their large-area manufacturing. Finally, the figures of merit and the main challenges in S-RRAMs are discussed and future trends are proposed.

Bidirectional Volatile Signatures of Metal-Oxide Memristors—Part II: Modeling

Volatility in metal-oxide resistive random access memory (RRAM) families has mostly been treated as an unwanted side-effect, although recently there are trends to interpret such behavior as an additional technological feature. To date, the field has seen early demonstrations of possible applications that harness volatility. Moreover, some work has been conducted to understand both the mechanisms responsible for this behavior. In the context of modeling RRAM volatility, we still lack a comprehensive model that could allow simulations in a larger scale. In an attempt to fill this gap, this work presents a modeling framework that can account for RRAM relaxation characteristics. Specifically, we show how volatility can be simulated to significant accuracy when the resistive state (RS) of a device as well as the stimulus protocol in use are well-defined. Importantly, our approach is solely data-driven and decoupled from previous physical modeling studies on volatility. Our results work for both stimulation polarities and are consistent for a number of $TiO_{x}$ devices in use. Moreover, the mathematical relations that unfold via modeling volatility provide further intuition on the effect that invasive protocols can have on this technology. This modeling solution enables more advanced studying of memristive technologies in one hand, as well as more intricate designs of larger systems that can account for transient RRAM changes over time.

STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization

Processing-in-memory (PIM) exploits massive parallelism with high energy efficiency and becomes a promising solution to the von Neumann bottleneck. Recently, the emerging metal-oxide resistive random access memory (RRAM) shows its potential to construct a PIM architecture, because several stateful logic operations, e.g., IMP and NOR, can be executed in an RRAM crossbar in parallel. Previous synthesis flows focus on improving latency with stateful logic operations, but they ignore that the memory should be used primarily for storage. i.e., most of the area in the crossbar is used for computation but not storage. In this situation, storage and computation still have to be separated into different crossbars, which leads to considerable data transfer overhead and limited parallelism. In this work, we define the ratio of storage in a crossbar as area utilization. We aim to improve the area utilization without throughput loss by proposing STAR, a novel synthesis flow for the stateful logic. We present two optimization strategies to reduce the computation area in STAR. First, we reduce the area for redundant inputs. For the shared constants among different rows (or columns), we encode them as immediate values into the control signals without writing them into the crossbar at runtime. For the other inputs, we only store one copy of them in the crossbar. Second, we reduce the area for intermediate variables by reusing invalid cells. And we design a scheduling algorithm to find a computation sequence with the minimal variable erasing cycles. Invalid primary inputs can also be erased in this algorithm. Furthermore, we present a case study of the image convolution to demonstrate the effectiveness of STAR. Experimental evaluation shows that STAR achieves 33.03% more area utilization and a 1.43x throughput compared to SIMPLER, the state-of-the-art stateful logic synthesis flow. Our image convolution implementation also provides 78.36% more area utilization and a 1.48x throughput compared with IMAGING, the state-of-the-art stateful logic-based image processing accelerator.

Circuit design of RRAM-based neuromorphic hardware systems for classification and modified Hebbian learning

This paper proposes a solution to the learning of neuromorphic hardware systems based on metal-oxideresistive random access memory (RRAM) arrays, which are used as binary electronic synapses. A modified Hebbian learning method is developed to update the binary synaptic weights, and mixed-signal circuits are designed to implement the proposed learning method. The circuits are verified by SPICE, and systematic simulations are also conducted to verify the capability of the neuromorphic system to process relatively large databases. The results show that the system presents high processing speed ($10^6$ examples per second) for both classification and learning, and a high recognition accuracy (up to 95.6%) on the MNIST database.

TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks

The training of neural networks (NN) is usually time-consuming and resource intensive. The emerging metal-oxide resistive random-access memory (RRAM) device has shown potential for the computation of NN. RRAM crossbar structure and multibit characteristics can perform the matrix-vector product in high energy efficiency, which is the most common operation of NN. Two challenges exist for realizing training NN based on RRAM. First, the current architectures based on RRAM only support the inference in training NN and cannot perform the backpropagation (BP) and the weight update of training NN. Second, training NN requires enormous iterations to constantly update the weights for reaching the convergence. However, this weight update leads to large energy consumption because of the nonideal factors of RRAM. In this paper, we propose a training-in-memory based on RRAM (TIME) architecture and the peripheral circuit design to enable training NN on RRAM. TIME supports the BP and the weight update while maximizing the re-usage of peripheral circuits of the inference operation on RRAM. Meanwhile, a set of optimization strategies focusing on the nonideal factors are designed to reduce the cost of tuning RRAM. We explore the performance of both supervised learning (SL) and deep reinforcement learning (DRL) on TIME. A specific mapping method of DRL is also introduced to further improve energy efficiency. Simulation results show that in SL, TIME can achieve $5.3{\times }$ higher energy efficiency on average compared with DaDianNao, an application-specific integrated circuits (ASIC) in CMOS technology. In DRL, TIME can perform an average $126{\times }$ higher than GPU in energy efficiency. If the cost of tuning RRAM can be further reduced, TIME has the potential to boost the energy efficiency by two orders of magnitudes compared with ASIC.

Design and Hardware Implementation of Neuromorphic Systems With RRAM Synapses and Threshold-Controlled Neurons for Pattern Recognition

In this paper, a hardware-realized neuromorphic system for pattern recognition is presented. The system directly captures images from the environment, and then conducts classification using a single layer neural network. Metal-oxide resistive random access memory (RRAM) is used as electronic synapses, and threshold-controlled neurons are proposed as postsynaptic neurons to save the system area and simplify the operation. In the proposed threshold-controlled neuron, no capacitor is utilized, which contributes to higher integration density. The total energy consumption of RRAM synapses for classifying an example is 0.31μJ on average. The proposed system has been implemented on hardware, and has been experimentally demonstrated to show the capability of pattern recognition.

Analysis and Simulation of Capacitor-Less ReRAM-Based Stochastic Neurons for the in-Memory Spiking Neural Network.

The stochastic neuron is a key for event-based probabilistic neural networks. We propose a stochastic neuron using a metal-oxide resistive random-access memory (ReRAM). The ReRAM's conducting filament with built-in stochasticity is used to mimic the neuron's membrane capacitor, which temporally integrates input spikes. A capacitor-less neuron circuit is designed, laid out, and simulated. The output spiking train of the neuron obeys the Poisson distribution. Using the 65-nm CMOS technology node, the area of the neuron is , which is one ninth the size of a 1-pF capacitor. The average power consumption of the neuron is 1.289 W. We introduce the neural array-A modified one-transistor-one-ReRAM (1T1R) crossbar that integrates the ReRAM neurons with ReRAM synapses to form a compact and energy efficient in-memory spiking neural network. A spiking deep belief network (DBN) with a noisy rectified linear unit (NReLU) is trained and mapped to the spiking DBN using the proposed ReRAM neurons. Simulation results show that the ReRAM neuron-based DBN is able to recognize the handwritten digits with 94.7% accuracy and is robust against the ReRAM process variation effect.

Stuck-at Fault Tolerance in RRAM Computing Systems

Emerging metal-oxide resistive switching random-access memory (RRAM) devices and RRAM crossbars have demonstrated their potential in boosting the speed and energy-efficiency of analog matrix-vector multiplication. However, due to the immature fabrication technology, commonly occurring Stuck-At-Faults (SAFs) seriously degrade the computational accuracy of an RRAM-based computing system (RCS). In this paper, we present a fault-tolerant framework for RCS. A mapping algorithm with inner fault tolerance is proposed to convert matrix parameters into RRAM conductances in RCS and tolerate SAFs by fully exploring the available mapping space. Two baseline redundancy schemes are proposed to ensure that RCS is effective when the percentage of faulty RRAM cells is high. To reduce the number of redundant RRAM cells when the SAFs follow a non-uniform distribution or an unknown distribution, a distribution-aware redundancy scheme and a re-configurable redundancy scheme are proposed to provide dynamic fault tolerance. Simulation results show that, the baseline redundancy schemes can improve the recognition accuracy of the MNIST data set to almost the same as the RRAM-fault-free case, with an energy overhead of approximately 30%. When SAFs follow a non-uniform and an unknown distribution, the distribution-aware and re-configurable schemes can reduce the number of redundant RRAM cells from more than 200% to less than 40% and 60%, respectively, without reducing the recognition accuracy.

A Novel ReRAM-Based Processing-in-Memory Architecture for Graph Traversal

Graph algorithms such as graph traversal have been gaining ever-increasing importance in the era of big data. However, graph processing on traditional architectures issues many random and irregular memory accesses, leading to a huge number of data movements and the consumption of very large amounts of energy. To minimize the waste of memory bandwidth, we investigate utilizing processing-in-memory (PIM), combined with non-volatile metal-oxide resistive random access memory (ReRAM), to improve both computation and I/O performance. We propose a new ReRAM-based processing-in-memory architecture called RPBFS, in which graph data can be persistently stored and processed in place. We study the problem of graph traversal, and we design an efficient graph traversal algorithm in RPBFS. Benefiting from low data movement overhead and high bank-level parallel computation, RPBFS shows a significant performance improvement compared with both the CPU-based and the GPU-based BFS implementations. On a suite of real-world graphs, our architecture yields a speedup in graph traversal performance of up to 33.8×, and achieves a reduction in energy over conventional systems of up to 142.8×.

Investigation of resistance switching in SiOx RRAM cells using a 3D multi-scale kinetic Monte Carlo simulator

We employ an advanced three-dimensional (3D) electro-thermal simulator to explore the physics and potential of oxide-based resistive random-access memory (RRAM) cells. The physical simulation model has been developed recently, and couples a kinetic Monte Carlo study of electron and ionic transport to the self-heating phenomenon while accounting carefully for the physics of vacancy generation and recombination, and trapping mechanisms. The simulation framework successfully captures resistance switching, including the electroforming, set and reset processes, by modeling the dynamics of conductive filaments in the 3D space. This work focuses on the promising yet less studied RRAM structures based on silicon-rich silica (SiOx) RRAMs. We explain the intrinsic nature of resistance switching of the SiOx layer, analyze the effect of self-heating on device performance, highlight the role of the initial vacancy distributions acting as precursors for switching, and also stress the importance of using 3D physics-based models to capture accurately the switching processes. The simulation work is backed by experimental studies. The simulator is useful for improving our understanding of the little-known physics of SiOx resistive memory devices, as well as other oxide-based RRAM systems (e.g. transition metal oxide RRAMs), offering design and optimization capabilities with regard to the reliability and variability of memory cells.

Metal oxide resistive switching memory: Materials, properties and switching mechanisms

Abstract With the continuously changing landscape of the computer technologies, a new memory type is needed that will be fast, energy efficient and long-lasting. It shall combine the speed of random access memory (RAM) and non-volatile in the same time. Resistive RAM (RRAM) is one of the most promising candidates in this respect. RRAM has attracted a great deal of attention owing to its potential as a possible replacement for flash memory in next-generation nonvolatile memory (NVM) applications. A brief summary of binary metal oxide RRAM is given in this review. We discuss the RRAM technology development based on published papers, including the mechanism of resistive switching in transition metal oxides, resistive switching materials, device structure, properties, and reliability such as endurance and retention of the device. We also provide possible solutions through innovations in device materials, structures, and understanding the device physics.

Impact of ultra-thin Al2O3–y layers on TiO2–x ReRAM switching characteristics

Transition metal-oxide resistive random access memory devices have demonstrated excellent performance in switching speed, versatility of switching and low-power operation. However, this technology still faces challenges like poor cycling endurance, degradation due to high electroforming (EF) switching voltages and low yields. Approaches such as engineering of the active layer by doping or addition of thin oxide buffer layers have been often adopted to tackle these problems. Here, we have followed a strategy that combines the two; we have used ultra-thin Al2O3–y buffer layers incorporated between TiO2–x thin films taking into account both 3+/4+ oxidation states of Al/Ti cations. Our devices were tested by DC and pulsed voltage sweeping and in both cases demonstrated improved switching voltages. We believe that the Al2O3–y layers act as reservoirs of oxygen vacancies which are injected during EF, facilitate a filamentary switching mechanism and provide enhanced filament stability, as shown by the cycling endurance measurements.

(Invited) Compliance-Free Pulse Forming of Filamentary RRAM

Despite the overwhelming effort to improve the efficacy of resistive random access memory (RRAM), the underlying physics governing RRAM operation have proven elusive. Consequently, substantial effort has been spent to empirically develop transition metal oxide (filamentary) RRAM structures which exhibit reasonable behavior [1,2]. A survey of the recent literature almost universally indicates that the remaining glaring issues center around device variability as well as endurance. Perhaps the only consensus in the RRAM community is that these issues are linked to the forming process [2,3]. The forming process is an initial conditioning step in which voltage is applied across the dielectric stack to form, or break-down, the oxide via the formation of a resistive filament [2,3]. The forming process is thought to greatly determine the subsequent behavior of the device [2,3]. Thus, the vast majority of this presentation will detail our recent efforts to bring the forming process under control and the resulting improvements in RRAM viability in HfO2-based devices. The vast majority of efforts to control the forming process all involve the inclusion of an additional series resistor element to limit the current that flows through the RRAM during forming (compliance). Our efforts show that even the most careful series resistor implementation still invokes a serious forming variability due to the unavoidable parasitic capacitance [4]. These parasitics introduce a current overshoot which greatly alters the ability to terminate forming (i.e. a large current continues to flow through the filament for some uncontrollable time before the compliance element can clamp) [4]. This introduces a relatively large uncertainty in the forming energy ((forming voltage) x (current) x (time)) and consequent variability in the filament [5]. This pitfall can be avoided by removing all current compliance elements, and their associated parasitics, and utilizing ultrashort voltage pulses to induce forming [5,6]. In this approach, the forming process can occur uncontrolled at any point in time during the voltage pulse. However, utilization of the ultrashort pulse width minimizes the timing uncertainty and bring the forming energy under control [5]. One can, of course, invoke multi-pulse approaches to further tune the forming energy to the specific RRAM device stack [5]. Using this approach, we show for nominally identical RRAM devices, varying the forming energy using ~100 ps pulses can greatly alter the variability as measured via the endurance window [5]. In extreme cases, we show that a change in forming energy can effectively open up an endurance window in a device which was unusable using more traditional forming methods [5]. In addition, we show (figure 1) further improvement in endurance when applying multiple pulse forming schemes to “tune” the forming energy to the desired value and consequent endurance [5]. In summary, we describe a new compliance-free RRAM forming technique that greatly enhances the energy control of the forming process and improves the device endurance characteristics proportionately. [1] Y. Shimeng, et al., IEDM, pp. 26.1.1 (2012) [2] B. Butcher, et al., IIRW, pp. 146 (2011) [3] A. Kalantarian, IRPS, pp. 6C.4.1 (2012) [4] P. Shrestha, et al., IIRW, pp. 55 (2013) [5] P. Shrestha, et al., IRPS, pp. MY.10.1 (2014) [6] P. Shrestha, et al., VLSI-TSA, pp. TR82 (2014) Figure 1

PRIME

Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360× and the energy consumption by ~895×, across the evaluated machine learning benchmarks.