Metal-nitride-oxide-semiconductor Research Articles

Electron Trap Characteristics of Silicon Rich Silicon Nitride Thin Films

Charge localization causes initial retention loss and memory window narrowing after write/erase cycling in a nonvolatile memory device using a metal–oxide–nitride–oxide–semiconductor (MONOS) structure. To overcome these problems, we propose the use of silicon-rich silicon nitride (SRN) thin film as a charge-trapping layer. It was found that most of the electrons injected from the substrate were trapped at the interface between the SRN film and the top oxide and the number of electrons captured by bulk traps of the nitride is negligible. When negative bias is applied to the gate electrode, the electrons trapped at the top interface move back to the bottom interface with SRN. The high effective mobility of the electrons is presumably due to donor-like traps at 0.8 eV below the conduction band bottom of SRN.

Metal–Oxide–Nitride–Oxide–Semiconductor Memory Device with One-Side Halo Implantation to Enable Low-Voltage Operation Using Hot-Carrier Injection

We have developed a metal–oxide–nitride–oxide–semiconductor (MONOS) memory device with one-side halo implantation, in which programming and erasing are performed by channel-hot-electron injection and hot-hole injection, respectively. This MONOS memory has a simple structure and is fabricated through the conventional complementary metal–oxide–semiconductor (CMOS) process before the specific process for the memory device. A threshold voltage shift of more than 3.0 V, obtained through a programming operation, results in a threshold voltage greater than the programming gate voltage and is sufficient to enable the 10-year lifetime of this device.

Visualization of electrons and holes localized in the thin gate film ofmetal-oxide-nitride-oxide-semiconductor type Flash memory by scanning nonlineardielectric microscopy

By applying scanning nonlinear dielectric microscopy (SNDM),we identified the position of electrons/holes existing in the gateSiO2–Si3N4–SiO2 (ONO) film of the metal-oxide-nitride-oxide-semiconductor(MONOS) type Flash memory. The electrons were detected in theSi3N4 part of the ONO film. The holes, on the other hand, were found in theSi3N4 film as well asin the bottom SiO2 film.

Narrow Distribution of Threshold Voltage in 4-Mbit MONOS Memory-Cell Array With F–N Channel Write and Direct/F–N Tunneling Erase Operation as a Single Transistor Structure

This paper describes the narrow and nonspreading distribution of threshold voltage in metal-oxide-nitride-oxide semiconductor (MONOS) memory cell array with Fowler-Nordheim (F-N) channel write operation and direct/F-N tunneling erase operation as a single transistor structure. We fabricated a 4-Mbit MONOS memory test chip using 0.25-/spl mu/m technology. The gate length of the memory cell was shrunk to 0.18 /spl mu/m. The distribution of threshold voltage for many operations were evaluated. The range of threshold voltage distribution is small, within 0.5 V in 12-14 V for programming and -8.5 to -9 V for erasing. It was also narrow for program/erase cycles up to 10/sup 4/ and after exposure to temperatures of 300/spl deg/C for 17 h and 150/spl deg/C for 304 h. These characteristics of narrow Vth distribution represent advantages of the MONOS memory device both for nonverify operation in program/erase mode and for low supply voltage operation in read mode. Another advantage is that no anomalous leak cell or tail bit is evident in the data retention result, demonstrating high reliability. The MONOS memory device is a promising candidate for use in cheaper and more scalable gate length fabrication processes compared with floating gate for highly reliable embedded applications.

Data Retention Improvement of Metal-Oxide-Nitride-Oxide-Semiconductor Memories Using Silicon-Tetrachloride-Based Silicon Nitride with Ultralow Si-H Bond Density

We have improved the data retention of metal-oxide-nitride-oxide-semiconductor (MONOS) memories by reducing the Si-H bond density in silicon nitride. This marked improvement was achieved by depositing silicon nitride with NH3 and SiCl4 (silicon tetrachloride, STC), instead of with NH3 and the conventionally used SiCl2H2 (dichlorosilane, DCS). The Si-H bond density of the STC-based nitride was less than 1% that of the DCS-based nitride. We clarified that the improvement was due to the suppression of the leakage of trapped electrons through shallow traps which are related to Si-H bonds with an activation energy of 0.1–0.2 eV.

A 2-bit MONOS nonvolatile memory cell based on asymmetric double gate MOSFET structure

A novel 2-bit/cell nonvolatile memory (NVM) with metal-oxide-nitride-oxide-semiconductor (MONOS) asymmetric double gate (ADG) MOSFET structure is proposed. With the double gate structure, the two conducting channels provide the ability to store 2 bits in a cell. Program and erase can be performed by channel hot electron (CHE) injection and Fowler-Nordheim (FN) tunneling respectively. The read operation and the array structure of the proposed novel NVM are also studied and described in this paper.

A model of radiation effects in nitride–oxide films for power MOSFET applications

Total dose effects in composite nitride–oxide (NO) films with various nitride and oxide thicknesses are studied. Metal nitride oxide semiconductor (MNOS) devices with thicknesses in the range of power transistors have been irradiated with X-rays up to a total dose of 1 Mrad (SiO 2). A model is proposed to describe the observed flatband voltage shifts as a function of total dose in the range of electric fields where the charge yield in the dielectrics to a first order approximation is linearly proportional to the electric field. The modulation of electric field in the dielectrics due to charge accumulation at the NO interface is found to be the dominating factor in determining the flatband voltage shift. It is suggested that, for the process conditions examined here, n-channel MNOS devices with oxide thickness between 12 and 15 nm give minimal radiation-induced flatband voltage shifts.

Radiation-induced trapped charge in metal-nitride-oxide-semiconductor structure

The radiation-induced trapped charge in the insulation layer of metal-nitride-oxide-semiconductor (MNOS) structure has been investigated. The mechanism of charge trapping under irradiation is studied by the radiation-induced mid-gap voltage shift using a simple charge trap model. The depth profile of fixed charge in the insulator before irradiation was evaluated by the mid-gap voltage of MNOS structures with varying insulator thicknesses using slanted etching. The irradiation tests were carried out using a Co-60 gamma ray source up to 1 Mrad(Si) with a gate voltage of +6 or -6 V. The calculated results using the model can be fitted well to the experimental results, and we confirmed the model is very useful to discuss the radiation-induced trapped charge. By simulating the mid-gap voltage shift of MNOS structures, we considered the possibility of a radiation hardened device.

Electrical characterisation of MNOS devices on p-type 6H-SiC

Metal-nitride-oxide semiconductor (MNOS), metal-oxide semiconductor (MOS) and metal-nitride semiconductor (MNS) devices have been fabricated on p-type 6H-SiC substrates without epitaxial layers. They have been characterised using high frequency capacitance-voltage (CV), conductance-voltage (GV) and current-voltage (IV) measurements. High frequency CV characteristics of SiC MNOS structures exhibit a capacitance-voltage behaviour that is very similar to high frequency CV characteristics of SiC MOS capacitors. Similar leakage current characteristics compared with p-type 6H-SiC MNS structures have been found for p-type 6H-SiC MNOS devices, but the SiO2/Si3N4 insulator current is lower, particularly for positive electric fields.

Detection of plasma produced in the interaction between an Nd:YAG laser and a metal-nitride-oxide-semiconductor-type charge-coupled device

In this paper, the interaction process of a high-power Q-switched YAG laser and a metal–nitride–oxide–semiconductor (MNOS)-type charge-coupled device (CCD) is studied with the help of the plasma shape and structure under the repeated actions of laser pulses. Mach–Zehnder interferograms of plasmas and related experimental results produced by a 1064 nm laser beam with a pulse width of 15 ns acting upon the MNOS-type CCD are obtained. © 1997 John Wiley & Sons, Inc. Microwave Opt Technol Lett 16: 160–162, 1997.

Scanning Force Microscopy on Laser Ablated Silicon Nitride Films

Silicon nitride insulators are gaining increased interest and are being widely used for passivation, annealing masks and as a dielectric in metal—nitride--oxidesemiconductor (MNOS) structures for non-volatile memories. Silicon nitride films can be prepared by reactive plasma deposition (RPD), plasma-enhanced chemical vapour deposition (PECVD) or by low pressure chemical vapour deposition (LPCVD). Recently, new laser-based methods have been developed, such as: pulsed laser deposition (PLD), laser chemical vapour deposition (LCVD) and laser direct synthesis (LDS). For the present study, silicon nitride films were deposited by the laser reactive ablation (LRA) method. The laser reactive ablation method is derived from the pulsed laser deposition technique. PLD is used to deposit stoichiometric thin films of alloys or compounds by ablating already-prepared solid targets. Unlike PLD, in LRA, ablation occurs in a reactive gas atmosphere [1]. Thus, a solid target consisting of the material to be reacted is ablated in a reactive gas atmosphere. The resulting material is collected on a substrate placed at a given distance from the target [2]. Laser reactive ablation (LRA) is a new method, which combines (in one step) the synthesis of the compound and the deposition. The LRA method is

Development of Sub-Quarter-µm MONOS (metal/oxide/nitride/oxide/semiconductor) Type Memory Transistor

A MONOS (metal/oxide/nitride/oxide/semiconductor) type nonvolatile memory transistor with a gate length of 0.23 µm has been developed. This memory transistor offers high endurance, low programming voltage and a narrow distribution of programmed threshold voltages. By introducing a rapid thermal nitridation (RTN) step into the fabrication prosecc of the ONO (oxide/nitride/oxide) layer, an enhancement in erase speed of one order of magnitude is achieved. The RTN also improves the oxidation resistance of the nitride layer, so that scaling down the thickness of the ONO film in order to reduce the programming voltage is feasible.

Charge separation in an electron cyclotron resonance plasma

Separation of an electron cyclotron resonance (ECR) plasma flux into an ion flux and an electron flux during plasma extraction has been investigated. The phenomenon is explained by the difference between ion current distribution and electron current distribution in the ECR plasma. When magnetic force lines cross the direction of the electron flux at a larger angle, the charged particle flux separation is enhanced. Also, evaluation of the flux diffusion equation for a magnetoplasma indicates that the diffusion coefficient of the electron flux across the force lines is much smaller than that of the ion flux. The ion flux diffuses isotropically compared to the electron flux confined by the magnetic field, resulting in charged particle flux separation. The potential distribution within a wafer exposed to the ECR plasma was evaluated by the flat band voltage (Vfb) shifts in metal–nitride–oxide semiconductor capacitors. The separation of the charged particle flux causes a nonuniform potential distribution within the wafer.

Improvement of hot-carrier and radiation hardnesses in metal-oxide-nitride-oxide semiconductor devices by irradiation-then-anneal treatments

The hardnesses of hot-carrier and radiation of metal-oxide nitride-oxide semiconductor (MONOS) devices can be improved by the irradiation-then-anneal (ITA) treatments. Each treatment includes an irradiation of Co-60 with a total dose of 1M rads(SiO/sub 2/) and an anneal in N/sub 2/ at 400/spl deg/C for 10 min successively. This improvement can be explained by the release of SiO/sub 2//Si interfacial strain. >

A novel MONOS nonvolatile memory device ensuring 10-year data retention after 10/sup 7/ erase/write cycles

A highly reliable nonvolatile memory device suitable for high-density electrically erasable and programmable read only memories (EEPROMs) is described. A metal-oxide-nitride-oxide-semiconductor (MONOS) structure whose top oxide is fabricated by chemical vapor deposition (CVD) on the nitride is proposed. This CVD oxide is densified by pyrogenic annealing and has stoichiometric SiO/sub 2/ characteristics. Its potential barrier, which prevents stored charges from decaying through the top oxide to the gate, thus becomes sharper than that of the thermally grown top oxide used in the conventional MONOS structure. For comparison between the proposed MONOS, conventional MONOS, and MNOS structures, three devices were fabricated on the same process line. The 16.7-nm nitride thickness in combination with a top oxide thickness of 4.0 nm results in a gate capacitance equivalent to that of the conventional NMOS structure with a 23.5-nm nitride thickness. Moreover, an asymmetric erase/write programming voltage has been adapted to the MONOS device operation by considering both erased-state degradation and written-state retention. At 85 degrees C, the proposed MONOS device has 10/sup 7/-cycle endurance with 10-year data retention. >

Characterization of the spatial distribution of traps in Si 3N 4 by field-assisted discharge of metal-nitride-oxide-semiconductor devices

The spatial distribution of electron traps in silicon nitride is determined by modelling the discharge of electrons out of nitride traps in metal-nitride-oxide-semiconductor (MNOS) structures subjected to low positive gate voltages. We assume a uniform density of capture centres in the nitride bulk and a high level of near-interface traps, which are modelled according to an exponentially decreasing distribution. By comparing the experimental data on field-assisted discharge of MNOS devices with the results derived from the proposed model, the bulk trap density has been found to be more than one order of magnitude lower than the interface trap density. We point out the strong influence of the interface traps on the memory action of MNOS devices and we discuss the reasons leading to such an excess of electron capture centres in the SiO 2-Si 3N 4 boundary. The distribution of traps obtained provides a good description of the discharge process, thus supporting the validity of the proposed method as a new approach for the characterization of MNOS devices.

Carrier transport and storage in Si 3N 4 for metal-nitride-oxide-semiconductor memory applications

The carrier transport and storage properties in the nitride of metal-nitride-oxide-semiconductor (MNOS) capacitors have been studied by combining repeated voltage ramp stress and constant voltage stress measurements. From the positive flat band voltage shift that results after bias application to the samples, it is clear that electrons dominate in the transport current and trapping. However, it is shown that, whereas at intermediate and low fields electrons are the single species involved in the capture-emission processes in the nitride, at higher electric fields a certain mechanism responsible for positive charge accumulation in the oxide-nitride interface region is also evident. By fitting theoretical results describing electron trapping in the nitride to the experimental flat band voltage shift dependence on bias, the density of electron traps in the nitride and the trapping efficiency have been estimated to be 3.7 × 10 18 cm −3 and 10 −2s cm 2 respectively. We have also compared the experimental flat band voltage shift dependence on current obtained in constant current stressed MNOS capacitors with theoretical values derived from the fitted parameters. Quite good agreement has been found (except at low stress levels where leakage currents through the parallel resistance of the current source become significant), thus supporting the validity of the proposed model.

Analysis, measurement, and simulation of dynamic write inhibit in an nvSRAM cell

Dynamic write inhibit (DWI) is a method of selectively inhibiting the programming (writing) of nonvolatile semiconductor memory cells. Its primary use is in silicon nitride oxide semiconductor (SNOS) and metal nitride oxide semiconductor (MNOS) memories, although it may be generalized to other nonvolatile technologies. This technique is based on a mechanism generally known as deep-depletion channel shielding (DDCS). A characterization of this phenomenon from the vantage points of analytic, experimental, and numerical simulations is presented. In addition, a brief review of the literature and the introduction of a novel memory cell used in a 64K nonvolatile static random access memory (nvSRAM) demonstrate the need for this better physical understanding.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The Combined Effect of Hydrogen and Oxygen Impurities in the Silicon Nitride Film of MNOS Devices

The combined effect of varying the hydrogen and oxygen impurities in the silicon nitride film of metal‐nitride‐oxide‐semiconductor (MNOS) devices was studied to develop a correlation among the chemical composition, current conduction, charge trapping, and memory properties of the devices. The atomic percentage of hydrogen increased in the film as a function of decreasing deposition temperature from 850 to 650°C. Oxygen was incorporated into the film by replacing nitrogen atoms through the use of nitrous oxide gas during the film deposition process. The addition of oxygen further reduced the hydrogen concentration in the film. The trapped electron and hole densities decreased by 25 and 66%, respectively, with a corresponding decrease in film conductivity as hydrogen and oxygen concentration in the silicon nitride film increased by 4 and 12%, respectiyely. The incorporation of hydrogen and oxygen improved the overall average device retention and endurance characteristics by 40% and from 107 to 108 cycles, respectively. The hydrogen and oxygen impurities may passivate the silicon dangling bonds associated with shallow traps within the bandgap of silicon nitride and, thus, allow the carriers to become trapped in deep traps, yielding enhanced memory properties in the MNOS devices.

Electron injection characteristics of MNOS nonvolatile semiconductor memory structure using the reverse breakdown of the PN junction

AbstractIn this paper, we describe an improved carrier injection method for the metal nitride‐oxide semiconductor (MNOS) structure, which is a prospective nonvolatile semiconductor memory device. The investigation is based on the prediction that carrier injection should be improved by increasing the carrier density at the Si surface and by lowering the tunneling barrier height of the SiO2 and that these conditions should be realizable by using the current flow due to reverse breakdown of the pn junction near the channel region of the Si surface under the gate electrode.Experiments indicate that the flatband voltage shift in the presence of electron injection is large as a result of the reverse breakdown current of the pn junction. Electron injection was further improved by an additional lowering of the tunneling barrier height associated with the voltage drop across the resistance connected to the bias circuit of the pn junction. This voltage drop was produced by the current flow due to reverse breakdown of the pn junction.Faster, stronger carrier injection from the Si surface to the traps in the insulator of MNOS structure can be realized by optimizing the doping densities in p and n regions and optimizing the resistance connected to the pn biasing circuit. This method is useful for electrical erasable nonvolatile semiconductor memory (EEPROM) devices without voltage up‐converter circuits.