Metal-nitride-oxide-semiconductor Research Articles

TCAD simulation for capture/emission of carriers by traps in SiN: trap-assisted tunneling model extended for capture of carriers injected via Fowler–Nordheim tunneling

We propose the novel trap-assisted tunneling (TAT) model that incorporates the ability to calculate dissipation of the kinetic energy of carriers propagating in the conduction or valence band. The proposed model allows us to evaluate capture efficiency (or the capture cross section) of carriers injected into the SiN charge trap layer via Fowler–Nordheim tunneling. By applying our TAT model to large planar metal-oxide-nitride-oxide-semiconductor (MONOS) capacitors, experimental data showing that electron capture efficiency depends on the tunnel oxide thickness are physically interpreted. Furthermore, three-dimensional technology computer-aided design (TCAD) simulation using SiN trap parameters roughly extracted from planar MONOS data shows that the incremental step pulse programming characteristics calculated for the charge trap memory (CTM) prototype device are comparable with measured data. We have found that additional time to calculate SiN trap charges is less than only 5% of all remaining calculation time.

Anomalous Behavior of Lateral C–V Characteristic of an MNOS Transistor with an Embedded Local Charge in the Nitride Layer

The C–V characteristic of the lateral source–substrate junction in a metal–nitride–oxide–semiconductor transistor has been simulated. With a certain voltage across the junction that depends on the dopant concentration in the substrate, a local trapped charge embedded in the nitride layer causes an anomalous rise or fall of the junction capacitance. Such a capacitance variation is associated with charge carrier redistribution in the near-surface region of the substrate when the trapped charge is embedded. This feature of the C–V characteristic can be used to detect a local charge embedded in the insulating layer of a field-effect transistor.

The Effect of Tungsten Volume on Residual Stress and Cell Characteristics in MONOS

The effect of residual stress during the tungsten deposition process were investigated using metal-oxide-nitride-oxide-semiconductor (MONOS) devices. The variation of residual stress due to tungsten volume was measured under tensile and compressive stress conditions. Residual stress increased in proportion to the deposition volume. Stress influenced the Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface and caused deterioration of the electrical properties, which was experimentally observed during measurements of the interface trap densities and memory windows. We confirmed that residual stress led to degradation of the cell characteristics of MONOS devices, and the absolute value of stress significantly affected these issues regardless of the polarity. From our experiments results, we can predict the degradation of cell characteristics in memory devices, and confirm the need for appropriate stress control in manufacturing process.

The Effect of Mechanical Stress on Cell Characteristics in MONOS Structures

We investigated the impact of mechanical stress on the cell characteristics of metal–oxide–nitride–oxide–semiconductor (MONOS) structures through experimental observations based on a curvature method for residual stress extraction and an analysis of the interface state. Residual stress induced on a substrate was observed to change from compressive to tensile depending on the tungsten process conditions; a high interface trap density was extracted under a high compressive stress environment based on a silicon bonding model. These interface trap densities were suggested as being attributable to a critical factor weakening the leakage characteristics of the MONOS structure. Besides, interface traps interrupted electron tunneling due to unintended charge trapping at the interface, which deteriorated memory characteristics indicated by a reduction in trap density. These results experimentally supported the effects of mechanical stress on device characteristics and reliability, which could be a straightforward way toward understanding the impact of stress for improved future flash memory applications.

Theoretical study of the atomistic behavior of O vacancy complexes with N and H atoms in the SiO2 layer of a metal–oxide–nitride–oxide–semiconductor memory: Physical origin of the irreversible threshold voltage shift observed in metal–oxide–nitride–oxide–semiconductor memories

Metal–oxide–nitride–oxide–semiconductor (MONOS) memories are attracting considerable interest for use as next-generation three-dimensional (3D) NAND flash memories; however, these memories have a serious reliability issue, that is, the irreversible threshold voltage shift arising from the generation of interface states at the Si/SiO2 interface due to program/erase (P/E) cycling. The clarification of the origin of this shift is essential in order to enable us to design high-reliability MONOS devices in the future. We clarified from first-principles calculations that defects consisting of an O vacancy and two substituent N atoms, (NO)2VO, are generated in SiO2, and that these turn into positively charged NSi2H2+ defects by trapping protons when a negative gate bias is applied. Furthermore, we found that thermal treatment in H2 atmosphere prevents (NO)2VO defects from turning into NSi2H2+ defects. This work clearly shows that proton trapping by (NO)2VO defects in SiO2 is the cause of interface state generation, leading to irreversible threshold voltage shifts during P/E cycling.

Evaluation of Hole Trapping Characteristics in MONOS-Type Memories Using the Constant-Current Carrier Injection Method

The hole trapping characteristics of two conditions of silicon nitride films with only empty trap centers and with both trap centers filled by electrons and empty trap centers were investigated. In addition, the constant-current hole injection method was presented to count the number of holes injected to the silicon nitride film in MONOS (Metal-oxide-nitride-oxide-semiconductor)-type memory capacitors. After a large number of holes were injected to the silicon nitride film, the flat-band voltage in the MONOS memory capacitor with both trap centers filled by electrons and empty trap centers clearly coincided to that with only empty trap centers. This result indicates that almost all trapped electrons could not remain in trap centers and were eliminated from the silicon nitride film after a large number of holes were injected. The electrons trapped in the silicon nitride films in this study were unstable against holes.

Relaxation of the electric current in Si3N4: Experiment and numerical simulation

The relaxation of the electric current in a metal–nitride–oxide–semiconductor structure has been measured experimentally. The experiment has been compared with the calculation based on the two-band conduction model and the multiphonon mechanism of the ionization of traps. The upper estimate obtained for the recombination cross section from the comparison of the experiment with the calculation is found to be 5 × 10–13 cm2.

Evaluation of Hole Trapping Characteristics in MONOS-Type Memories Using the Constant Current Carrier Injection Method

MONOS (Metal-oxide-nitride-oxide-semiconductor)-type nonvolatile memory (NVM) with a silicon nitride charge trapping layer has attracted considerable attention as the data storage for communication and multimedia applications.1-5In this type of memory, electrons and holes captured by traps in the silicon nitride layer cause shifts in the threshold voltage of memory transistors. Recently, the amount of charge stored in memory transistors is reduced because of shrinking the memory cell size. It is necessary to understand the charge trapping mechanism to ensure sufficient charge storage even in the small size transistors of NVMs. It is considered that three kinds of traps (namely, empty traps, traps which captured electrons and traps which captured holes) exist in the nitride layer. In the present study, we investigated the hole trapping characteristics in the empty traps and the traps which captured electrons in the nitride layer. Memory capacitors with the blocking oxide-silicon nitride-tunnel oxide (17.2/30.4/2.4 nm) stacked films were fabricated on p-type (100) silicon substrates. A tunnel oxide film of 2.4 nm in thickness was formed by rapid thermal oxidation. A 30.4-nm-thick silicon nitride film was formed by LPCVD using of Si2Cl6 and NH3 gases at 600 °C. A 17.3-nm-thick blocking oxide film was grown at 400 °C by PECVD. Finally, an aluminum film was deposited to form the gate electrode. After the sample fabrication, all the memory capacitors were baked at 233 °C for a long period of time to emit electrons and holes trapped in the stacked films. The CV characteristics of the baked capacitors were measured to determine the flat-band voltage Vfb,0. To inject electrons from the silicon substrate into the nitride layer, the gate electrode was positively biased with visible light illumination. At the next step, negative voltages were applied to the gate electrode to inject holes from the silicon substrate into the nitride layer under a constant current density (Jg = -4.2 × 10-9 A/cm2). Two sets of experiments were performed on the samples. In the first experiment, the samples were subjected to hole injection following electron injection. (These samples called HI-EI.) In the second experiment, the samples were subjected to hole injection following the bake. (These sample called HI-BK.) The number of injected holes per unit area Finj was derived by combining Jg and hole injection time. After hole injection, the CV characteristics were again measured to obtain the flat-band voltage Vfb,h. In Fig.1, Vfb,h as a function of Finj for the HI-EI samples (▲) is shown. Vfb,h increased with increasing Finj, and then was saturated. Fig.1 also shows Vfb,h as a function of Finjfor the HI-BK samples (△). In Fig.2, we show the flat-band voltage shift ΔVfb,h as a function of Finj for the HI-EI samples (▲). Here, ΔVfb,h is defined as |Vfb,h-Vfb,0|. Fig. 2 also shows ΔVfb,h as a function of Finj for the HI-BK samples (△). At small Finj, ΔVfb,h for the HI-EI samples was almost equal to ΔVfb,h for the HI-BK samples. This suggests that the hole trapping speed of the HI-EI samples were identical to that of the HI-BK samples. Next, at large Finj in Fig.1, Vfb,h for the HI-EI samples was almost equal to Vfb,hfor the HI-BK samples. The amount of net positive charge for the HI-EI samples was identical to that of the HI-BK samples. On the other hand, in Fig. 2, ΔVfb,h for the HI-EI samples was greater than that for the HI-BK sample at larger Finj. In the HI-BK samples, the injected holes were captured by the empty traps (i). In the HI-EI samples, in addition to process (i), the injected holes were captured by the traps which were filled by electrons (ii), or electrons trapped in the nitride layer were emitted (iii). The presence of the process (ii) or (iii) would be responsible for the larger ΔVfb,h of the HI-EI samples. Acknowledgements We would like to express gratitude to S. Tanaka, K. Hukuyama and K. Ozaki for their valuable discussions. This work was partly supported by JSPS KAKENHI Grant Number 26420280.

Experimental Extraction of the Charge Centroid in SiCN-Based Charge Trapping Memories Using the Constant-Current Carrier Injection Method

Nitride-based charge trapping memories, such as the metal-oxide-nitride-oxide-semiconductor (MONOS) devices, have received considerable attention for next generation nonvolatile memory (NVM) applications.1-3,7,8 The threshold voltage shifts of memory transistors are induced by electrons and holes trapped in the silicon nitride charge trapping layers. The memory cell size in the MONOS-type devices is rapidly becoming smaller. The number of electrons and holes trapped in the charge trapping layer is reduced in such small memory cells. It is essential to achieve sufficient memory effects even in the small size transistors of NVMs. There are still some challenging issues regarding the performance and reliability for the MONOS-type memories. We have previously proposed the application of silicon carbonitride (SiCN) films to the charge trapping layers.4-6 The relative dielectric constant of the SiCN films is 4.8-4.9, which is lower than that of silicon nitride films (~7). It has been suggested that larger threshold voltage shifts can be achieved by using the low-k SiCN films in the charge trapping memories. In order to improve the device performance in the SiCN based-NVM devices, it is important to understand the carrier trapping mechanism in the programming and erasing operations. In the present study, we investigated the hole trapping characteristics in the SiCN charge trapping layer using the constant-current carrier injection method and extracted the charge centroid in the SiCN layer. Two types of stacked film were formed on p-type (100) silicon substrates: (a) blocking oxide-silicon nitride-tunnel oxide (17.2/30.4/2.4 nm) stacked films and (b) blocking oxide-SiCN-tunnel oxide (17.3/31.6/2.4 nm) stacked films. The SiCN film was grown at 400 °C using Si(CH3)4 and NH3 gases by PECVD. The silicon nitride film was deposited at 600 °C by LPCVD. An aluminum film was deposited to form the gate electrode. After the sample fabrication, all the memory capacitors were baked at 235 °C for a long period of time to emit electrons and holes trapped in the stacked films. The flat-band voltage Vfb was determined by analyzing the CV curve of the baked capacitors. At the next step, the gate electrode was negatively biased to inject holes from the silicon substrate into the charge trapping film under a constant current density (Jg = -4.2 × 10-9 A/cm2). The number of injected holes per unit area Finj was derived by combining Jg and carrier injection time. Again the CV characteristics were measured to estimate the flat-band voltage shift ΔVfb,h which is induced by the trapped holes in the charge trapping layer. The charge centroid xtctl was calculated from the injected charges per unit area Qinj and ΔVfb.h as the injected charges can be assumed to be fully captured. Figs. 1(a) and 1(b) show xtctl as a function of Finj in the silicon nitride and SiCN layers during the constant current hole injection. As shown in Fig. 1(a), xtctl was initially located around the middle of the silicon nitride layer at smaller Finj and shifted towards the blocking oxide-silicon nitride interface at larger Finj. On the other hand, xtctl in the SiCN layer was located near the blocking oxide-SiCN interface as compared to that of the silicon nitride layer, as shown in Fig. 1(b). As mentioned above, the dielectric constant of the SiCN films is low. Therefore, in the two types of stacked film, the electric field in the SiCN layer is higher than that of the silicon nitride layer when a fixed voltage is applied to the gate electrodes. It is suggested that holes injected into the SiCN layer were easily transported towards the blocking oxide-SiCN interface by Poole–Frenkel conduction because of the higher electric field in the SiCN layer. This would result in the charge centroid near the blocking oxide-SiCN interface. The constant-current carrier injection method is useful to evaluate the hole trapping characteristics in the stacked films of charge trapping memories. Acknowledgement We would like to express gratitude to S. Tanaka, K. Hukuyama and K. Ozaki for their valuable discussions. This work was partly supported by JSPS KAKENHI Grant Number 26420280.

Defect Generation Mechanism and Its Impact on Reliability Properties in MONOS Devices

Introduction Metal-oxide-nitride-oxide-semiconductor (MONOS) device attracts much attention owing to its potential as future nonvolatile memory devices. For the use of MONOS devices, it is important to understand accurately the mechanism of reliability degradation induced by electrical stress such as programming and erasing. In this paper, we discuss the defects-generation mechanisms by using evaluation technique that we developed. We also show how the defects generation influences to reliability properties of the MONOS devices. Interface-State Generation by Program/Erase Cycling Program/Erase (P/E) cycle stress generates defects in MONOS devices and degrades their performance and reliability. Since it has been recognized for the MONOS devices that the degradation is mainly due to interface-state generation, we examined the mechanism of interface-state generation in the MONOS devices under P/E stress by using a charge measurement technique we developed. The amount of interface states (ΔNit) is found to have a strong correlation with charges flowing during erasing, irrespective of pulse voltage, pulse width and number of P/E cycles. It is further demonstrated that the ΔNit increases as hole current dominates in erasing, suggesting that hole injection from Si substrate during erasing is the main cause for the ΔNit. Data Retention Degradation Caused by Stress Induced Hole Current Data retention measurements after P/E cycle stress were carried out with applying gate voltage to control the direction of electron leakage during retention. As a result, higher charge loss was observed when applying negative gate voltage during retention, indicating that P/E stress-induced leakage current (SILC) across the tunnel oxide layer degrades the data retention.To detect the SILC directly, we performed carrier separation I-V measurement for p-channel MONOS devices. The tail of electron detrapping current at low voltage (electron SILC) was, however, observed only for the MONOS with highly Si-rich SiN charge trapping layer. Thus, a mechanism other than the electron SILC must be involved in the data retention degradation for the MONOS devices. The carrier separation measurements further demonstrated that hole current injected into the MONOS devices is increased after P/E cycle stress, indicating the existence of “hole SILC”. The hole SILC is found to be determined by the ΔNit regardless of MONOS structure, suggesting that the hole SILC is attributable to the generated interface states. These results suggest a mechanism for the data retention degradation caused by P/E cycle stress: The P/E cycle stress damages tunnel oxide layer and generates the ΔNit. The hole SILC is injected via the ΔNit, degrading data retention through hole trapping and possible subsequent recombination with stored electrons. Impact of Interface-State Recovery on Reliability Properties It is well known, in the research field of MOS reliability, that accumulated holes attack Si-H bonds at the Si/SiO2 interface and induce negative bias temperature instability (NBTI). Since the ΔNit in the MONOS devices is generated by holes accumulated in Si substrate, it is speculated that physical origin of the ΔNit is similar to that in MOS devices, that is, Si-H bond dissociation. The Reaction-Diffusion (R-D) model, which explains well the NBTI mechanism, suggests that hydrogen released by the Si-H dissociation diffuses back to the interface and passivates the generated interface states after removal of electrical stress. It was observed for the MONOS devices that the ΔNit was found to be decreased after 200ºC 1h baking, demonstrating that the ΔNit is due to dissociation of Si-H bonds. Since the recovery accompanies the threshold voltage shift, suppression of the ΔNit is important for data retention property as well as for endurance property. Conclusions We have investigated the mechanisms for interface-state generation by P/E cycle stress, and demonstrated that holes injected from Si substrate is the main cause for the ΔNit. It is also found that the hole SILC is injected via the ΔNit, degrading data retention property through hole trapping and possible subsequent recombination with stored electrons. Since the physical origin of the ΔNit is Si-H bond breakage, a part of released hydrogen diffuses back to the interface and passivates the ΔNit, leading to the degradation of data retention property.

Re-Examination of Performance and Reliability Degradation in Metal–Oxide–Nitride–Oxide–Semiconductor Memory with Ultrathin SiN Charge Trap Layers

We demonstrated that the degradation of program characteristics in metal–oxide–nitride–oxide–semiconductor (MONOS) devices consisting of an ultrathin (∼2 nm) SiN charge trap layer is due to a decrease in the electron capture efficiency, instead of a reduction in the number of available trap sites. From the data retention properties with applied gate bias voltage, we clarified that charge loss through the tunnel layer during data retention becomes more significant with decreasing SiN thickness. These results indicate that to improve the performance and reliability of MONOS devices with an ultrathin SiN charge trap layer, measures must be taken to enhance the capture cross section of the traps and to inhibit carrier motion in the SiN layer simultaneously.

Re-Examination of Performance and Reliability Degradation in Metal–Oxide–Nitride–Oxide–Semiconductor Memory with Ultrathin SiN Charge Trap Layers

We demonstrated that the degradation of program characteristics in metal–oxide–nitride–oxide–semiconductor (MONOS) devices consisting of an ultrathin (∼2 nm) SiN charge trap layer is due to a decrease in the electron capture efficiency, instead of a reduction in the number of available trap sites. From the data retention properties with applied gate bias voltage, we clarified that charge loss through the tunnel layer during data retention becomes more significant with decreasing SiN thickness. These results indicate that to improve the performance and reliability of MONOS devices with an ultrathin SiN charge trap layer, measures must be taken to enhance the capture cross section of the traps and to inhibit carrier motion in the SiN layer simultaneously.

Engineering of Si-Rich Nitride Charge-Trapping Layer for Highly Reliable Metal–Oxide–Nitride–Oxide–Semiconductor Type NAND Flash Memory with Multi-Level Cell Operation

The relationship between chemical structure (N/Si ratio) or physical structure (bilayer or laminate structure) of Si-rich nitride charge-trapping layer for metal–oxide–nitride–oxide–semiconductor (MONOS) type NAND flash memory and its electrical characteristics (including program/erase Vth window, fresh cell data retention and data retention after program/erase cycling stress) are investigated in detail. A bilayer charge-trapping structure formed by two different composite Si-rich nitride films has been developed that can realize a sufficient program/erase window and excellent data retention characteristics for multi-level cell (MLC) operation.

(Invited) Efficient Guiding Principle of Highly Scalable MONOS-Type Memories

We study the atomistic behavior of O-related defects in metal-oxide-nitride-oxide-semiconductor (MONOS) type memories using first-principles calculations. We find that the O-related defects in SiN charge trap layers result in the local collapse of the layer, leading to serious memory degradation. Based on these results, we propose an efficient guiding principle for the fabrication of highly scalable MONOS-type memories; the interfacial O chemical potential should be controlled to prevent the formation of the O-related defects in the SiN layer. The realistic and skillful recipe along the guidelines is the insertion of a thin Si layer into the SiO2 layer near SiO2/SiN interface. This recipe is also applicable for future nano-scale devices, where the fabrication of sharp and high quality oxide interfaces is crucial.

Charge Trapping and Reliability Properties of MONOS Memory with High-k Blocking Layer

Carrier trapping and reliability characteristics during the cycling operation of metal-oxide-nitride-oxide-semiconductor (MONOS) devices with a high-k blocking layer (Al2O3) have been studied by measuring the injected charge during programming and erasing (P/E). The evaluated charge centroid during P/E indicates that the traps near the SiN/Al2O3 interface are filled at high electric field, while bulk traps in the SiN layer are also available at low electric field. The degradation of MONOS devices in cycling operation is found to be strongly correlated with injected charge during erasing. It is indispensable to suppress hole injection, as well as lowering the electric field to improve endurance of MONOS devices. The discussion of this paper also extends to the structure of the charge trapping layer to improve both cycling endurance and retention simultaneously. Finally, we report that a high-k blocking layer has significant impact on data readout and programming characteristics through its transient dielectric properties.

Atomistic Design of Guiding Principles for High Quality Metal–Oxide–Nitride–Oxide–Semiconductor Memories: First Principles Study of H and O Incorporation Effects for N Vacancies in SiN Charge Trap Layers

We theoretically investigate H- and O-incorporation effects on memory characteristics of N vacancies in the SiN layer of metal–oxide–nitride–oxide–semiconductor (MONOS) type memory. The present calculations show that N vacancy maintains high program/erase (P/E) cycle endurance characteristics, regardless of the existence of H and O atoms. It is also found that the incorporation of an H atom is energetically favorable for N vacancy, whereas the incorporation of such an atom is unfavorable for O-incorporated N vacancy. The present results indicate clearly that realistic process conditions, in which incorporation of H and O atoms is inevitable, do not affect memory characteristic of MONOS-type memory having N vacancies in the SiN layer, and, therefore, such a memory is desirable and feasible for future memories.

Direct Measurement of Back-Tunneling Current during Program/Erase Operation of Metal–Oxide–Nitride–Oxide–Semiconductor Memories and Its Dependence on Gate Work Function

In this study, we have established a novel scheme to extract the back-tunneling current from the transient characteristics of a metal–oxide–nitride–oxide–semiconductor (MONOS) memory capacitor during programming or erasing. Using a charge centroid extraction method, the separation of trapping current, leakage current and back-tunneling current was successfully accomplished. By studying the gate work function dependence of injected current, it was found that the leakage current due to electron injection from the Si substrate is the dominant component during deep programming and that the back-tunneling current due to electron injection from the gate electrode is the predominant component of injected current during deep erasing.

A New Method to Extract the Charge Centroid in the Program Operation of Metal–Oxide–Nitride–Oxide–Semiconductor Memories

We proposed and demonstrated a new method to extract the charge centroid of metal–oxide–nitride–oxide–semiconductor (MONOS) devices. Comparing with other existing methods for charge centroid evaluation, our new method has the advantage of simplicity and the compatibility with other test sequences of memory cell capacitors. Using our method, we investigated the dependence of charge centroid on the thickness of SiN layer. It is found that the charge centroid of the 14-nm-thick SiN MONOS is located around the middle of the SiN layer, while the 5-nm-thick SiN MONOS has the centroid at the SiN/Al2O3 interface. These results indicate that the available trap sites during program operation are dependent on the thickness of the SiN layer.

Dielectric-thickness dependence of damage induced by electron-beam irradiation on metal nitride oxide semiconductor gate pattern

We analyzed the electron-irradiation damage induced by electron-beam inspection of metal nitride oxide semiconductor (MNOS) capacitors with various gate-dielectric thicknesses. Damage induced in an MNOS capacitor with a SiON dielectric for high-performance CMOS devices was compared to that induced on a metal oxide semiconductor (MOS) capacitor. We found that there is no remarkable difference between the damage to MOS capacitors and that to metal nitride oxide semiconductor MNOS capacitors. Damage was induced when a high-energy electron beam, whose electron range was larger than the thickness of the gate electrode, was irradiated. The induced damage strongly depends on the thickness of the gate dielectric. When the beam was irradiated onto a capacitor with a gate-dielectric thickness of 10.0 nm the flatband voltage shifted. When the beam was scanned onto a capacitor with a gate-dielectric thickness of 4.0 nm, the flatband voltage shifted minimally. However, the leakage-current density increased to 10−7 A/cm2 at a gate voltage of 3.0 V. On the other hand, when the beam was scanned onto an MNOS capacitor with 2.5-nm-thick dielectric, not even the leakage current was increased. Accordingly, for damage-free inspection when a gate-dielectric thickness is 4.0 nm or more, the beam energy needs to be lower so that the electron range is shorter than the thickness of the gate electrode.

Effects of Nitridation on the Electrical Properties of MONOS Nonvolatile Memories

We investigated the mechanism that causes decreases in data erase and data retention times of metal-oxide-nitride-oxide-semiconductor (MONOS) nonvolatile memories when nitridation is applied to tunnel oxide film. Data erase and data retention times of MONOS nonvolatile memories decrease as nitrogen concentration in tunnel oxide film increases. Decreasing data erase times result from increasing hole current caused by lowering of the barrier height of the hole between the valence band of the tunnel oxide film and the silicon substrate. Lowering of barrier height is caused by nitridation of the tunnel oxide film. Decreases in data retention times of MONOS nonvolatile memories caused by nitridation of tunnel oxide film are due to increases in both electron current and hole current during data retention. Hole current increases as the temperature increases, but electron current does not change. Therefore, increases in electron current are due to increases in interface trap density between the silicon substrate and tunnel oxide film caused by nitridation. Increases in the hole current conducted through the tunnel oxide film caused by nitridation are due to the generation of hole traps in tunnel oxide film during nitridation. An activation energy of was obtained for the hole current conducted through the tunnel oxide film.