Metal Gate Electrode Research Articles

Bilayer metal gate electrodes with tunable work function: Adhesion and interface characterization

The dependence of Pt film thickness and forming gas annealing on the interface fracture properties and interface composition of Ti/Pt bilayer gate electrode films on a HfO2 gate dielectric are reported. These fracture properties and composition results are directly compared to work function tuning behavior witnessed in metal-oxide semiconductor (MOS) capacitors fabricated from the same films. The interface fracture energy of the metal bilayer/gate dielectric interface is strongly dependent on thickness after a forming gas anneal but shows no thickness dependence in the as-deposited case. The flat-band voltage increases abruptly and then remains constant as the thickness of the Pt film is increased in the as-deposited case but varies gradually with increasing Pt thickness after a forming gas anneal. Angle-resolved x-ray photoelectron spectroscopy characterization of the resulting fracture surfaces confirms that Ti diffusion to the metal bilayer/gate dielectric interface is responsible for these effects.

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

The impact of the titanium nitride (TiN) gate electrode thickness has been investigated in n- and p-channel SOI multiple gate field-effect transistors (MuGFETs) through low-frequency noise, charge pumping and static measurements as well as capacitance–voltage curves. The results suggest that a thicker TiN metal gate electrode gives rise to a higher EOT, a lower mobility and a higher interface trap density. The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TiN metal gate thickness and at higher V GF . In addition, it is demonstrated that post-deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TiN gate electrode thickness, where a continuous variation of EOT and an increase on the degradation of the interface quality are observed.

Damascene TiN–Gd 2O 3-gate stacks: Gentle fabrication and electrical properties

In this work, we present MOS capacitors and field effect transistors with a crystalline gadolinium oxide (Gd 2O 3) gate dielectric and metal gate electrode (titanium nitride) fabricated in a gentle damascene gate last process. Details of the gate last process and initial results on MOS devices with equivalent oxide thicknesses (EOT) of 3.0 nm and 1.5 nm, respectively, are shown.

Interface/Bulk Trap Recovery After Submelt Laser Anneal and the Impact to NBTI Reliability

In this letter, submelt laser anneal used to achieve ultrashallow junctions (USJs) in capped high- devices with TaN/TiN metal gate electrode is investigated. The submelt laser anneal results in USJ and sharp junction on both n- and pMOSFET devices. However, this process induces interface and bulk defects and reduces negative-bias temperature instability (NBTI) reliability additionally. It is shown that if the laser anneal is followed by a rapid thermal anneal, the laser-related damage decreases, and the NBTI robustness improves without altering the obtained junction sharpness.

Ion-Sensitive Properties of Organic Electrochemical Transistors

Ion-sensitive properties of organic electrochemical transistors (OECT) based on Poly(3,4-ethylenedioxythiophene): poly(styrene sulfonic acid) (PEDOT:PSS) have been systematically studied for the first time. It has been found that the transfer curve (I(DS)-V(G)) of an OECT shifts to lower gate voltage horizontally with the increase of the concentration of cations, including H(+), K(+), Na(+), Ca(2+), and Al(3+), in the electrolyte. The gate electrode of the OECT plays an important role on its ion-sensitive properties. For devices with Ag/AgCl gate electrode, Nernstian relationships between the shift of the gate voltage and the concentrations of the cations have been obtained. For devices with metal gate electrodes, including Pt and Au, the ion sensitivity is higher than that given by the Nernst equation, which can be attributed to the interface between the metal gate and the electrolyte.

A carrier-mobility model for high- k gate-dielectric Ge MOSFETs with metal gate electrode

A mobility model for high- k gate-dielectric Ge pMOSFET with metal gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high- k gate dielectric. The effects of structural and physical parameters (e.g. gate dielectric thickness, electron density, effective electron mass and permittivity of gate electrode) on the carrier mobility are investigated. The carrier mobility of Ge pMOSFET with metal gate electrode is compared to that with poly-Si gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si gate electrode is replaced by metal gate electrode. This is because metal gate electrode plays a significant role in screening the coupling between the optical phonons in the high- k gate dielectric and the charge carriers in the conduction channel.

Physical and chemical characterization of combinatorial metal gate electrode Ta–C–N library film

This paper reports comprehensive structural and chemical analyses for the combinatorial Ta–C–N/HfO2 system, crucial data for understanding the electrical properties of Ta–C–N/HfO2. Combinatorial Ta–C–N “library” (composition spread) films were deposited by magnetron sputtering. Electron probe wavelength dispersive spectroscopy and x-ray fluorescence-yield near-edge spectroscopy were used to quantitatively determine the composition across these films. Scanning x-ray microdiffractometry determined that a solid solution of Ta(C,N)x forms and extends to compositions (0.3≤Ta≤0.5 and 0.57≤Ta≤0.67) that were previously unknown. The thermal stability of the Ta–C–N/HfO2 library was studied using high resolution transmission electron microscopy, which shows Ta–C–N/HfO2/SiO2/Si exhibiting good thermal stability up to 950 °C.

Photoinduced charge-trapping phenomena in metal/high-k gate stack structures studied by synchrotron radiation photoemission spectroscopy

We have demonstrated photoinduced charge-trapping phenomena in metal/high-k gate stack structures using time-dependent photoemission spectroscopy with synchrotron radiation. Pt metal gate electrode with a large work function releases trapped negative charges near the surface of the HfSiON film while TiN metal gate electrode with a lower work function keeps negative charges in the HfSiON film. The release of negative trapped charges reveals a possibility of positive charge trapping at the interface in the HfSiON film. The location of energy level for negative charges is concluded to be between Pt and TiN Fermi-level in the band gap of the HfSiON film.

Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor

We have investigated the characteristics of silicon oxide films deposited by plasma-enhanced atomic layer deposition (PEALD) and plasma-enhanced chemical vapor deposition (PECVD) as offset spacer films of high-k/metal gate stacks. From the results of bonding structure analysis, the silicon oxide film deposited by PEALD has been found to be composed of a Si–O bond network of the stoichiometric silicon oxide film. On the other hand, the silicon oxide film deposited by PECVD is considered to contain suboxide bond structures. From the results of physical and mechanical evaluations, the silicon oxide film deposited by PEALD exhibits a lower wet etch rate, a higher film density, a lower dielectric constant, a smaller amount of water in the film, and a higher elastic modulus than that deposited by PECVD. PEALD showed excellent thickness controllability. From these results, the silicon oxide film deposited by PEALD has higher quality and is more suitable for use as an offset spacer than that deposited by PECVD. X-ray photoelectron spectroscopy showed that the surface oxidation of a titanium nitride film, which is used as a metal gate electrode, during PEALD can be suppressed by using a lower PEALD temperature. Finally, we have demonstrated that the drain current of a high-k/metal gate transistor with a silicon oxide offset spacer deposited by PEALD is markedly increased, compared with that with a high-temperature-deposited silicon oxide offset spacer.

Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High- $k$ Dielectrics

Achieving low p-channel metal-oxide-semiconductor (PMOS) threshold voltages with metal gates and high-k dielectrics is challenging with conventional gate-first complimentary metal-oxide-semiconductor process integration. This study, for the first time, explores the tradeoffs in using different combinations of thin-strained Si1 - x Gex channels, boron counterdopings, Si capping layers, and different metal-gate electrodes to obtain low PMOS threshold voltages with metal gate on high-k dielectrics in a gate-first integration technology. Device simulations are used to explain the experimental threshold voltage trends with varying Si1 - x Gex thicknesses, boron counterdopings, and gate work functions.

Investigation of Thermal Stability of TiN Film Formed by Atomic Layer Deposition Using Tetrakis(dimethylamino)titanium Precursor for Metal-Gate Metal–Oxide–Semiconductor Field-Effect Transistor

In this paper, we describe the superiority of the titanium nitride (TiN) film formed by atomic layer deposition (ALD) using a tetrakis(dimethylamino)titanium (TDMAT) precursor for metal-gate electrodes of planar metal–oxide–semiconductor field-effect transistors (MOSFETs). It was demonstrated that the resistivity of the ALD TiN was significantly reduced by NH3 post deposition annealing (PDA). The electrical characteristics of the ALD-TiN-gate MOS capacitors and planar MOSFETs were evaluated and compared with those of the physical-vapor-deposited (PVD) TiN. The performance of the ALD-TiN-gate cases was confirmed to be superior to that of the PVD-TiN-gate cases, which was explained by the lower interface trap density (Dit) of the ALD TiN/SiO2 gate stack.

Bilayer metal gate electrodes with tunable work function: Mechanism and proposed model

A bilayer metal structure has been demonstrated to adjust the gate work function over the Si band gap. The underlying tuning mechanism is believed to be due to metal interdiffusion based on comparison of work function behavior under different anneal conditions. In this paper, we conduct physical characterization on bilayer metal gates and successfully verify that the interdiffusion is the cause of the work function tuning. Furthermore, we find that metal interdiffusion significantly slows down after an initial anneal, resulting in a stable work function. A diffusion model involving the annealing out of fast diffusion paths is proposed to explain the work function results.

Oxygen migration in TiO2-based higher-k gate stacks

We report on the stability of high-permittivity (high-k) TiO2 films incorporated in metal-oxide-silicon capacitor structures with a TiN metal gate electrode, focusing on oxygen migration. Titanium oxide films are deposited by either Ti sputtering [physical vapor deposition (PVD)] followed by radical shower oxidation or by plasma-enhanced atomic layer deposition (PEALD) from titanium isopropoxide (Ti{OCH(CH3)2}4) and O2 plasma. Both PVD and PEALD films result in near-stoichiometric TiO2 prior to high-temperature annealing. We find that dopant activation anneals of TiO2-containing gate stacks at 1000 °C cause 5 Å or more of additional SiO2 to be formed at the gate-dielectric/Si-channel interface. Furthermore, we demonstrate for the first time that oxygen released from TiO2 diffuses through the TiN gate electrode and oxidizes the poly-Si contact. The thickness of this upper SiO2 layer continues to increase with increasing TiO2 thickness, while the thickness of the regrown SiO2 at the gate-dielectric/Si interface saturates. The upper SiO2 layer degrades gate stack capacitance, and simultaneously the oxygen-deficient TiOx becomes a poor insulator. In an attempt to mitigate O loss from the TiO2, top and bottom Al2O3 layers are added to the TiO2 gate dielectric as oxygen barriers. However, they are found to be ineffective, due to Al2O3-TiO2 interdiffusion during activation annealing. Bottom HfO2/Si3N4 interlayers are found to serve as more effective oxygen barriers, reducing, though not preventing, oxygen downdiffusion.

Voltage-controlled group velocity of edge magnetoplasmon in the quantum Hall regime

We investigate the group velocity of edge magnetoplasmons (EMPs) in the quantum Hall regime by means of time-of-flight measurement. The EMPs are injected from an Ohmic contact by applying a voltage pulse, and detected at a quantum point contact by applying another voltage pulse to its gate. We find that the group velocity of the EMPs traveling along the edge channel defined by a metallic gate electrode strongly depends on the voltage applied to the gate. The observed variation of the velocity can be understood to reflect the degree of screening caused by the metallic gate, which damps the in-plane electric field and hence reduces the velocity. The degree of screening can be controlled by changing the distance between the gate and the edge channel with the gate voltage.

Tunable electrical superlattices in periodically gated bilayer graphene

The paper demonstrates that a single flake of bilayer graphene patterned with a periodic array of metallic gate electrodes behaves like a programmable superlattice formed by heterostructures of type I, II, or III, depending on the dc gate voltage values. The engineering of the width and position of the band gap in each region is performed only by tuning the dc voltages applied on the gate electrodes. Such a single programmable superlattice on bilayer graphene could replace the existing superlattices that require different semiconductor materials for each heterostructure type.

TEM analysis of Ge-on-Si MOSFET structures with HfO2 dielectric for high performance PMOS device technology

In this paper, we present a (scanning) transmission electron microscopy analysis of novel Ge-on-Si MOSFETs which incorporate a high-k HfO2 dielectric and TaN/TiN metal gate electrodes. A key feature of these devices is the incorporation of a very thin (~1nm) Si passivation layer on top of the Ge virtual substrate, which is partially oxided to form SiO2 (~0.5nm), before depositing the HfO2 dielectric and TaN and TiN metal gate electrodes. Our results confirm the architecture of the device structures and the existence of Si passivation.

Advanced high-k/metal gate stack progress and challenges – a materials and process integration perspective

Abstract Scaling of complementary metal oxide semiconductor devices is critical to enhancing performance and reducing the production cost of transistors. Conventional gate stack film systems consisting of a SiO2 dielectric layer between the Si substrate channel and a doped polycrystalline silicon (poly-Si) gate electrode exhibited excessively high gate current leakage when the physical thickness of this traditional dielectric was scaled to Tphys = ∼2 nm. The rate of scaling was initially preserved by incorporating nitrogen to form an SiOxNy insulator layer; however, this material soon experienced unacceptable levels of direct tunneling leakage current, which launched an industry-wide investigation of potential high dielectric constant (high-k) metal oxides as replacement materials for the SiO2 based gate dielectric layer. Thermal stability requirements for the introduction of high-k dielectric materials necessitated the simultaneous replacement of poly-Si with a metal gate electrode due to several performance factors including unscalable threshold voltage. Although high-k/metal gate thermal stability has been demonstrated, significant challenges remain to be resolved for future technology nodes. This paper reviews the progress and challenges associated with the introduction of high-k/metal gate transistors, including threshold voltage tuning and gate dielectric thickness scaling, from a materials and process integration perspective.

Fabrication of advanced La-incorporated Hf-silicate gate dielectrics using physical-vapor-deposition-based in situ method and its effective work function modulation of metal/high-k stacks

Lanthanum (La) incorporation into Hf-silicate high-permittivity (high-k) gate dielectrics was conducted using a physical-vapor-deposition (PVD)-based in situ method. PVD-grown metal Hf, La, and Hf–La alloys on base SiO2 oxides received in situ annealing to form high-quality HfLaSiO dielectrics, and subsequent deposition of metal gate electrodes was carried out to fabricate advanced metal/high-k gate stacks without breaking vacuum. The in situ method was found to precisely control La content and its depth profile and to tune the effective work function of metal/high-k stacks. Remarkable leakage current reduction of almost seven orders of magnitude compared with conventional poly-Si/SiO2 stacks and excellent interface properties comparable to an ideal SiO2/Si interface were also achieved at an equivalent oxide thickness of around 1.0 nm. Our x-ray photoelectron spectroscopy analysis revealed that, as previously suggested, effective work function modulation due to La incorporation is attributed to the interface dipole (or localized sheet charge) at the bottom high-k/SiO2 interface, which is crucially dependent on the La content at the interface. Moreover, it was found that high-temperature annealing causing interface oxide growth leads to redistribution of La atoms and forms the uppermost La-silicate layer at the metal/high-k interface by releasing the dipole moment at the bottom high-k/SiO2 interface. Based on these physical and electrical characterizations, the advantages and process guidelines for La-incorporated dielectrics were discussed in detail.

High density plasma etching of titanium nitride metal gate electrodes for fully depleted silicon-on-insulator subthreshold transistor integration

Etching of TiN metal gate materials as a part of an integrated flow to fabricate fully depleted silicon-on-insulator ultralow-power transistors is reported. TiN etching is characterized as a function of source power, bias power, gas composition, and substrate temperature in a high density inductively coupled plasma reactor. Under the conditions used in this work, the TiN etch rate appears to be ion flux limited and exhibits a low ion enhanced etching activation energy of 0.033eV. Notching of the polysilicon layer above the TiN may occur during the polysilicon overetch step as well as the TiN overetch step. Notching is not significantly affected by charging of the underlying gate dielectric under the conditions used. By optimizing the plasma etch process conditions, TiN:SiO2 selectivity of nearly 1000:1 is achieved, and a two-step TiN main etch and TiN overetch process yields well-defined metal gate structures without severe gate profile artifacts.

Interface Engineering of a Metal/ High-k/ Semiconductor Layered Structure by Water Vapor Discharge

The suppression of interfacial reactions in a tungsten (W)/hafnia (HfO2)/germanium (Ge) structure by water (H2O) vapor discharge was demonstrated. In the case of a HfO2/Ge dioxide (GeO2)/Ge structure, it was confirmed that the thickness of the interfacial GeO2 layer was decreased by H2O vapor discharge. Moreover, in the case of a W/hafnium (Hf)/Ge structure, it was found that such discharge can also achieve the formation of a W/HfO2/Ge structure with abrupt interfaces, without the oxidation of W or Ge. These results suggest that the selective removal of interfacial reaction layers and residual oxygen atoms in metal gate electrodes by hydrogen (H) radicals and the selective repair of oxygen-deficient high-dielectric-constant (high-k) insulators by hydroxyl (OH) and oxygen (O) radicals occur simultaneously during H2O vapor discharge. This means that thermodynamically selective etching and oxidation conditions can be realized using only H2O discharge.