Memristive Memory Research Articles

Fault tolerant adaptive write schemes for improving endurance and reliability of memristor memories

The non-deterministic nature of memristor and its unreliable behavior are the two major concerns hampering its growth and industrial manufacturability. The endurance and reliability of memristor memories are affected not only by the process variations (intrinsic), but also due to the electrical stress created by interfacing peripheral circuits (extrinsic). Concerning the intrinsic faults in transition metal oxide (TMO) memristors, drifting of oxygen vacancies across the device is responsible for SET/RESET operation. It is likely that such drifting might induce switching faults during the device operation, for instance endurance of the memory. Thus, the application of a fixed write pulse may not suffice to achieve successful write operations under these circumstances. To circumvent the above pitfall, we propose here a new technique by designing a fault tolerant adaptable write scheme which can adapt by itself based on the behavior and switching faults. Accordingly, the proposed write scheme identifies the optimal amplitude and the width for write pulse. The proposed write scheme under various memristor faults is found to enhancing the reliability of memristors efficiently. Further, the results are validated by means of Monte-Carlo analysis by infusing the random variations of internal parameters of memristors as well.

Stability analysis of memristive multidirectional associative memory neural networks and applications in information storage

Traditional biological neural networks lack the capability of reflecting variable synaptic weights when simulating associative memory of human brains. In this paper, we investigate the existence and exponential stability of a novel memristive multidirectional associative memory neural networks (MAMNNs) model, which includes the time-varying delays. In the proposed approach, the time-varying delays are set to be bounded, and it is not necessary for their derivative to be differentiable. With removal of certain conditions, less conservative results are generated. Sufficient criteria guaranteeing the stability of the memristive MAMNNs are derived based on the Lyapunov function and some inequality techniques. To illustrate the performance of the proposed criteria, a procedure is designed to realize information storage. Meanwhile, the effectiveness of the proposed theories is validated with numerical experiments.

Finite-time anti-synchronization of memristive stochastic BAM neural networks with probabilistic time-varying delays

This paper investigates the drive-response finite-time anti-synchronization for memristive bidirectional associative memory neural networks (MBAMNNs). Firstly, a class of MBAMNNs with mixed probabilistic time-varying delays and stochastic perturbations is first formulated and analyzed in this paper. Secondly, an nonlinear control law is constructed and utilized to guarantee drive-response finite-time anti-synchronization of the neural networks. Thirdly, by employing some inequality technique and constructing an appropriate Lyapunov function, some anti-synchronization criteria are derived. Finally, a number simulation is provided to demonstrate the effectiveness of the proposed mechanism.

A memristive plasticity model of voltage-based STDP suitable for recurrent bidirectional neural networks in the hippocampus

Memristive systems have gained considerable attention in the field of neuromorphic engineering, because they allow the emulation of synaptic functionality in solid state nano-physical systems. In this study, we show that memristive behavior provides a broad working framework for the phenomenological modelling of cellular synaptic mechanisms. In particular, we seek to understand how close a memristive system can account for the biological realism. The basic characteristics of memristive systems, i.e. voltage and memory behavior, are used to derive a voltage-based plasticity rule. We show that this model is suitable to account for a variety of electrophysiology plasticity data. Furthermore, we incorporate the plasticity model into an all-to-all connecting network scheme. Motivated by the auto-associative CA3 network of the hippocampus, we show that the implemented network allows the discrimination and processing of mnemonic pattern information, i.e. the formation of functional bidirectional connections resulting in the formation of local receptive fields. Since the presented plasticity model can be applied to real memristive devices as well, the presented theoretical framework can support both, the design of appropriate memristive devices for neuromorphic computing and the development of complex neuromorphic networks, which account for the specific advantage of memristive devices.

Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition

Hierarchical temporal memory (HTM) is a machine learning algorithm inspired by the information processing mechanisms of the human neocortex and consists of a spatial pooler (SP) and temporal memory (TM). In this paper, we develop circuits and systems to achieve the optimized design of an HTM SP, an HTM TM, and a memristive analog pattern matcher for pattern recognition applications. The HTM SP realizes an optimized hardware design through the introduction of mean overlap calculations and by replacing the threshold determination in the inhibition stage with a weighted summation operator over the neighborhood of the pixel under consideration. HTM TM is based on discrete analog memristive memory arrays and a weight update procedure. The operation of the proposed system is demonstrated for a face recognition problem, using the standard AR, ORL, and Yale databases, and for speech recognition, using the TIMIT database, with achieved accuracies of 87.21% and approximately 90%, respectively, given an SNR of 10 dB. Visual data processing using binary HTM SP features requires less storage and processing memory than required by the traditional processing methods, with the area and power requirements for its implementation being 0.096 mm2 and 1756 mW, respectively. The design of the TM circuit for a single pixel requires 23.85 ${\mu}\text{m}^{2}$ of area and 442.26 ${\mu}\text{W}$ of power.

Fault Modeling and Parallel Testing for 1T1M Memory Array

Memristor memory is a novel electrical device, which has attracted more and more attentions as a new nonvolatile memory due to its fast write/read speed, low operation voltage, long data retention time, and excellent scalability. The gateless 1 memristor (1M) crossbar memristor structure has the highest density but suffers from the sneak-path problem. One transistor and one memristor (1T1M) structure can eliminate the effect of sneak-path currents. However, leakage currents exist in the 1T1M memory array through the off transistors, which will affect the write and read operations. The wire resistance which is inevitable in the memristor circuits is another fatal factor that affects the write and read operations. In this paper, we analyze the effect of the leakage currents and wire resistance during the write and read operations based on 1T1M memory array under different array sizes. Memristor can be employed as either logic gate or memory element. Stateful logic operations can be performed through memristors and resistors with the help of appropriate circuit. In this paper, a parallel testing method was proposed based on memristive stateful logic which can improve the test efficiency compared to the traditional March algorithm. The proposed parallel testing method is 1.242 times faster than the March algorithm when the array size is 64 * 64, and when the array size increased to 1024 * 1024, the parallel testing is 1.249 times faster than the March algorithm while the test time can be reduced by 19.51% and 19.92%, respectively.

Exponential lag function projective synchronization of memristor-based multidirectional associative memory neural networks via hybrid control

This paper is concerned with the exponential lag function projective synchronization of memristive multidirectional associative memory neural networks (MMAMNNs). First, we propose a new model of MMAMNNs with mixed time-varying delays. In the proposed approach, the mixed delays include time-varying discrete delays and distributed time delays. Second, we design two kinds of hybrid controllers. Traditional control methods lack the capability of reflecting variable synaptic weights. In this paper, the controllers are carefully designed to confirm the process of different types of synchronization in the MMAMNNs. Third, sufficient criteria guaranteeing the synchronization of system are derived based on the derive-response concept. Finally, the effectiveness of the proposed mechanism is validated with numerical experiments.

On-chip face recognition system design with memristive Hierarchical Temporal Memory

Hierarchical Temporal Memory is a new machine learning algorithm intended to mimic the working principle of neocortex, part of the human brain, which is responsible for learning, classification, and making predictions. Although many works illustrate its effectiveness as a software algorithm, hardware design for HTM remains an open research problem. Hence, this work proposes an architecture for HTM Spatial Pooler and Temporal Memory with learning mechanism, which creates a single image for each class based on important and unimportant features of all images in the training set. In turn, the reduction in the number of templates within database reduces the memory requirements and increases the processing speed. Moreover, face recognition analysis indicates that for a large number of training images, the proposed design provides higher accuracy results (83.5\%) compared to only Spatial Pooler design presented in the previous works.

Neuron inspired data encoding memristive multi-level memory cell

Mapping neuro-inspired algorithms to sensor backplanes of on-chip hardware require shifting the signal processing from digital to the analog domain, demanding memory technologies beyond conventional CMOS binary storage units. Using memristors for building analog data storage is one of the promising approaches amongst emerging non-volatile memory technologies. Recently, a memristive multi-level memory cell for storing discrete analog values has been developed in which memory system is implemented combining memristors in voltage divider configuration. In given example, the memory cell of 3 sub-cells with a memristor in each was programmed to store ternary bits which overall achieved 10 and 27 discrete voltage levels. However, for further use of proposed memory cell in analog signal processing circuits data encoder is required to generate control voltages for programming memristors to store discrete analog values. In this paper, we present the design and performance analysis of data encoder that generates write pattern signals for 10 level memristive memory.

Implementation of digital equality comparator circuit on memristive memory crossbar array using material implication logic

One of the most significant constraints of Von Neumann architecture is the limited bandwidth between memory and processor. The cost to move data back and forth between memory and processor is considerably higher than the computation in the processor itself. This architecture significantly impacts the Big Data and data-intensive application such as DNA analysis comparison which spend most of the processing time to move data. Recently, the in-memory processing concept was proposed, which is based on the capability to perform the logic operation on the physical memory structure using a crossbar topology and non-volatile resistive-switching memristor technology. This paper proposes a scheme to map digital equality comparator circuit on memristive memory crossbar array. The 2-bit, 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit of equality comparator circuit are mapped on memristive memory crossbar array by using material implication logic in a sequential and parallel method. The simulation results show that, for the 64-bit word size, the parallel mapping exhibits 2.8× better performance in total execution time than sequential mapping but has a trade-off in terms of energy consumption and area utilization. Meanwhile, the total crossbar area can be reduced by 1.2× for sequential mapping and 1.5× for parallel mapping both by using the overlapping technique.

Origin of a continuously enlarge memristor effect in Nb inserted into MgB2 multilayer constructed heterojunctions

In this work, a resistive switching memory device, in which niobium (Nb) inserted into magnesium diboride (MgB2) multilayer constructed heterojunctions, was prepared by vacuum sputtering at 400 °C. Furthermore, a continuously enlarge memristor memory effect was observed in Ti/(MgB2/Nb)n/MgB2/Ti (n = 0, 1, 2, 3) devices with the increasing of the inserted Nb layers numbers for the first time. Finally, a model of Schottky barrier based on interfaces of Ti/MgB2 and Nb/MgB2 are used to explain the memory characteristics.

Passivity of memristive BAM neural networks with leakage and additive time-varying delays

This paper investigates the passivity of memristive bidirectional associate memory neural networks (MBAMNNs) with leakage and additive time-varying delays. Based on some useful inequalities and appropriate Lyapunov–Krasovskii functionals (LKFs), several delay-dependent conditions for passivity performance are obtained in linear matrix inequalities (LMIs). Moreover, the leakage delays as well as additive delays are considered separately. Finally, numerical simulations are provided to demonstrate the feasibility of the theoretical results.

Heterogeneous Memristive Devices Enabled by Magnetic Tunnel Junction Nanopillars Surrounded by Resistive Silicon Switches

AbstractEmerging nonvolatile memories (NVMs) have currently attracted great interest for their potential applications in advanced low‐power information storage and processing technologies. Conventional NVMs, such as magnetic random access memory and resistive random access memory, suffer from limitations of low tunnel magnetoresistance, low access speed, or finite endurance. NVMs with synergetic advantages are still highly desired for future computer architectures. This study reports a heterogeneous memristive device composed of a magnetic tunnel junction (MTJ) nanopillar surrounded by resistive silicon switches, named resistively enhanced MTJ (Re‐MTJ), which may be utilized for novel memristive memories, enabling new functionalities that are inaccessible for conventional NVMs. The Re‐MTJ device features a high ON/OFF ratio of >1000% and multilevel resistance behavior by combining magnetic switching together with resistive switching mechanisms. The magnetic switching originates from the MTJ, while the resistive switching is induced by a point‐switching filament process that is related to the mobile oxygen ions. Microscopic evidence of silicon aggregated as nanocrystals along the edges of the nanopillars verifies the synergetic mechanism of the heterogeneous memristive device. This device may provide new possibilities for advanced memristive memory and computing architectures, e.g., in‐memory computing and neuromorphics.

Finite-Time Synchronization of Chaotic Memristive Multidirectional Associative Memory Neural Networks and Applications in Image Encryption

Traditional biological neural networks lack the capability of reflecting variable synaptic weights when simulating associative memory of human brains. In this paper, we propose a novel memristive multidirectional associative memory neural networks (MAMNNs) model with mixed time-varying delays. More precisely, the proposed model is investigated with time-varying delays and distributed delays. Then, we design two kinds of delay-independent and delay-dependent controllers to analyze the problem of finite-time synchronization. Based on the drive-response concept and Lyapunov function, some sufficient criteria guaranteeing the finite-time synchronization of the drive-response system are derived. With the removal of certain constraints on the weight parameters, the results we obtained for synchronization are less conservative. To illustrate the chaotic characteristics of the memristive MAMNNs, an image encryption scheme is designed. Meanwhile, the effectiveness of the proposed theories is validated with numerical experiments.

A Memristive Neural Network Model With Associative Memory for Modeling Affections

Memristor is a nonlinear resistor with memory, which has the characteristics of neuron synapses and can be used to design a new generation of memristive neural networks. Based on the Pavlov associative memory, a novel memristive associative memory neural network model is designed by using the charge-controlled nanoscale HP memristor model as the electronic synapse. This model includes neurons, memristor synapses, and weighted input feedback learning rule. Based on the proposed memristive associative memory model, a memristor-based neural network structure for simulating human emotions is further designed. The emotion simulation takes into account the excitation and inhibition between different neurons, making it more bionic. In order to simulate the memristive neural network structure, a relatively simplified emotional simulation circuit is constructed, which effectively reduces the network complexity and circuit power consumption. Finally, PSPICE is used to simulate the circuit. The simulation results not only verify the correctness of the model but also achieve a simple simulation of human emotions, which is helpful for the further development of the artificial neural network in the field of artificial intelligence.

Passivity of Memristive BAM Neural Networks with Probabilistic and Mixed Time-Varying Delays

This paper is concerned with the passivity problem of memristive bidirectional associative memory neural networks (MBAMNNs) with probabilistic and mixed time-varying delays. By applying random variables with Bernoulli distribution, the information of probability time-varying delays is taken into account. Furthermore, we consider the probability distribution of the variation and the extent of the delays; therefore, the results derived are less conservative than in the existing papers. In particular, the leakage delays as well as distributed delays are all taken into consideration. Based on appropriate Lyapunov-Krasovskii functionals (LKFs) and some useful inequalities, several conditions for passive performance are established in linear matrix inequalities (LMIs). Finally, numerical examples are given to demonstrate the feasibility of the presented theories, and the results reveal that the probabilistic and mixed time-varying delays have an unstable influence on the system and should not be ignored.

Synchronization Control of Memristive Multidirectional Associative Memory Neural Networks and Applications in Network Security Communication

In this paper, we investigate the synchronization in the mean square sense of memristive multidirectional associative memory neural networks with mixed time-varying delays and stochastic perturbations. In the proposed approach, the mixed delays include time-varying delays and distributed time delays. Sufficient criteria guaranteeing the synchronization of the drive-response system are derived based on the drive-response concept, the stochastic differential theory and Lyapunov function. With the removal of certain strict conditions of weight parameters, less conservative results are generated. To illustrate the performance of the proposed synchronization criteria, a secure communication scheme to realize secure data transmission is designed. Meanwhile, the effectiveness of the proposed theories is validated with numerical experiments.

Synchronization of a Class of Memristive Stochastic Bidirectional Associative Memory Neural Networks with Mixed Time-Varying Delays via Sampled-Data Control

The paper addresses the issue of synchronization of memristive bidirectional associative memory neural networks (MBAMNNs) with mixed time-varying delays and stochastic perturbation via a sampled-data controller. First, we propose a new model of MBAMNNs with mixed time-varying delays. In the proposed approach, the mixed delays include time-varying distributed delays and discrete delays. Second, we design a new method of sampled-data control for the stochastic MBAMNNs. Traditional control methods lack the capability of reflecting variable synaptic weights. In this paper, the methods are carefully designed to confirm the synchronization processes are suitable for the feather of the memristor. Third, sufficient criteria guaranteeing the synchronization of the systems are derived based on the derive-response concept. Finally, the effectiveness of the proposed mechanism is validated with numerical experiments.

Fixed-Time Synchronization of Memristive Fuzzy BAM Cellular Neural Networks With Time-Varying Delays Based on Feedback Controllers

This paper mainly investigates the fixed-time synchronization problem of memristive fuzzy bidirectional associative memory (BAM) cellular neural networks (MFBAMCNNs) with time-varying delays. MFBAMCNNs are formulated by virtue of differential inclusion and set-valued map theories. By utilizing the definition of fixed-time synchronization and some inequality techniques, some novel criteria for easy verification are derived to ensure the fixed-time synchronization of the drive-response MFBAMCNNs based on the Lyapunov stability theory and nonlinear feedback controllers. The results of the main theorem can be easily extended to the fuzzy BAM cellular neural networks without memristor and the memristive BAM cellular neural networks without fuzzy logic. In addition, the settling time of fixed-time synchronization, which does not depend on the initial values, can be simply calculated. At last, two numerical examples are presented to verify the effectiveness of main results.

$$H_{\infty }$$ H ∞ state estimation for discrete-time stochastic memristive BAM neural networks with mixed time-delays

In this paper, the $$H_\infty$$ state estimation problem is investigated for a class of discrete-time stochastic memristive bidirectional associative memory (DSMBAM) neural networks with mixed time delays. The mixed time delays comprise both discrete and distributed time-delays. A series of novel switching functions are proposed to reflect the state-dependent characteristics of the memristive connection weights in the discrete-time setting, which facilitates the dynamics analysis of the addressed memristive neural networks (MNNs). By means of the introduced series of switching functions, an $$H_\infty$$ state estimator is designed such that the estimation error is exponentially mean-square stable and the prescribed $$H_\infty$$ performance requirement is achieved. The gain matrices of the desired estimator are parameterized by utilizing the semi-definite programming method. Finally, a simulation example is employed to demonstrate the usefulness and effectiveness of the proposed theoretical results.