Memoryless Digital Predistortion Research Articles

A Wideband Energy-Efficient Multi-Mode CMOS Digital Transmitter

This article presents a wideband, energy-efficient digital transmitter (DTX) suitable for multi-mode/multi-band wireless communication applications. It features various operation modes comprising Cartesian (Modes-1/-2) and multi-phase (Modes-3/-4) configurations utilizing LO clocks with different duty cycle in the interleaving/non-interleaving configurations. The multi-phase operation compromises polar and Cartesian features by mapping the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> signals into two non-orthogonal basis vectors with a 45° relative phase difference and a 3-bit phase selector scheme. The different operation modes are extensively analyzed and compared. Fabricated in a 40-nm CMOS process with an off-chip matching network, the proposed DTX occupies a core area of 0.72 mm2 and delivers 23.18-dBm RF peak power at 2.1 GHz from a 0.95-V supply voltage with drain/system efficiencies of 66.26%/52.59%, respectively. Utilizing a simple memory-less digital pre-distortion (DPD) for a 160-MHz four-channel 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal, the DTX delivers an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P _{\text {Out}}$ </tex-math></inline-formula> of 13.5/11.4/7.7/9.4 dBm, achieving an adjacent channel (power) ratio (ACL(P)R) of better than −42/−40/−40/−38 dBc and an average error vector magnitude (EVM) of −36/−34/−34/−32 dB, operating in Modes-1/-2/-3/-4, respectively. While transmitting a 200-MHz single-channel 256 (1024)-QAM OFDM signal at 2.4 GHz in Modes-1/-4, the average delivered output power is 14.11/9.29 (12.23/7.32) dBm with average drain and system efficiencies of 33.17%/26.3% (23.82%/22.83%) and 24.81%/22.85% (19.34%/18.81%), while the ACLR and EVM are better than −42/−41 (−43/−43) dBc and −34.6/−33.1 (−33.5/−33.9) dB, respectively.

Millimeter Wave SOI-CMOS Power Amplifier With Enhanced AM-PM Characteristic

This paper proposes a novel inter-stage load-pull characterization method to enhance the linearity of millimeter wave integrated power amplifiers (PAs) by minimizing their amplitude-to-phase (AM-PM) distortion without worsening their AM-AM or efficiency performances. The proposed method identifies the optimal solution for the inter-stage matching network which enables the synthesis of a driver stage AM-PM characteristic that is complementary to that of the power stage; consequently, reducing the overall AM-PM distortion of the PA. The proposed technique is applied to design a proof-of-concept 28–31 GHz PA demonstrator using 45 nm silicon-on-insulator CMOS technology. The measurement results obtained under continuous wave excitation at 29 GHz demonstrate an excellent AM-PM characteristic, with phase distortions as low as 0.2° at the 1-dB compression power level of 13.9 dBm and less than 1° at an output power level of up to 16 dBm (very close to the saturation power of 16.6 dBm). This enhanced AM-PM linearity improves the linearizability of the PA. This was confirmed by testing the PA with a 64 quadrature amplitude modulated test signal with an instantaneous bandwidth of 800 MHz. Without applying any digital pre-distortion (DPD) technique, the PA delivers a power added efficiency (PAE) of 8.7% at an average output power ( $P_{avg}$ ) of 9.4 dBm while maintaining an error vector magnitude (EVM) of −25 dB. However, after applying a very simple memoryless DPD function with only four coefficients, the PA can operate at a higher $P_{avg}$ of 11.1 dBm with a much better PAE of 12.2% while still maintaining an acceptable EVM of −25.2 dB. Thanks to the proposed technique, the PAE of the proposed PA can be improved by 40% with a very simple application of a low cost and low complexity DPD technique.

A Multilevel Pulse-Modulated Polar Transmitter Based on a Doherty Power Amplifier and Memoryless Digital Predistortion

This letter presents an aliasingfree multilevel pulse modulation (MLPM) architecture to implement a linear Doherty power amplifier (PA). This letter is believed to be the first reported results of this type of Doherty architecture to achieve linear amplification rather than the usual situation of a continuous amplitude modulated carrier and continuous load modulation. Our results show that both high efficiency and good linearization can be achieved with simple memoryless digital predistortion. Doherty operation with MLPM is believed to have benefits in linearization due to the MLPM discrete drive as less power is dissipated by the PA, leading to less thermal-related memory effects. A prototype transmitter system is constructed using a commercially available Doherty PA for validation. Measurements are performed using a 64-QAM long-term evolution (LTE) downlink signal at 2140 MHz with 20-MHz bandwidth. The overall system achieved an output power level of 40.1 dBm with a power-added efficiency of 39.5% while passing the −45-dBc downlink spectral requirements of the LTE standard.

An Efficient Combined Scheme of Proposed PAPR Reduction Approach and Digital Predistortion in MIMO-OFDM Systems

The combination of Multiple Input Multiple Output (MIMO) system with Orthogonal Frequency Division Multiplexing (OFDM) technology provides a powerful choice to increase channel capacity and improves the quality of service of wireless mobile communication systems. However, MIMO-OFDM systems are prone to high Peak-to-Average Power Ratio (PAPR), which leads to more interference and greatly limits the efficiency of the transmit high power amplifier (HPA). In this article, we propose a combinational approach is proposed, a PAPR reduction with memoryless digital predistortion (PRDPD) in order to combat PAPR in MIMO-OFDM, to improve HPA efficiency as well as linearity, and to mitigate in-band distortion and spectrum regrowth. The main idea of PAPR reduction is the rotation of phase independently in frequency and time domain based on Partial Transmit Sequence (PTS) and Selected Mapping (SLM) techniques with minimum complexity. This analysis is carried out based on Solid State Power Amplifiers (SSPA) of Saleh model and digital predistortion (DPD) as linearization technique. The simulation results show that the proposed scheme cannot only significantly reduce the PAPR, but also improves out-of-band radiation over other conventional techniques.

Design of a Fully Integrated Two-Stage Watt-Level Power Amplifier Using 28-nm CMOS Technology

We present a linear two-stage power amplifier (PA) for UMTS terrestrial radio access (UTRA) applications. The PA has been designed using a standard 28-nm complementary metal–oxide–semiconductor process. It includes an on-chip input matching network, a predriver stage, and an on-chip output matching network. Additional process-voltage-temperature compensation circuits and electrostatic discharge protection have been implemented on-chip. A differential triple-stack transistor array acts as transconductance circuit and generates watt-level RF output power. Measured saturated output power is more than 31 dBm and peak power-added efficiency is 33% for sinusoidal operation at 1.8 GHz. When applying memoryless digital predistortion (DPD) for 3rd Generation Partnership Project (3GPP) UTRA test vectors, an adjacent-channel leakage ratio of $\leq -$ 33 dBc at $\pm$ 5 MHz for 26.5-dBm output power is achieved. A corresponding error-vector magnitude of $\leq$ 1.7% can be measured when using memoryless DPD.

Broadband Sequential Power Amplifier With Doherty-Type Active Load Modulation

This paper presents the concept and the detailed analysis of a sequential power amplifier with Doherty-type active load modulation (SPA-D). By introducing a Doherty-type output combiner into the conventional sequential power amplifier (PA), highly efficient amplification over broadband and wide dynamic range for the reconfigurable output power back-off can be achieved. The proposed amplifier mimics both the sequential and the Doherty PAs by exploiting the active load modulation region that has not been considered in the design of Doherty amplifiers. A broadband SPA-D prototype having 8-dB output back-off power (OBO) is designed and implemented. The experimental results exhibit drain efficiencies of 50%-75% at 7-10-dB OBO and 57%-70% at peak power with Doherty-like behavior over 700-MHz bandwidth centered at 2.35 GHz. The ability to easily reconfigure the breakpoint is experimentally verified, providing a convenient means for optimizing the amplifier efficiency according to various wireless standards. In addition, by using a memoryless digital predistortion, the spectrum emission mask required for long-term evolution down link can be fulfilled, making it well suited for applications in modern wireless transmitters.

Broadband CMOS Stacked RF Power Amplifier Using Reconfigurable Interstage Network for Wideband Envelope Tracking

In this paper, a two-stage broadband CMOS stacked FET RF power amplifier (PA) with a reconfigurable interstage matching network is developed for wideband envelope tracking (ET). The proposed RF PA is designed based on Class-J mode of operation, where the output matching is realized with a two-section low-pass matching network. To overcome the bandwidth (BW) limitation from the high- Q interstage impedance, a reconfigurable matching network is proposed, allowing a triple frequency mode of operation using two RF switches. The proposed RF PA is fabricated in a 0.32- μm silicon-on-insulator CMOS process and shows continuous wave (CW) power-added efficiencies (PAEs) higher than 60% from 0.65 to 1.03 GHz with a peak PAE of 69.2% at 0.85 GHz. The complete ET PA system performance is demonstrated using the envelope amplifier fabricated on the same process. When measured using a 20-MHz BW long-term evolution signal, the overall system PAE of the ET PA is higher than 40% from 0.65 to 0.97 GHz while evolved universal terrestrial radio access adjacent channel leakage ratios are better than -33 dBc across the entire BW after memoryless digital pre-distortion. To our knowledge, this study represents the highest overall system performance in terms of PAE and BW among the published broadband ET PAs, including GaAs HBT and SiGe BiCMOS.

Dynamic Stack-Controlled CMOS RF Power Amplifier for Wideband Envelope Tracking

In this paper, a dynamic stack-controlled CMOS FET RF power amplifier (PA) is developed to enhance the efficiency of the envelope tracking power amplifier (ET PA) system for low-voltage operation. The power cell used in the two-stage PA is a quadruple-stacked FET structure with dynamic stacking controller to reconfigure the power cell into the quasi-triple or quasi-double stacks according to the magnitude of the input envelope signal. The proposed power cell boosts the peak efficiency in the low V DD region by bypassing the stack entering the triode region and reoptimizing the load impedance so that all the FETs operate under the saturation and the optimum load conditions. A detailed analysis is presented to understand the gain and phase step discontinuities at the stack switching points, and the circuit techniques to equalize the gain and phase between the adjacent stack configurations are developed. The proposed two-stage stack-controlled PA is fabricated with a 0.32-μm silicon-on-insulator (SOI) CMOS process together with the envelope amplifier (EA). Full long-term evolution (LTE) characterization is performed using LTE signals with a peak-to-average power ratio (PAPR) of 6.7 dB and signal bandwidths (BW) of 10 and 20 MHz. With 10-MHz signals, dynamic stacking provides 3.5% power added efficiency (PAE) improvement over the static stack at 25.7 dBm, resulting in 47.5% PAE with 26.6-dB gain. A 20-MHz LTE test shows an overall PAE of 45.9% with an evolved universal terrestrial radio access (E-UTRA) adjacent channel leakage ratio (ACLR) of -33 dBc with memoryless digital predistortion. Even with the lower efficiency of the EA compared with the state-of-the-art results, the measured overall system efficiency with 3.4 V maximum voltage is comparable with those reported using GaAs HBT's with 5 V supplies, which clearly demonstrates the advantages of the proposed dynamic stack control.

A Package-Integrated Chireix Outphasing RF Switch-Mode High-Power Amplifier

This paper describes the design and implementation of a package-integrated Chireix outphasing RF switch-mode power amplifier (PA). The optimum loading conditions, based on class E, and the Chireix compensation elements are provided to the active devices by a dedicated low-loss bondwire-based transformer power combiner that enables a very small form factor and low cost. The realized prototype achieved 70.6-W peak power with 73% peak drain efficiency at 2.3 GHz and 28 V, and up to 81% peak drain efficiency at 2.2 GHz and 20 V. When operated for maximum power at 28 V, it reached 53.5%/43.5% average drain/total efficiency for a 9.6-dB peak-to-average-power-ratio W-CDMA signal at 2.3 GHz with low ACLR1/2 levels ( -49/ -56 dBc after memoryless digital predistortion). Moreover, from 2.1 to 2.4 GHz, the realized PA demonstrated more than 50% drain efficiency across > 260, > 160, and > 80 MHz at 6-, 8-, and 10-dB back-off, respectively.

A SiGe PA With Dual Dynamic Bias Control and Memoryless Digital Predistortion for WCDMA Handset Applications

This paper demonstrates a two-stage 1.95-GHz WCDMA handset RFIC power amplifier (PA) implemented in a 0.25-/spl mu/m SiGe BiCMOS process. With an integrated dual dynamic bias control of the collector current and collector voltage, the average power efficiency of the two-stage PA is improved from 1.9% to 5.0%. The measured power gain is 18.5 dB. The gain variation with dynamic biasing is less than 1.8 dB. An off-chip memoryless digital predistortion linearizer is also adopted, satisfying the 3GPP wideband code division multiple access (WCDMA) linearity specification by a 10 dB improvement of adjacent channel power ratio (ACPR) at +26 dBm average channel output power.

Realistic power-amplifiers characterization with application to baseband digital predistortion for 3G base stations

In this paper, a realistic, accurate, versatile, and thermal-free complex behavior test bed suitable for third-generation power-amplifiers characterization is proposed. Using this approach, a 90-W peak power amplifier based on Motorola-LDMOS class-AB transistors was measured under several signal excitations such as W-CDMA, cdma2000, and eight-tone signals. The results obtained show noticeable discrepancies compared to those measured using a vector network analyzer (HP-8510C) for both AM/AM and AM/PM curves. This test bed was also used for the investigation of the memory effect in RF power amplifiers. In the second part of this paper, the characterization results obtained by the test bed were used to design a digital predistorter for an LDMOS amplifier. A baseband predistortion accurate synthesis algorithm is presented. Indeed, a memoryless baseband digital predistorter lookup table was directly synthesized using the measured AM/AM and AM/PM curves without any need to perform additional analytical derivations and/or numerical optimizations. The predistorter synthesis procedure requires only one iteration, contrary to previous works, which need several iterations to obtain similar performances.