Memory Reference Instructions Research Articles

Low-power and real-time address translation through arithmetic operations for virtual memory support in embedded systems

An arithmetic-based address translation technique is presented for low-power and real-time embedded processors with virtual memory support. General-purpose virtual memory support comes with its disadvantages of excessive power consumption and nondeterministic execution times, which are the main reasons for not adopting virtual memory in energy-efficient and real-time embedded systems. To address these issues, an application-driven address translation is proposed, where most of the address translations, which are traditionally performed as translation lookaside buffer (TLB) lookups, are replaced with fast and energy-efficient addition operations. To achieve this, a program and system-wide information is used to identify sequences of consecutive virtual page numbers, which are mapped to sequences of consecutive physical page frames. For such pairs of page sequences, only the addition of a constant to the virtual page number is needed to produce the physical page frame. The proposed methodology relies on the combined efforts of compiler, operating system, and hardware architecture to achieve a significant power reduction. As the approach fundamentally eliminates conflicts inherent in the hardware translation table, execution time is not only improved but also made predictable for a large number of memory reference instructions. Experiments show power reductions in the range of 80–95% compared to a general-purpose TLB.

DYNAMEM — A microarchitecture for improving memory disambiguation at run-time

This paper presents a new microarchitecture technique named DYNAMEM, in which memory reference instructions are dynamically scheduled and can be executed out-of-order. Load instructions can bypass store instructions speculatively, even if the store instructions’ addresses are unknown. DYNAMEM can greatly alleviate the restraints of ambiguous memory dependencies. Simulation results show that the frequency of false load is low. Mechanism has been provided to repair false loads with low penalty, and to achieve precise interrupts. Discussions and experimental results show that DYNAMEM could dramatically raise instruction-level parallelism in programs without recompilation.

COGLAB: A computer system designed for human research

RICHARD L. TAYLOR Memorial University of Newfoundland, St. John's, Newfoundland, Canada COGLAB: A computer system designed for human research* by memory reference instructions. giving a program in memory exclusive control of the 1/0. Since the DOS-M Disk Manager and Job Processor are always in core and protect Locations 1-0100. it was necessary to have a device for wresting I/O control from DOS-M. 4. For many purposes. this kind of pseudorandom generator will serve. However. for simulation wolk bias and failure of runs up and down to be random