Memory Power Consumption Research Articles

Thermodynamic properties and switching dynamics of perpendicular shape anisotropy MRAM

The power consumption of modern random access memory (RAM) has been a motivation for the development of low-power non-volatile magnetic RAM (MRAM). Based on a CoFeB/MgO magnetic tunnel junction, MRAM must satisfy high thermal stability and a low writing current while being scaled down to a sub-20 nm size to compete with the densities of current RAM technology. A recent development has been to exploit perpendicular shape anisotropy along the easy axis by creating tower structures, with the free layers’ thickness (along the easy axis) being larger than its width. Here we use an atomistic model to explore the temperature dependent properties of thin cylindrical MRAM towers of 5 nm diameter while scaling down the free layer from 48 to 8 nm thick. We find thermal fluctuations are a significant driving force for the switching mechanism at operational temperatures by analysing the switching field distribution from hysteresis data. We find that a reduction of the free layer thickness below 18 nm rapidly loses shape anisotropy, and consequently stability, even at 0 K. Additionally, there is a change in the switching mechanism as the free layer is reduced to 8 nm. Coherent rotation is observed for the 8 nm free layer, while all taller towers demonstrate incoherent rotation via a propagated domain wall.

Dynamic Power Reduction in TCAM Using Advanced Selective Pre-Charging of Match Lines

In this paper, we propose a power-efficient memory operation, selective match line precharge, based on an analysis of power consumption in ternary content-addressable memory (TCAM). A statistical study reveals that, on average, 58% of power dissipation related to the match line operation is saved by deactivating the unnecessary swing of match lines. The improvement has been simulated and proved using 180 nm CMOS technology.

Optimal FPGA memory allocation for image processing

In the field of computer vision, Field Programmable Gate Array (FGPA) limited de on-chip memory is difficult to meet the power, size and other requirements. To address this phenomenon, the study constructs a partitioning algorithm to achieve a balance between energy consumption and resource utilisation based on the analysis of memory resource allocation, overall power consumption and resource utilisation from the perspective of image processing technology. The power consumption of the balancing algorithm is lower compared to the optimised utilisation algorithm HLS tool, with both Block Ramdom Access Memory (BRAM) power consumption taking the value of 0.005; the dynamic power consumption takes the value range of 0.014–0.082. Compared to the High Level Synthesis (HLS) tool, the overall power consumption of the balancing algorithm and the optimised utilisation algorithm is significantly lower, with the values of 0.251 and 0.252 respectively, both with a reduction rate of approximately 30%. The accuracy rate of the proposed memory optimisation allocation algorithm is the highest among the four memory optimisation allocation algorithms and strategies on all three types of target scales. FPGA memory optimisation allocation strategy can guarantee to have lower power consumption while satisfying the same resource occupancy, and the model has in-depth application value in visual image vision technology.

Enhanced Polarization Effect of Flexible Magnetoelectric PVDF-TrFE/Fe3O4 Smart Nanocomposites for Nonvolatile Memory Application

High power consumption of nonvolatile memory is a major challenge, as it reduces the memory efficiency of information storage devices. The magnetoelectric (ME) coupling in multiferroic nanocomposites, which can be utilized in magnetoelectric random access memory, is an effective approach to reduce power consumption in information storage. Here, a type of ME nanocomposite embedded with 0.5 wt % Fe3O4 is presented, exhibiting higher ME voltage coefficients for piezoelectric thin films. Specifically, the ME voltage coefficient of the P(VDF-TrFE)/Fe3O4 composite developed in this study is 8.97 mV/(cm·Oe), which is 17.5% higher compared to that of the pure P(VDF-TrFE) at a Hdc of 1000 Oe. Meanwhile, the enhanced ME effect of smart nanocomposites is characterized by the increase of diffraction peak intensity at a microscopic level. The nanocomposite films exhibit high ME voltage coefficients and information storage performance, providing a great potential for creating next-generation memory devices in the realm of artificial intelligence and wearable devices.

OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse Weight Transposer

In this article, we present an energy-efficient deep reinforcement learning (DRL) processor, OmniDRL, for DRL training on edge devices. Recently, the need for DRL training is growing due to the DRL’s distinct characteristics that can be adapted to each user. However, a massive amount of external and internal memory access limits the implementation of DRL training on resource-constrained platforms. OmniDRL proposes four key features that can reduce external memory access by compressing as much data as possible and can reduce internal memory access by directly processing compressed data. A group-sparse training (GST) enables a high weight compression ratio (CR) for every DRL iteration by selective utilization of weight grouping and weight pruning. A group-sparse training core is proposed to fully take advantage of compressed weight from GST by skipping redundant operations and reusing duplicated data. An exponent-mean-delta encoding additionally compresses the exponent of both weight and feature map for higher CR and low memory power consumption. A world-first on-chip sparse weight transposer enables the DRL training process of compressed weight without off-chip transposer. As a result, OmniDRL is fabricated in a 28-nm CMOS technology and occupies a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.6\times 3.6$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area. It shows a state-of-the-art peak performance of 4.18 TFLOPS and a peak energy efficiency of 29.3 TFLOPS/W. It achieved 7.42-TFLOPS/W energy efficiency for training robot agent (Mujoco Halfcheetah, TD3), which is 2.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> higher than the previous state of the art.

FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies

Cache memories are an indispensable component of many processor-based systems and contribute significantly to the overall area, power consumption, and delay. This leads to an important role played by modeling tools for estimating the area, power consumption, and access time of cache memories. However, existing modeling tools such as CACTI and its various extensions have been primarily designed using data from various projections. For the first time, we propose an entire flow for obtaining/calibrating the transistor characteristics from a commercial technology and use these characteristics within CACTI. We also improve the modeling approach to make them more fine-grained and follow recent manufacturing trends suitable for FinFET technology. Further, for the first time, we extend CACTI to support negative capacitance fin field effect transistor (NC-FinFET), an emerging technology depicting negative capacitance whose current and capacitive characteristics are very different compared to those of the FinFET. We use the proposed tool (FN-CACTI) to identify NC-FinFET-based caches to be significantly more energy-efficient than corresponding FinFET-based caches. We also study an application of FN-CACTI to determine optimal voltages corresponding to the lowest energy consumption for NC-FinFET and FinFET-based caches of various sizes.

Supporting Swap in Real-Time Task Scheduling for Unified Power-Saving in CPU and Memory

As the size of data grows rapidly in modern IoT (Internet-of-Things) and CPS (Cyber-Physical System) applications, the memory power consumption of real-time embedded systems increases dramatically. Unlike general-purpose systems where memory consumes about 10&#x0025; of the CPU power consumption, modern real-time systems have the memory power of 20&#x2013;50&#x0025; of CPU power. This is because the memory size of a real-time system should be large enough to accommodate the entire task set, and thus DRAM refresh operations become a major source of power consumption. In this article, we present a new swap scheme for real-time systems, which aims at reducing memory power consumption. To support swap with real-time constraints, we adopt high-speed NVM storage and co-optimize power-savings in CPU and memory. Unlike traditional real-time task models that only consider the executions in CPU, we define an extended task model that characterizes memory and storage paths of tasks as well, and tightly evaluate the worst-case execution time by formulating the overlapped latency between CPU and memory. By optimizing the CPU supply voltage and the memory swap ratio of given task set, our scheme reduces the energy consumption of real-time systems by 31.1&#x0025; on average under various workload conditions.

Low power SRAM cell design with power gating technique

The power consumption of Static Random-Access Memory (SRAM) cell is considered as a major factor in modern technologies due to voltage scaling. The existing SRAM cell design of consumes more power at higher frequencies. In the proposed work, power reduction is achieved in various radiation-hardened SRAM cell designs which is based on power gating technique. Hence, the power gated voltage (VDD) design technique is employed to reduce power consumption.

ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor

The authors propose a heterogeneous floating-point (FP) computing architecture to maximize energy efficiency by separately optimizing exponent processing and mantissa processing. The proposed exponent-computing-in-memory architecture and mantissa-free exponent-computing algorithm reduce the power consumption of both memory and FP MAC while resolving previous FP computing-in-memory processors’ limitations. Also, a bfloat16 DNN training processor with proposed features and sparsity exploitation support is implemented and fabricated in 28-nm CMOS technology. It achieves 13.7-TFLOPS/W energy efficiency while supporting FP operations with CIM architecture.

Novel low‐power and stable memory cell design using hybrid CMOS and MTJ

SummaryMemory is an essential component of any VLSI data storage system. Because of the shrinking of CMOS processing nodes, power consumption in conventional memory (SRAM and DRAM) increases. Traditional memory technologies also suffer several additional difficulties, such as limited scalability, low reliability, short data retention time, low durability, increased space, and latency, among others. As a result, new device technologies are critical for developing low‐power, high‐performance memory devices. Among the numerous developing nonvolatile (NV) memory technologies available today, STT‐MRAM is regarded as one of the most appealing and promising NV memory technologies for overcoming the limitations of traditional memories. STT‐MRAM is more efficient, quicker, NV, highly scalable, and readily integrated with CMOS technology. Because of the scalability of technology nodes below 45 nm, traditional STT‐MRAM cells have several difficulties, including high write power consumption, destructive read and write operation, prolonged write time, and so on. To address the issues associated with the writing operation of STT‐MRAM cells, this article presented an optimum STT‐MRAM cell design based on PMA‐MTJ. The write failure mitigation strategies are utilized to increase the proposed cell's write stability. A comparative analysis between conventional STT‐MRAM cell and the proposed cell is performed by concerning the write power consumption, write delay, and write stability. The experimental results indicate the performance superiority of the proposed cell architecture.

IDC Sensor for Low-Cost Water Quality Monitoring Applications

In order to properly monitor the health status of the hydrological resources of a region, in terms of water contamination, a scalable and low-cost system is necessary to map the water quality at different locations and allow the prioritization of more sophisticated and expensive monitoring campaigns on those areas where a suspicious behavior seems to be occurring. This paper presents the design and implementation process of such an IoT-based solution for low-cost and scalable water quality monitoring applications. To achieve that end, we propose the utilization of a low-cost inter-digital capacitance (IDC) sensor to characterize the conductivity of the water, a very telling parameter about the level of pollution in the water. Additionally, an embedded method to measure such sensor was designed and implemented, which considers the requirements of a portable platform: low computational capabilities, small memory and low power consumption. Our results show that an IDC sensor is capable of detecting the changes of the capacitance of the sample, and therefore mapping the changes in the conductivity of the water. Additionally, integrating an embedded measuring method is a valid option for in-situ characterization of water samples and the complete solution enables a new paradigm for water quality monitoring in large scale scenarios.

Design and Optimization of 4-BIT Static RAM and 4-BIT Dynamic RAM for Compact and Portable Devices

As technology advances, the combined compactness of transistors also increases. Portable electronics such as cellphones, notebooks, and laptops are in high demand. The enhanced innovation reduces the feature value for this compact design. Devices with a small feature set require less electricity to operate. The edge voltage is reduced when the power source is reduced. Low-limit devices perform better, but in such a deep submicron domain, sub-edge leakage current is critical. As a result, architects should focus on decreasing leakage. Several field workers have presented divergent ideas to explain this. A 4-bit static RAM cell using the reduction of the leakage power consumption (sleepy stack) technique and the 4-bit DRAM is proposed in this paper. The RAMs' schematic was produced using DSCH, and their layout was built using MICROWIND. Improved power consumption in static random-access memory by combining a sleepy stack with a keeper strategy and constructing a 4-bit dynamic random-access memory was explained as a result of this research. According to the findings, the higher the technology used, the higher the power consumption. On the other hand, after assessing the results, SRAM uses less electricity and has more transistors per memory.

Thermal design power and vectorized instructions behavior

AbstractVectorized instructions were introduced to improve the performance of applications. However, they come at the cost of an increase in the power consumption. As a consequence, processors are designed to limit their frequency when such instructions are used in order to respect the thermal design power limit. In this paper, we study and compare the impact of thermal design power and Simple Instruction Multiple Data (SIMD) instructions on performance, power and energy consumption of processors and memory. The study is performed on three different architectures providing different characteristics and four applications with different profiles (including one application with different phases, each phase having a different profile). The study shows that, because of processor frequency, performance and power consumption are strongly related to thermal design power. It also shows that AVX512 has unexpected behavior regarding processor power consumption, while DRAM power consumption is impacted by SIMD instructions because of the generated memory throughput. Finally, this paper tackles the impact of turboboost which shows equivalent to better performance for all the studied cases while not always decreasing energy consumption.

Spatiotemporal signal processing and device stability based on bi-layer biomimetic memristor

The neural network under the current computer architecture is difficult to process complex data efficiently, thus becoming one of the bottlenecks restricting the development of artificial intelligence technology. The human brain has the characteristics of high efficiency, low power consumption and integration of memory and computing, and is regarded as a most potential computing system to break the traditional von Neumann computing system. Synaptic biomimetic device is to realize the neural mimicry of human brain from the hardware level. It can simulate the information processing mode of brain nerve, that is, the process of “memory” and “calculation” can be realized on the same device, which is of great significance in building a new computing system. In recent years, the fabrication of memristor materials for bio-mimetic synaptic devices has made progress, but most of them focus on the simulation of synaptic function. The key research of pulse signal perception and information transmission is relatively lacking. In this paper, an bi-layer memristor with structure Al/nc-Al AlN/A&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;/Ag is fabricated by rf sputtering method to realize the basic functions of bionic synaptic devices. It is found that this bio-mimetic memristor exhibits bipolar switching property which is the basic condition to produce memristor based neural synapse. Both of PPF and PPD process can be observed and there will be no firing signal observed if the pulse interval is as large as 350 ms. The change of device conductance should be related to pulse voltage, frequency and pulse number applied. The larger pulse voltage, frequency and number will cause device conductance to increase sharply in both positive and negative pulse voltage region. The STDP measurement is executed with different sequence pulses from post and previous neuron separately. If the pulse of previous synapse comes in front of pulse from post synapse, the conductance will increase, which is so-called LTP process. If the pulse of previous neuron comes behind of pulse from post neuron, the conductance will be reduced as well. Triplet STDP measurement is executed with at least three pulses from previous and post neuron at the meanwhile. It is concluded that if the interval time of the first two pulses is fixed, the device conductance more depends on the value of the second and third pulse interval. Ebbinghaus forgetting curve can be used to explain the reason why the device conductance declines with time going by. The stability study of this memristor includes endurance and retention properties at both room and high temperature. It is found this biomimetic memristor can maintain its conductance for over 115.7 days at 85 ℃, which is long enough for current neural network design.

An [formula omitted]-Channel Band-to-Band Tunneling Flash Memory Design Optimization

This letter describes the design optimization of a flash memory cell that uses source-induced band-to-band hot electron (SIBE) injection programming method. The programming efficiency is determined by the tunneling current to the floating gate, which is shown to be dependent with the gate length covered width. Optimal gate length covered width is empirically studied in this work through simulation, and we are able to observe more than an order of magnitude increase in the programming efficiency which tremendously reducing the total power consumption of the flash memory.

Current suppressed self-compliance characteristics of oxygen rich TiOy inserted Al2O3/TiOx based RRAM

Although many studies have been continuously conducted to reduce the power consumption of a resistive random access memory (RRAM) cross-point array with the current-compliance effect, it has been difficult yet to realize intrinsic self-compliance effects in an RRAM device itself. In this study, a simple oxygen-rich TiOy layer is inserted into the Al2O3/TiOx-based RRAM stack as a current suppression layer, and XPS analysis is provided to compare the stoichiometry of the TiOx and TiOy layers. A self-compliance region is formed between the different breakdown voltages of Al2O3 and TiOy layers, and a relatively thinner current path is formed in the Al2O3 layer than a device without the TiOy layer and the overall current level is significantly decreased since the TiOy layer limits the overshoot current.

Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations

The superiority of various Deep Neural Networks (DNN) models, such as Convolutional Neural Networks (CNN), Generative Adversarial Networks (GAN), and Recurrent Neural Networks (RNN), has been proven in various real-world applications and has received much attention. However, different DNN models include various types of operations. For example, CNN models are usually composed of convolutional layers (Conv) and fully-connected layers (FC). Furthermore, some light CNN models such as MobileNet adopt depthwise separable convolution with depthwise convolution (DWC) and pointwise convolution (PWC) to compress the models. In addition to regular convolution, de-convolution (De-Conv) is also widely used in many GAN models. Moreover, many RNN models also employ long-short-term memory (LSTM) to control update of internal states and data. Such a high diversity of various DNN operations poses great design challenges in implementing reconfigurable Deep Learning (DL) accelerators, which can support various types of DNN operations. Most recent DL accelerators focus only on some DNN operations, which lacks computing flexibility. In this paper, by exploiting the sparsity in current DNN models, we design sparsity-aware DL hardware accelerators that can support efficient computation of various DNN operations, including Conv, DeConv, DWC, PWC, FC, and LSTM. Through reconfiguring dataflow and parallelizing different operations, the proposed designs not only improve system performance but also increase hardware utilization with a significant reduction of power consumption in memory accesses and arithmetic computations.

A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability

Scaling of supply voltage is a well-received approach to reduce power consumption in Static Random Access Memory (SRAM). However, conventional 6T and 8T SRAMs suffer from degraded stability due to random process variations, thereby limiting voltage scaling. It has been observed that Schmitt Trigger (ST) based SRAMs exhibit much better stability than conventional 6T and 8T SRAMs. However, ST based SRAMs inherently suffer from poor write-ability and therefore, exhibit overall higher VMIN. In this work, we propose a twelve-transistor ST based SRAM bit cell, aimed at enabling process-variation-tolerant write-ability, consequently allowing an overall reduction in VMIN and energy per operation. Simulations on the 32 ​nm process node demonstrate that the proposed SRAM allows up to 188 ​mV reduction in VMIN over previous ST bit cells. This translates to up to 3.65 × and 1.91 × lower energy consumptions than conventional 6T and ST-based SRAMs respectively. With large reductions in energy per operation at VMIN, the proposed SRAM is suitable for ultra-low power applications.

Evolution-Based Real-Time Job Scheduling for Co-Optimizing Processor and Memory Power Savings

With the recent advances in battery-based mobile computing technologies, power-saving techniques in real-time embedded devices are becoming increasingly important. This paper presents a novel job scheduling policy for real-time systems, which aims at minimizing the power consumption of processor and memory without missing the deadline constraints of real-time jobs. To do so, we formulate the power saving techniques of processor voltage/frequency scaling and memory job placement as a unified measure, and show that it is a complex search problem that has the exponential time complexity. Thus, an efficient heuristic based on evolutionary computation is performed to cut down the huge searching space and find a reasonable schedule within the feasible time budget. To evaluate the proposed scheduling policy, we conduct experiments under various workload conditions. Our experimental results show that the proposed policy significantly reduces the energy consumption of real-time systems. Specifically, the average reduction in the energy consumption is 41.7% without deadline misses.

A first-principles study of the switching mechanism in GeTe/InSbTe superlattices.

Interfacial Phase Change Memories (iPCMs) based on (GeTe)2/Sb2Te3 superlattices have been proposed as an alternative candidate to conventional PCMs for the realization of memory devices with superior switching properties. The switching mechanism was proposed to involve a crystalline-to-crystalline structural transition associated with a rearrangement of the stacking sequence of the GeTe bilayers. Density functional theory (DFT) calculations showed that such rearrangement could be achieved by means of a two-step process with an activation barrier for the flipping of Ge and Te atoms which is sensitive to the biaxial strain acting on GeTe bilayers. Within this picture, strain-engineering of GeTe bilayers in the GeTe–chalcogenide superlattice can be exploited to further improve the iPCM switching performance. In this work, we study GeTe–InSbTe superlattices with different compositions by means of DFT, aiming at exploiting the large mismatch (3.8%) in the in-plane lattice parameter between GeTe and In3SbTe2 to reduce the activation barrier for the switching with respect to the (GeTe)2–Sb2Te3 superlattice.