Core Memory Research Articles

Development of a cycle-accurate simulator of the Elbrus processor core memory subsystem

Increasing complexity of modern microprocessors, combined with semiconductor technology progress slowdown, make a further increase in performance more difficult. Under these circumstances, the relevance of the performance estimations of prospective microprocessors by dint of cycle-accurate simulation prior to their production in silicon is of growing importance. The approach to implementation of cycle-accurate simulator of core memory subsystem for Elbrus architecture, controlled by the existing functional simulator of this architecture, is presented herein. The method for validation of a cycleaccurate simulator by comparison with modeling of the RTL description of the prospective microprocessor is considered. The data on the speed of the cycle-accurate simulator and the main optimization methods, which were used to achieve acceptable performance, are presented. The preliminary estimates of the impact on the performance of some changes in the prospective processor core, including the cache access latency and hardware support for virtualization, obtained with the help of the cycle-accurate simulator are given. These assessments are important for making architectural decisions when designing the prospective Elbrus architecture processors.

NVQuery: Efficient Query Processing in Nonvolatile Memory

Today’s computing systems use a huge amount of energy and time to process basic queries in database. A large part of it is spent in data movement between the memory and processing cores, owing to the limited cache capacity and memory bandwidth of traditional computers. In this paper, we propose a nonvolatile memory-based query accelerator, called NVQuery, which performs several basic query functions in memory including aggregation, prediction, bit-wise operations, join operations, as well as exact and nearest distance search queries. NVQuery is implemented on a content addressable memory and exploits the analog characteristic of nonvolatile memory in order to enable in-memory processing. To implement nearest distance search in memory, we introduce a novel bitline driving scheme to give weights to the indices of the bits during the search operation. To further improve the energy efficiency, our design supports configurable approximation by adaptively putting memory blocks under voltage overscaling. Our experimental evaluation shows that a NVQuery can provide $49.3{\boldsymbol \times }$ performance speedup and $32.9{\boldsymbol \times }$ energy savings as compared to running the same query on traditional processor. Approximation improves the energy-delay product (EDP) of NVQuery by $7.3{\boldsymbol \times }$ , while providing acceptable accuracy. In addition, NVQuery can achieve $30.1{\boldsymbol \times }$ EDP improvement as compared to the state-of-the-art query accelerators.

Predictors of Reading Skills in Children With Listening Concerns.

Previous research shows that children with reading disorders perform poorly on auditory processing (AP) tasks. Correlational studies have also shown significant associations between some AP tasks and word and nonword reading. There is less clear evidence for AP contributions to spelling and passage reading. The aim of this research was to extend current knowledge by investigating the association between a range of AP measures used clinically and children's reading of words, nonwords, and passages, as well as word spelling. Regression analyses were conducted on data from 90 children 7 to 13 years of age (58 males) with reported listening and/or reading concerns. All children had normal hearing sensitivity and were tested on AP tasks including the frequency pattern test (FPT), dichotic digits test, random gap detection test, and the masking level difference. Reading tasks included word, nonword, and passage reading. Phonologic processing, core language skills, nonverbal intelligence, memory, and attention were also measured. All multiregression analyses were fixed order with age and gender, nonverbal intelligence, core language, phoneme manipulation, and digits backward scores included in the model before AP measures. FPT was the only AP task that accounted for significant unique variance in word/nonword reading and nonword spelling, but not passage reading. The findings from this study failed to show an association between many clinically used AP measures and children's reading and spelling outcomes. Nevertheless, they reiterate the importance of evaluating FPT in children with word reading disorders. The findings justify further investigation into the role of this test when diagnosing children with reading or spelling disorders.

MELEXIR: maximum entropy Legendre expanded image reconstruction. A fast and efficient method for the analysis of velocity map imaging or photoelectron imaging data.

A fast and efficient method is presented that recovers a three-dimensional cylindrically symmetric probability distribution from its two-dimensional projection onto a plane parallel to the cylinder axis. This problem arises regularly in the analysis of data from velocity map imaging or photoelectron imaging experiments. The data can be considered the (numerically stable) Abel transform of the unknown probability distribution. The inverse Abel transform belongs to the class of ill-posed problems. In 2014 I presented two methods which solve this problem, termed maximum entropy velocity image reconstruction (MEVIR) and maximum entropy velocity Legendre reconstruction (MEVELER) (Phys. Chem. Chem. Phys., 2014, 16, 570). The maximum entropy concept finds the most probable solution that agrees with the data for a Gaussian or Poissonian particle statistics. The new method presented here also uses the maximum entropy concept and finds a solution in terms of an expansion in Legendre polynomials like MEVELER. The new method dramatically reduces the size of the numerical problem by using an expansion in terms of Legendre polynomials also for the image data. The new method performs at least as well as MEVELER (i.e. down to intensities of ca. 0.01 counts per pixel), but requires only a small fraction of the CPU time and core memory. It should hence be applicable for on-the-fly data analysis during measurements. It can analyze distributions containing higher-order and odd-order Legendre polynomials, whereas MEVELER performed well only for Legendre polynomials of order l = 0 and l = 2. Higher-order and odd-order Legendre polynomials are required in the analysis of multiphoton dissociation reactions, photoelectrons from higher harmonics experiments, or involving circular dichroism.

Chapter 5 - Transcranial magnetic stimulation: Neurophysiological and clinical applications

Transcranial magnetic stimulation (TMS) is a safe and noninvasive means of electrically stimulating the brain by electromagnetic induction. TMS is capable of probing intracortical circuits and modulating cortical activity in humans; as such it has been instrumental to studying the neurophysiology and functional neuroanatomy of the frontal lobes. For example, using TMS to induce "virtual lesions"-transient disruption of function in the targeted brain region-has yielded important insights into the functional organization of the prefrontal cortex (PFC) with respect to working memory, language, and other core cognitive functions. Whereas neuroimaging is typically limited to observing correlations between brain function and behavior, TMS, by interacting with neural circuits, can lead to causal inferences that bridge human, nonhuman primate, and other model system studies. Applied repetitively in trains of stimuli, TMS is also capable of normalizing aberrant patterns of cortical activity in the treatment of neurologic and psychiatric disorders. The earliest and most well-established clinical use of repetitive TMS is in the treatment of medication-resistant depression with high-frequency stimulation of the left dorsolateral PFC. Research efforts to identify other promising clinical applications-such as for stroke and Alzheimer's disease-are rapidly expanding; however, the majority of these indications have yet to have devices cleared by the FDA for on-label use.

The integrative memory model is detailed, but skimps on false memories and development.

The integrative memory model combines five core memory systems with an attributional system. We agree with Bastin et al. that this melding is the most novel aspect of the model. But we await further evidence that the model's substantial complexity informs our understanding of false memories or of the development of recollection and familiarity.

Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors

Energy-efficient microprocessors are essential for a wide range of applications. While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting. In this paper, we perform static reliability analysis of 6T SRAM and discover the variance among different sizing configuration and asymmetric minimum voltage requirements between read and write operations. We leverage this asymmetric property i n near-threshold processors equipped with voltage boosting capability by proposing an opportunistic dual-supply switching scheme with a write aggregation buffer. Our results show that proposed technique improves energy efficiency by more than 21.45% with approximate 10.19% performance speed-up.

OMBM: optimized memory bandwidth management for ensuring QoS and high server utilization

Latency-critical workloads such as web search engines, social networks and finance market applications are sensitive to tail latencies for meeting service level objectives (SLOs). Since unexpected tail latencies are caused by sharing hardware resources with other co-executing workloads, a service provider executes the latency-critical workload alone. Thus, the data center for the latency-critical workloads has exceedingly low hardware resource utilization. For improving hardware resource utilization, the service provider has to co-locate the latency-critical workloads and other batch processing ones. However, because the memory bandwidth cannot be provided in isolation unlike the cores and cache memory, the latency-critical workloads experience poor performance isolation even though the core and cache memory are allocated in isolation to the workloads. To solve this problem, we propose an optimized memory bandwidth management approach for ensuring quality of service (QoS) and high server utilization. By providing isolated shared resources including the memory bandwidth to the latency-critical workload and co-executing batch processing ones, firstly, our proposed approach performs few pre-profilings under the assumption that memory bandwidth contention is the worst with a divide and conquer method. Second, we predict the memory bandwidth to meet the SLO for all queries per seconds (QPSs) based on results of the pre-profilings. Then, our approach allocates the amount of the isolated memory bandwidth that guarantees the SLO to the latency-critical workload and the rest of the memory bandwidth to co-executing batch processing ones. It is experimentally found that our proposed approach can achieve up to 99% SLO assurance and improve the server utilization up to 6.5×.

Fast de Bruijn Graph Compaction in Distributed Memory Environments.

De Bruijn graph based genome assembly has gained popularity as short read sequencers become ubiquitous. A core assembly operation is the generation of unitigs, which are sequences corresponding to chains in the graph. Unitigs are used as building blocks for generating longer sequences in many assemblers, and can facilitate graph compression. Chain compaction, by which unitigs are generated, remains a critical computational task. In this paper, we present a distributed memory parallel algorithm for simultaneous compaction of all chains in bi-directed de Bruijn graphs. The key advantages of our algorithm include bounding the chain compaction run-time to logarithmic number of iterations in the length of the longest chain, and ability to differentiate cycles from chains within logarithmic number of iterations in the length of the longest cycle. Our algorithm scales to thousands of computational cores, and can compact a whole genome de Bruijn graph from a human sequence read set in 7.3 seconds using 7680 distributed memory cores, and in 12.9 minutes using 64 shared memory cores. It is 3.7× and 2.0× faster than equivalent steps in the state-of-the-art tools for distributed and shared memory environments, respectively. An implementation of the algorithm is available at https://github.com/ParBLiSS/bruno.

Political memory, ontological security, and Holocaust remembrance in post-communist Europe

ABSTRACTPost-communist states today are dealing with conflicting sources of ontological insecurity. They are anxious to be perceived as fully European by “core” European states, a status that remains fleeting. Being fully European, however, means sharing in the cosmopolitan European narratives of the twentieth century, perhaps the strongest being the narrative of the Holocaust. Influencing the European Union’s own memory politics and legislation in the process, post-communist states have attempted to resolve these insecurities by undergoing a radical revision of their respective Holocaust remembrance where the memory, symbols, and imagery of the Holocaust become appropriated to represent crimes of communism. By rejecting the cosmopolitan European narrative of the Holocaust, post-communist states have also removed anti-fascist resistance from the core memory of the Holocaust, allowing for a revival and ideological normalisation of contemporary fascist ideological movements. I illustrate the argument with an overview of contemporary Holocaust remembrance practices in the EU’s youngest member, Croatia.

Energy-Efficient Monolithic Three-Dimensional On-Chip Memory Architectures

Memory bandwidth is one of the major performance bottlenecks for chip multiprocessors (CMPs), which continue to integrate an increasing number of cores with the help of Moore's Law. The growing disparity between the CPU clock rate and offchip memory access speed is known as the Memory Wall. This problem has been actively studied in the past two decades. It is addressed by placing memory closer to the processor, such as stacking the memory directly on top of a CMP, thereby significantly reducing the interconnect latency between them. However, previous 3D-stacked memory architectures use through-silicon via (TSV)based three-dimensional (3-D) integration, which bonds multiple dies with TSVs that have diameters in the 1-5 μm range. Unlike TSV-based 3-D integration, monolithic 3-D integration builds device tiers sequentially on a single substrate. Different tiers are connected using monolithic inter-tier vias (MIVs), which have a diameter (around 50 nm) that is the same as that of a local via. Main memory typically consists of DRAM, which is volatile and thus requires periodic refresh to maintain the stored data. This increases both the energy consumption and access latency. However, various nonvolatile RAMs (NVRAMs) have emerged as possible universal memory technologies, which promise low power, fast read access, high density, and nonvolatility. In this paper, we present an efficient memory interface for monolithic 3D-stacked RAM (both DRAM and NVRAMs such as resistive RAM and nanotube RAM). It takes advantage of the tremendous bandwidth made available by MIVs to implement an on-chip memory bus in order to hide the latency of large data transfers. We propose a multientry row-based write buffer to increase the buffer hit rate and reduce the number of memory core accesses. We decouple read and write accesses using extra interconnects available through MIVs to increase memory throughput. We also present an adaptive power-down policy to maintain balance between energy efficiency and performance. Simulation results show that the proposed architecture can achieve both high performance and energy efficiency, and is thus attractive for low-power/high-performance computing.

A Changing-Reference Parasitic-Matching Sensing Circuit for 3-D Vertical RRAM

The 3-D vertical array architecture is considered to be a promising technology for emerging nonvolatile memories. But in 3-D vertical emerging nonvolatile memories, planar parasitic elements, vertical parasitic elements, and the sneak currents of the half-selected memory cells result in the delay of the read operation and read errors. This paper refers to the case of the 3-D vertical resistive switching random access memory (RRAM) technology. A read scheme, the memory core design, and the read path are proposed or analyzed. The factors that affect the read operation are concluded. A changing-reference parasitic-matching sensing circuit is, therefore, proposed. In the proposed circuit, the reference side and the read side share similar sneak currents and read paths. Simulated in a 40-nm CMOS process, the sensing time of 128-Mb 3-D vertical RRAM is 8.54 ns compared to the conventional 34.26 ns. Monte Carlo simulations show a 130.21-ns worst sensing time compared to the conventional 401.95 ns. The read errors are reduced by 100% and 95.31% under the regular and the worst RRAM resistance, respectively.

A Programmable IEEE 1500-Compliant Wrapper for Testing of Word-Oriented Memory Cores

In today’s embedded technology, memories are the universal components. With the onset of the deep-submicron VLSI technology, the density and capacity of the memory are growing. However, providing a cost-effective test solution for these on-chip memories is becoming a challenging task. As memory and other processing cores have been embedded deeply in system chips, the IEEE std 1500 has been suggested to facilitate the test of these core types. Whereas up to now this standard has not presented a definite solution for testing of memory cores, in this paper, we proposed a programmable IEEE 1500-compliant wrapper for applying several Mach algorithms on word-oriented memory cores to reach the desired fault coverage. The proposed wrapper is without finite-state-machine controller, and as a result, the complexity of wrapper circuitry is low and hardware redundancy is acceptable as well.

General build up of basis and matrix in the diagonalization approach. Determination of Kramers configuration state functions

AbstractAlgorithms to build the basis and matrix representation to obtain the Kramers configuration space functions (KCSFs) via diagonalization will be formally generalized to an arbitrary number of unpaired (open shell) fermions. Effective build up of the matrix representation will be outlined (including threading and graphical processing unit parallelism) to subsequently obtain the KCSFs via calling external/numerical library routines for diagonalization. The effective build up of the matrix representation relays on a binary tree search algorithm to allow evaluation the action on a given basis vector. The binary tree search avoids the treatment of zero matrix elements which leads to an exponential acceleration. The implementation ( basis creation, matrix representation, and matrix diagonalization) will be done in an all in core and all at once manner, hence the available core memory sets the physical limits in practical applications. Memory limitations, sparsity of the matrix, general case of n fermions in m spinors, and the application of KCSFs will be put into further perspective.

Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach

Cache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves programmability. However, ccNUMA architectures require sophisticated and expensive cache coherence protocols to enforce correctness during parallel executions, which trigger a significant amount of on- and off-chip traffic in the system. This paper analyses how coherence traffic may be best constrained in a large, real ccNUMA platform comprising 288 cores through the use of a joint hardware/software approach. For several benchmarks, we study coherence traffic in detail under the influence of an added hierarchical cache layer in the directory protocol combined with runtime managed NUMA-aware scheduling and data allocation techniques to make most efficient use of the added hardware. The effectiveness of this joint approach is demonstrated by speedups of 3.14x to 9.97x and coherence traffic reductions of up to 99 percent in comparison to NUMA-oblivious scheduling and data allocation.

Longitudinal accrual of neocortical amyloid burden is associated with microstructural changes of the fornix in cognitively normal adults.

The fornix and parahippocampal cingulum are 2 major limbic tracts in the core memory network of the hippocampus. Although these fiber tracts are known to degrade with Alzheimer's disease (AD), little is known about their vulnerability in the asymptomatic phase of AD. In this longitudinal study of cognitively normal adults, we assessed amyloid-beta (Aβ) plaques using positron emission tomography and white matter microstructure using diffusion tensor imaging. We found that an increase of neocortical Aβ burden over time was associated with an increase of radial diffusivity in the fornix but not in the parahippocampal cingulum. The effect of increasing neocortical Aβ burden on the fornix remained significant after controlling for baseline measures, head motion, global brain atrophy, regional Aβ burden in the hippocampus, or microstructural changes in the global white matter. In addition, microstructural changes in the fornix were not associated with decline of episodic memory or other cognitive abilities. Our findings suggest that microstructural changes in the fornix may be an early sign in the asymptomatic phase of AD.

Massively parallel structural acoustics in Sierra-SD

Sierra-SD is a massively parallel finite element application for structural dynamics and acoustics. Problems on the order of 2 billion degrees of freedom and running on as up to one hundred thousand distributed memory cores have been solved. Sierra-SD offers a wide range of modern acoustic capabilities. Unbounded problems can be solved with either an absorbing boundary condition, infinite elements, or perfectly matched layers. Problems can be solved in the time domain, frequency domain, or as a linear or quadratic eigenvalue problem. Structural acoustics problems can be solved with monolithic strong coupling, or a Multiple Program Multiple Data (MPMD) coupling with the linear and nonlinear structural Sierra applications. One way handoff is available from other applications in the Sandia National Laboratories’ Sierra Mechanics suite, enabling loading through the Lighthill tensor from incompressible fluid codes to calculate far field noise. Real world applications include ship shock loading and vibration of reentry bodies. [Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-NA-0003525.]

Controllable synthesis of SnO2@carbon hollow sphere based on bi-functional metallo-organic molecule for high-performance anode in Li-ion batteries

Constructing hollow structure and nano-sized SnO2 particles are two normal strategies to improve lithium storage performance of SnO2-based electrode. But it is still challengeable to fabricate ultrasmall SnO2 embedded in carbon hollow sphere in a controllable way. Herein, we have synthesized a kind of SnO2@carbon hollow sphere via a confined Friedel-Crafts crosslinking of a novel metal-organic compound (triphenyltin chloride, named Sn-Ph) on the surface of SiO2 template. The as-prepared SnO2@carbon hollow sphere has 10 nm-sized SnO2 particles embedded in amorphous carbon wall. Furthermore, 100, 200 and 400 nm-sized SnO2@carbon hollow spheres can be obtained by regulating the size of SiO2 template. When they are applied in lithium-ion batteries, the carbon structure can act as barriers to protect SnO2 particles from pulverization, and hollow core stores electrolyte and very small SnO2 particles of 10 nm shorten the diffusion distance of lithium ions. Thus, SnO2@carbon hollow sphere presents superior electrochemical performance. The first discharge and charge capacities reach 1378.5 and 507.3 mAh g−1 respectively, and 100 cycles later, its capacity remains 501.2 mAh g−1, indicating a capacity retention of 98.8% (C100th/C2nd).

The Application of Improved Spherical Harmonics Expansion-Based Multilevel Fast Multipole Algorithm in the Solution of Volume-Surface Integral Equation

During the solution of volume-surface integral equation (VSIE), to reduce the core memory requirement of the radiation patterns (RPs) of the basis functions, an improved spherical harmonics expansion-based multilevel fast multipole algorithm (SE-MLFMA) using the mixed-potential representation and the triangle-/tetrahedron-based grouping scheme is applied. Numerical results show that accompanying with a faster speed, the memory requirement of the RPs in the improved SE-MLFMA is several times less than that in the conventional MLFMA without compromising accuracy. A result employing the OpenMP parallelization and vector arithmetic logic unit (VALU) hardware acceleration technique is also shown to illustrate the robustness and scalability of the improved SE-MLFMA method.

Striking a chord with healthy aging: memory system cooperation is related to preserved configural response learning in older adults

Evidence from tasks that primarily tap either hippocampal- or striatal-based memory systems suggests that although these systems often compete for control of behavior, aging is associated with greater cooperation between them. This may stem from altered prefrontal cortex function. Here, we use a configural response task designed to engage both memory systems to test how age affects their interaction with cortical regions including the prefrontal cortex. We found that although older and younger adults learned just as well, older adults showed greater initial activation in cortical networks associated with visuospatial-action mapping and resolving conflict for competing memory representations. Older adults also showed greater functional coupling of the striatum with the left inferior frontal gyrus, in parallel with similar hippocampal coupling to ventral visual regions as young adults. Overall, our results support the proposal that aging is associated with more cooperative memory systems, but we did not find that greater cooperation is associated with less interaction between the prefrontal cortex and core memory system structures during learning.