Testability Measures Research Articles

A New Testability Calculation Method to Guide RTL Test Generation

Current paper presents a unified approach for calculating mixed-level testability measures. In addition, a new method of testability guided RTL Automated Test Pattern Generation (ATPG) for sequential circuits is introduced. The methods and algorithms are based on path tracing procedures on decision diagrams. The previous known methods have been implemented in test synthesis and in guiding gate-level test generation. However, works on application of testability measures to guide high-level test generation are missing. The main aim of this paper is to bridge this gap. Current method is compared to a recent approach known from the test synthesis area. Experiments show that testability measures greatly influence the fault coverage in RT-level test generation with the proposed approach achieving the best results. Similar to earlier works, our research confirms that RT-level fault coverage is in correlation with logic level one.

A Fuzzy Approach for Integrated Measure of Object-Oriented Software Testability

For large software systems, testing phase seems to have profound effect on the overall acceptability and quality of the final product. The success of this activity can be judged by measuring the testability of the software. A good measure for testability can better manage the testing effort and time. Different Object Oriented Metrics are used in measurement of object-oriented testability but none of them is alone sufficient to give an overall reflection of software testability. Thus an integrated measure considering the effect of all these measures is required to well define the testability. The paper combines OO software metric values into a single overall value (called Testability Index) that can be used to calculate the testability of a class. The approach uses fuzzy techniques and concepts (fuzzification of crisp metric values, inference and aggregation, defuzzification of fuzzy output). We include empirical data of testing time of 25 different Java classes, which proves that individual metric values are not sufficient to arrive at the testability of a class and validates the testability index as a good integrated measure for arriving at the testability of the class.

Partial scan design based on circuit state information and functional analysis

Partial scan design is divided into two stages: 1) critical cycle breaking and 2) partial scan flip-flop selection with respect to conflict resolution. A multiple phase partial scan design method is introduced by combining circuit state information and conflict analysis. Critical cycles are broken using a combination of valid circuit state information and conflict analysis. It is quite cost-effective to obtain circuit state information via logic simulation, therefore, circuit state information is iteratively updated after a given number of partial scan flip-flops have been selected. The valid-state-based testability measure may become ineffective to select scan flip-flops when cycles remaining in the circuit are not so influential to testability. The method turns to the conflict resolution process using an intensive conflict-analysis-based testability measure conflict. Sufficient experimental results are presented.

Quantitative evaluation of safety critical software testability based on fault tree analysis and entropy

One of the definitions for testability is the probability whether tests will detect a fault, given that a fault in the program exists. The testability can be estimated from the probability of each statement fault leading to output failure. The probability of the test detecting a fault depends on the probability of individual statement faults appearing as an output failure when a fault exists at a statement. The testability measure of the software has been introduced based on output failure probability and the entropy of the importance of basic statements to the output failure from the software fault tree analysis. The output failure probability and the importance of statements are calculated from software fault tree analysis. The suggested testability measure has been applied to the two modules of the safety system in a nuclear power plant. The proposed testability measure can be used for the selection of output variables or to determine the modules that are more vulnerable to undetected faults.

Testability-analysis driven test-generation of analogue cores

A new definition of the testability transfer factor for circuit components that provides better sensitivity with respect to parametric deviations is presented. New equations for the testability measures in a mixed-signal core are given. Testability analysis is used for test-pattern generation and for consideration of inserting wrapper cells. The simulation results show the effectiveness of the approach.

Nonscan design for testability for synchronous sequential circuits based on conflict resolution

A testability measure called conflict, based on conflict analysis in the process of sequential circuit test generation is introduced to guide nonscan design for testability. The testability measure indicates the number of potential conflicts to occur or the number of clock cycles required to detect a fault. A new testability structure is proposed to insert control points by switching the extra inputs to primary inputs, using whichever extra inputs of all control points can be controlled by independent signals. The proposed design for testability approach is economical in delay, area, and pin overheads. The nonscan design for testability method based on the conflict measure can reduce many potential backtracks and make many hard-to-detect faults easy-to-detect; therefore, it can enhance actual testability of the circuit greatly. Extensive experimental results are presented to demonstrate the effectiveness of the method.

Behavioral-Level DFT via Formal Operator Testability Measures

The focus of this research is on the testability analysis of the operators in the behavioral description prior to synthesis. The controllabilities of the inputs to an operator and the observabilities of the outputs of the operation are computed from the value ranges of the variables that serve as the inputs and outputs. Candidate hard-to-test operations are selected for testability enhancement based on the computed testability measures for all the involved operations in the behavioral description. While value ranges have been applied to compute variable testability measures, this paper addresses computation of the operator testability. Experimental results show that circuits synthesized using our technique exhibit higher testability than variable selection while keeping the area-performance overhead to a minimum.

BIST Analysis of an Embedded Memory Associated Logic

Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other.This paper expands upon past work using a more flexible design rule which allows feed‐forward connections between the data‐path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two‐port memory.The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built‐in self‐test (BIST) designs [2, 11, 17], but may also be suitable for use with other detection probability tools [9, 19], and simulation tools [20].

Communications software design for testability: specification transformations and testability measures

To deal with the increased complexity related to the testing of communications software, we propose the integration and application of finite state machine based specification transformations and testability measures early in the communications software development process. Based on this integration, the testability of a given design is estimated and appropriate specification transformations are defined and applied iteratively to enhance the testability of the product implementation.

A functional-level testability measure for register-level circuits and its estimation

Estimation of circuit testability is an important issue when evaluating the circuit design. A testability measure indicates how easy or difficult it would be to generate tests for the circuit. STAFAN (Statistical Fault Analysis) is a well known gate-level testability analysis program which predicts the fault coverage of a digital circuit under the stuck-at fault model, without actually performing fault simulation. STAFAN offers speed advantage over other testability analysis programs such as SCOAP; further, it explicitly predicts the fault coverage for a given test set, unlike other testability measures which are harder to interpret. We show how a STAFAN-like testability analysis program can be constructed for circuits built out of register-level modules such as adders, multipliers, multiplexers, and busses. Our tool, which we call FSTAFAN, is useful in a testability-driven high-level synthesis environment. We have implemented FSTAFAN on a Sun/SPARC workstation and describe its performance on some register-level circuits.

Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST

This paper proposes a new testability analysis and test-point insertion method at the register transfer level (RTL), assuming a full scan and a pseudorandom built-in self-test design environment. The method is based on analyzing the RTL synchronous specification in synthesizable very high speed integrated circuit hardware descriptive language (VHDL). A VHDL intermediate form representation is first obtained from the VHDL specification and then converted to a directed acyclic graph (DAG) that represents all data dependencies and flow of control in the VHDL specification. Testability measures (TMs) are computed on this graph. The considered TMs are controllability and observability for each bit of each signal/variable that is declared or may be implied in the VHDL specification. Internal signals of functional modules (FMs) such as adders and comparators are also analyzed to compute their controllability and observability values. The internal signals are obtained by decomposing at the RTL large FMs into smaller ones. The calculation of TMs is carried out at a functional level rather than the gate level, to reduce or eliminate errors introduced by ignoring reconvergent fanouts in the gate network, and to reduce the complexity of the DAG construction. Based on the controllability/observability values, test-point insertion is performed to improve the testability for each bit of each signal/variable. This insertion is carried out in the original VHDL specification and thus becomes a part of it unlike in other existing methods. This allows full application of RTL synthesis optimization on both the functional and the test logic concurrently within the designer constraints such as area and delay. A number of benchmark circuits were used to show the applicability and the effectiveness of our method in terms of the resulting testability, area, and delay.

Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections

Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other. This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory. The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs, but may also be suitable for use with other detection probability tools and simulation tools.

An approach to test synthesis from higher level

Consideration to testability from the early stage in the design process is one of the most effective ways to reduce testing cost. This paper addresses approaches to high-level test synthesis, especially for testability targeting non-scan design. We give a brief survey of such approaches and introduce our approach. We present a high-level test synthesis method that considers testability of generated register-transfer level (RTL) data paths, as well as their area and performance. This work is mainly different from the related works in the following two points. (1) Our target is weak testability which is a testability measure of RTL data paths whose target is non-scan design for sequential automatic test pattern generation. (2) We take testability into consideration from the beginning of high-level synthesis. We consider testability during both scheduling and binding, while most related works (except for a few) consider testability during binding after scheduling. We propose a heuristic synthesis algorithm that generates a weakly testable data path while minimizing area under a performance constraint.

Efficient test-point selection for scan-based BIST

We propose a test point selection algorithm for scan-based built-in self-test (BIST). Under a pseudorandom BIST scheme, the objectives are (1) achieving a high random pattern fault coverage, (2) reducing the computational complexity, and (3) minimizing the performance as well as the area overheads due to the insertion of test points. The proposed algorithm uses a hybrid approach to accurately estimate the profit of the global random testability of a test point candidate. The timing information is fully integrated into the algorithm to access the performance impact of a test point. In addition, a symbolic procedure is proposed to compute testability measures more efficiently for circuits with feedbacks so that the test point selection algorithm can be applied to partial-scan circuits. The experimental results show the proposed algorithm achieves higher fault coverages than previous approaches,with a significant reduction of computational complexity. By taking timing information into consideration, the performance degradation can he minimized with possibly more test points.

SCOAP‐based Testability Analysis from Hierarchical Netlists

Circuits of VLSI complexity are designed using modules such as adders, multipliers, register files, memories, multiplexers, and busses. During the high‐level design of such a circuit, it is important to be able to consider several alternative designs and compare them on counts of area, performance, and testability. While tools exist for area and delay estimation of module‐level circuits, most of the testability analysis tools work on gate‐level descriptions of the circuit. Thus an expensive operation of flattening the circuit becomes necessary to carry out testability analysis. In this paper, we describe a time and space‐efficient technique for evaluating the well known SCOAP testability measure of a circuit from its hierarchical description with two or more levels of hierarchy. We introduce the notion of SCOAP Expression Diagrams for functional modules, which can be precomputed and stored as part of the module data base. Our hierarchical testability analysis program, HISCOAP, reads the SCOAP expression diagrams for the modules used in the circuit, and evaluates the SCOAP measure in a systematic manner. The program has been implemented on a Sun/SPARC workstation, and we present results on several benchmark circuits, both combinational and sequential. We show that our algorithm also has a straightforward parallel realization.

Software testability measurement for intelligent assertion placement

Voas defines software testability as the degree to which software reveals faults during testing. This software characteristic is important when determining how to best apply verification techniques and build quality assurance plans. When testability is low, testers often want advice on how to increase it. In this paper, we describe the use of testability measures (using VoasOs definition) for intelligent assertion placement. Software assertions are one relatively simple trick for improving testability. VoasOs perspective on what software testability is has been implemented via three algorithms that together comprise a technique termed Osensitivity analysisO. Sensitivity analysis analyses how likely a test scheme is to (1) propagate data state errors to the output space, (2) cause internal states to become corrupted when faults are exercised, and (3) exercise the code. By knowing where faults appear likely to hide from a particular test scheme, we have insight into where internal tests (assertions) are particularly beneficial. This paper explores using the one sensitivity analysis algorithm that measures propagation as a heuristic for where and how to inject software assertions.

Nonscan design-for-testability techniques using RT-level design information

This paper presents nonscan design-for-testability (DFT) techniques applicable to register-transfer (RT)-level data path circuits. Knowledge of high-level design information, in the form of the RT-level structure, as well as the functions of the RT-level components is utilized to develop effective nonscan DFT techniques. Instead of conventional techniques of selecting flip-flops (FF's) to make systems controllable/observable, execution units (EXU's) are selected using the EXU S-graph introduced in this paper. Controllability/observability points can be implemented using register files and constants. We introduce the notion of k-level controllable and observable loops and demonstrate that it suffices to make all the loops k-level controllable/observable, k>0, to achieve very high test efficiency. The new testability measure eliminates the need by traditional DFT techniques to make all loops directly (zero-level) controllable/observable, reducing significantly the hardware overhead required and making the nonscan DFT approach feasible and effective. We discuss ways of avoiding the formation of reconvergent regions while adding test points to make loops k-level controllable/observable. We introduce dual points, which utilize the different controllability/observability levels of loops, to make one loop controllable while making another loop observable. We present efficient algorithms to add the minimal hardware possible to make all loops in the data path k-level controllable/observable, without the use of scan FF's. The nonscan DFT techniques were applied to several data path circuits. The experimental results demonstrate the effectiveness of the k-level testability measure, and the use of distributed and dual points, to generate easily testable data paths with reduced hardware overhead. The hardware overhead and the test application time required for the nonscan designs are significantly lower than for the partial scan designs. Most significantly, the experimental results demonstrate the ability of the RT-level DFT techniques to produce nonscan testable data paths, which can be tested at-speed.

Design for Testability Using State Distances

The average distance between states is proposed as a new testability measure for finite state machines (FSMs). Also proposed is the concept of center state to reduce distances in FSMs. This test function embedding technique has been shown to improve the testability of sequential circuits with minimal overhead. An overview of several design-for-testability (DFT) and synthesis-for-testability (SFT) methods for sequential circuits will also be given in this paper. Experimental results have shown that the DFT approach is more advantageous than the SFT approach to implement our test function. The contribution of this paper is to analyze the trade-offs between several aspects of DFT and SFT techniques.

On the use of testability measures for dependability assessment

Program "testability" is informally, the probability that a program will fail under test if it contains at least one fault. When a dependability assessment has to be derived from the observation of a series of failure free test executions (a common need for software subject to "ultra high reliability" requirements), measures of testability can-in theory-be used to draw inferences on program correctness. We rigorously investigate the concept of testability and its use in dependability assessment, criticizing, and improving on, previously published results. We give a general descriptive model of program execution and testing, on which the different measures of interest can be defined. We propose a more precise definition of program testability than that given by other authors, and discuss how to increase testing effectiveness without impairing program reliability in operation. We then study the mathematics of using testability to estimate, from test results: the probability of program correctness and the probability of failures. To derive the probability of program correctness, we use a Bayesian inference procedure and argue that this is more useful than deriving a classical "confidence level". We also show that a high testability is not an unconditionally desirable property for a program. In particular, for programs complex enough that they are unlikely to be completely fault free, increasing testability may produce a program which will be less trustworthy, even after successful testing.

On Generating Optimal Signal Probabilities for Random Tests: A Genetic Approach

Genetic Algorithms are robust search and optimization techniques. A Genetic Algorithm based approach for determining the optimal input distributions for generating random test vectors is proposed in the paper. A cost function based on the COP testability measure for determining the efficacy of the input distributions is discussed. A brief overview of Genetic Algorithms (GAs) and the specific details of our implementation are described. Experimental results based on ISCAS-85 benchmark circuits are presented. The performance of our GAbased approach is compared with previous results. While the GA generates more efficient input distributions than the previous methods which are based on gradient descent search, the overheads of the GA in computing the input distributions are larger.To account for the relatively quick convergence of the gradient descent methods, we analyze the landscape of the COP-based cost function. We prove that the cost function is unimodal in the search space. This feature makes the cost function amenable to optimization by gradient-descent techniques as compared to random search methods such as Genetic Algorithms.