Manufacturing Yield Research Articles

A sensor data mining process for identifying root causes associated with low yield in semiconductor manufacturing

PurposeThe purpose of this paper is to identify the root cause of low yield problems in the semiconductor manufacturing process using sensor data continuously collected from manufacturing equipment and describe the process environment in the equipment.Design/methodology/approachThis paper proposes a sensor data mining process based on the sequential modeling of random forests for low yield diagnosis. The process consists of sequential steps: problem definition, data preparation, excursion time and critical sensor identification, data visualization and root cause identification.FindingsA case study is conducted using real-world data collected from a semiconductor manufacturer in South Korea to demonstrate the effectiveness of the diagnosis process. The proposed model successfully identified the excursion time and critical sensors previously identified by domain engineers using costly manual examination.Originality/valueThe proposed procedure helps domain engineers narrow down the excursion time and critical sensors from the massive sensor data. The procedure's outcome is highly interpretable, informative and easy to visualize.

DRDebug: Automated Design Rule Debugging

Design rule checking (DRC) is an important step in the physical design flow that checks if a design meets the manufacturing constraints or design rules imposed by the process technology. It allows the foundry to ensure high acceptable manufacturing yield. Design rule verification is one of the most challenging steps because of the sheer size of the rule decks and the lack of standardization among these design rule manuals (DRMs). One way of efficiently discovering missed rule checks is by comparing the rule deck with that of another mature or well-established process. In this work, we develop two complementary techniques for comparing process design rule decks and automatically establishing a one-to-one correspondence between rules from two different process design kits (PDKs). The first approach, random layout generation (RLG), creates random layouts of different shapes and sizes. The generated layout is checked using both rule decks. The rules are then matched based on the violations generated. The second approach, based on rule language processing (RLP), matches rules based on the similarity between rule commands. Rules are directly matched based on the layer names and keywords present in the DRC commands. The two approaches are complementary and together they can correctly match more than 80% of the rules in two DRMs.

Screen Printed Reflective Electrochromic Displays for Paper and Other Opaque Substrates.

Paper electronics is a viable alternative to traditional electronics, leading to more sustainable electronics. Many challenges still require solutions before paper electronics become mainstream. Here, we present a solution to enable the manufacturing of reflective all-printed organic electrochromic displays (OECDs) on paper substrates; devices that are usually printed on transparent substrates, for example, plastics. In order to operate on opaque paper substrates, an architecture for reversely printed OECDs (rOECDs) is developed. In this architecture, the electrochromic layer is printed as the last functional layer and can therefore be viewed from the print side. Square shaped 1 cm2 rOECDs are successfully screen printed on paper, with a high manufacturing yield exceeding 99%, switching times <3 s and high color contrast (ΔE* > 27). Approximately 60% of the color is retained after 15 min in open-circuit mode. Compared to the conventional screen printed OECD architectures, the rOECDs recover approximately three times faster from storage in a dry environment, which is particularly important in systems where storage in low humidity atmosphere is required, for example, in many biosensing applications. Finally, a more complex rOECD with 9 individually addressable segments is successfully screen printed and demonstrated.

High-Yield Production of Extracellular Vesicle Subpopulations with Constant Quality Using Batch-Refeed Cultures.

The conventional manufacturing of extracellular vesicles (EVs) is characterized by low yields and batch-to-batch variability, hampering fundamental research on EVs and their practical applications. Perfusion operations have huge potential to address these limitations and increase the productivity and quality of EVs. In this study, perfusion cultures are simulated with batch-refeed systems and their productivity is compared with that achieved using batch cultures. It is shown that a shift from batch to batch-refeed system can increase the space-time yields of a target EV subpopulation characterized by CD81 and CD63 biomarkers by threefold. Moreover, it is demonstrated that the method facilitates the consistent production of the target EVs from cells maintained under constant conditions for 13days. These results indicate that the use of perfusion cultures is a promising strategy to increase the manufacturing yield of EVs and control the production of specific EV subpopulations with constant quality attributes, thereby improving reproducibility.

Research on self-supporting T-shaped gate structure of GaN-based HEMT devices

A self-supporting T-shaped gate (SST-gate) GaN device and process method using electron beam lithography are proposed. An AlGaN/GaN high-electron-mobility transistor (HEMT) device with a gate length of 100 nm is fabricated by this method. The current gain cutoff frequency (f T) is 60 GHz, and the maximum oscillation frequency (f max) is 104 GHz. The current collapse has improved by 13% at static bias of (V GSQ, V DSQ) = (–8 V, 10 V), and gate manufacturing yield has improved by 17% compared with the traditional floating T-shaped gate (FT-gate) device.

The Impact of Crude Oil Price Changes in The Yield and Fluctuation of Manufacturing and Transportation Industries

Given that Russia was one of the largest oil exporters, has left the oil market unstable as the war between Russia and Ukraine intensifies. This report, studies the effect of the oil shock on returns and volatility of manufacturing and transportation industries of the US, to understand the relationship, lag, and intensity between these industries in conjunction with the Crude oil price in the international market. By using Time-Series data collected from NYME and constructing a VAR model, an ARIMA-GARCH model has been formulated using likelihood ratio lag of 12. The report finds out no significant relationship between the oil shock triggered by Russian-Ukrainian war on the US transportation and manufacturing industry. The Yield and Volatility of these two industries have not been driven due to exogenous factors, crude oil price. There is a possibility that the impact is lagged and hasn’t occurred yet or is too statistically small that it is hard to be captured by the model. The impact of exogenous shocks may be lagged much higher until it destabilizes these sectors. Government must set countermeasures based on lag effect as the impact is indirect.

An arrayed CRISPR screen reveals Myc depletion to increase productivity of difficult-to-express complex antibodies in CHO cells.

Complex therapeutic antibody formats, such as bispecifics (bsAbs) or cytokine fusions, may provide new treatment options in diverse disease areas. However, the manufacturing yield of these complex antibody formats in Chinese Hamster Ovary (CHO) cells is lower than monoclonal antibodies due to challenges in expression levels and potential formation of side products. To overcome these limitations, we performed a clustered regularly interspaced short palindromic repeats (CRISPR)/CRISPR associated protein 9 (Cas9)-based knockout (KO) arrayed screening of 187 target genes in two CHO clones expressing two different complex antibody formats in a production-mimicking set-up. Our findings revealed that Myc depletion drastically increased product expression (>40%) by enhancing cell-specific productivity. The Myc-depleted cells displayed decreased cell densities together with substantially higher product titers in industrially-relevant bioprocesses using ambr15 and ambr250 bioreactors. Similar effects were observed across multiple different clones, each expressing a distinct complex antibody format. Our findings reinforce the mutually exclusive relationship between growth and production phenotypes and provide a targeted cell engineering approach to impact productivity without impairing product quality. We anticipate that CRISPR/Cas9-based CHO host cell engineering will transform our ability to increase manufacturing yield of high-value complex biotherapeutics.

Transfection innovation for large-scale AAV &amp; LV: considerations for process development through commercial manufacturing

GMP-compliant nucleic acid delivery to HEK293 cells is often a critical first step in the manufacture of advanced therapies utilizing recombinant adeno-associated virus (AAV) or lentivirus (LV) to facilitate delivery of a therapeutic transgene to patients. Accordingly, the need for safe and reproducible large-scale viral vector manufacture processes has never been greater. Mirus Bio has developed a fully synthetic, innovative transfection formulation to enable higher titer AAV and LV generation and reduce the cost of therapeutic development and manufacture to bring more life-changing doses to patients sooner.&#160;Initial viral vector process development efforts tended towards adherent cell culture and transient transfection. These were for rare indications with low demand, and lower doses were needed. Now, the industry is undergoing rapid manufacturing development to support the upcoming demand for higher prevalence and/or dosage diseases. As a result, the size and yield in manufacturing have increased, as well as the need for lower costs to enable economic manufacture.

Timing-Aware Fill Insertions With Design-Rule and Density Constraints

Metal fill insertion has become an essential step in reducing dielectric thickness variation and improving pattern uniformity, which is important in mitigating process variations, thereby achieving better manufacturing yield. However, metal fills could induce coupling capacitance, which is not often considered in existing works that typically focus more on pattern density uniformity, incurring significant problems in timing closure. However, it is a great challenge to consider three types of capacitances (i.e., area, fringe, and lateral capacitances) with design rules and density constraints at the fill insertion stage simultaneously. This article presents an efficient timing-aware fill insertion algorithm for minimizing the total capacitance and fill amount, considering the density constraints. First, we present an initial metal fill insertion and design-rule-aware legalization to obtain an initial fill insertion solution quickly. Second, from critical conductors to powers/grounds in a circuit, we divide conductors into different equivalent paths and then construct a capacitance graph to reduce the capacitance of each equivalent path globally. Third, we propose a density-aware coupling capacitance optimization method and a fast Monte Carlo-based fill selection to further reduce the coupling capacitance between any pair of conductors. Finally, we present a density-aware fill deletion method to reduce the fill amount. We evaluate the performance of our algorithm on the benchmarks of the 2018 CAD Contest at ICCAD and its official contest evaluator. Compared with the first-place team of the contest and the state-of-the-artwork, experimental results show that our algorithm achieves the lowest total capacitance and the least fill amount in a comparable runtime.

Mapping the flat glass value-chain: a material flow analysis and energy balance of UK production

AbstractGlass is one of the UK’s eight energy-intensive industries. As such, it is under scrutiny to decouple growth in production from greenhouse gas (GHG) emissions. Recycled glass, also known as cullet, requires less energy to melt than primary raw materials in new glass production. The use of cullet thus reduces the energy intensity per unit of output whilst also reducing demand for primary material resources. However, efficient systems for flat glass collection are yet to be established in the UK, resulting in a limited supply of cullet available for the flat glass market and missed environmental opportunities. This study identifies the existing supply-chain inefficiencies in the UK glass industry in three stages. Firstly, the mass flows of materials within the three main glass sectors: container glass, flat glass and glass wool, are mapped from natural resource through to primary application and subsequent end-of-life management based on a reference year of annual production figures. The map is presented in the form of a “Sankey” diagram which draws attention to several opportunities for increasing resource efficiency; namely in the stark contrast in glass collection rates between the flat and container glass industry. Using the data collected on the annual mass flows of materials in the UK flat glass sub-sector, the energy (MJ) and GHG emission (CO2-eq) saving potential of enhanced end-of-life collection methods are assessed, based on three alternative recovery scenarios. These scenarios consider the use of alternative distributions of recovered flat glass cullet in the three primary glass sub-sectors. The emission savings resulting from each recovery scenario are evaluated, based on the estimated tonnage yield of finished flat glass products. It is shown that together with improved manufacturing yield, the reutilization of end-of-life flat glass as cullet in new production could reduce the annual emissions of the UK flat glass value-chain by up to 18.6%. Finally we review the existing barriers to recycling different glass types based on acceptability criteria and available take-back infrastructure, and thus find that the advancement of improved recycling rates will rely on establishing the business opportunity and/or supporting policy for developing efficient systems for flat glass collection.

Abstract 15 Safety of DUOC-01, Intrathecal Cord Blood-Derived Cellular Therapy, as an Adjunct to Allogeneic Cord Blood Transplantation in Children with Inherited Metabolic Diseases

IntroductionUnrelated donor umbilical cord blood transplantation (CBT) improves function and extends life in children with certain inherited metabolic diseases (IMDs); however, progressive neurologic decline often occurs during the few months post-CBT prior to donor engraftment in the brain, causing residual, irreversible impairments. We previously described donor engraftment in the brain after CBT and developed DUOC-01, a monocyte-derived CB cell product, to attempt to accelerate donor cell delivery to the brain.ObjectiveThe objective of this study was to determine manufacturing feasibility and safety of intrathecal DUOC-01 in a phase I study in children with IMDs undergoing CBT after myeloablative cytoreduction (busulfan/cyclophosphamide/anti-thymocyte globulin).MethodsDUOC-01 was manufactured in adherent cell culture in a GMP lab over 21 days with a target dose of ≤100 × 105 cells. When cell dose permitted, 80% of the CB unit was used for transplant and 20% of the same unit was used to manufacture DUOC-01. Otherwise, DUOC-01 was manufactured from a unique CB unit. On day ≥+28 post-CBT, if there was evidence of hematopoietic engraftment without severe graft versus host disease or morbidity, DUOC-01 cells were harvested and administered intrathecally. Safety was monitored via neurologic exams, neuroimaging, and CSF studies.ResultsForty patients (aged 0-15 years) underwent CBT, 37 engrafted with donor cells. Median infused total nucleated cell count was 6.5 × 107/kg (range 2.9-33.1 × 107/kg); median time to neutrophil engraftment was 20 days (range 13-46 days). Ten patients did not receive DUOC-01 cells for the following reasons: engraftment failure (3), transplant-related morbidity (4), and low manufacturing yield (3). Thirty patients received 0.2-100 × 105 DUOC-01 cells intrathecally for a median of 31 days (range 27-77 days) post-CBT (19 with the same CB donor and 11 with a unique CB donor). Two patients developed transient fever and hypotension hours after unique-donor DUOC-01, consistent with an inflammatory response. Hydrocortisone (HC) was added to the final formulation, and post-validation, seven additional patients received unique-donor DUOC-01+HC without incident. No other DUOC-01-related serious adverse events occurred.DiscussionDUOC-01 is a CB-derived product intended to accelerate donor cell delivery to the brain of children with IMDs undergoing CBT. Intrathecal DUOC-01 administration is well-tolerated post-CBT from the same donor and, with the addition of HC, also from a unique donor. Escalating DUOC doses are being tested for safety and exploration of potential efficacy in a phase Ia trial of adults with multiple sclerosis.

Automation of optimal metal density filling for deep sub micron technology designs

The locally adopted technique of Chemical-mechanical polishing (CMP) along with various other steps taken in design for manufacturing procedures employed for the fabrication of nano ICs, results in adverse impact on interconnecting wire parameters as well as device features. In order to enhance the manufacturability yield, performance predictability and also for getting the uniform chip layout a propos to prescribed density criteria; dummy fill insertion into layout is a mandatory step of contemporary manufacturing process. Full chip dummy fill is an iterative process which is time consuming and exponentially increases size of GDS. This paper discusses an algorithm which suggests a more sophisticated dummy-fill technique such that it optimizes the total number of metal fill by keeping a tradeoff between the fill requirement and need of design. The proposed algorithm will iterate automatically till a target density is reached with marginal increase to the size of the GDS. MENTOR GRAPHICS SVRF Calibre commands are used to develop the algorithm. PERL scripting is used to run the job automatically. The simulated experimental results points out that the proposed method renders a more balanced metal density distribution while using lesser dummy metal features. Besides this it shows an acceptable timing overhead.

Organic electrochemical transistors manufactured by laser ablation and screen printing

The dimensions of the material serving as the channel in organic electrochemical transistors (OECTs) are important for the overall switching performance. Here, a laser ablation step is included in the OECT manufacturing process, in an attempt to shorten the channel length of the OECT. The source and drain electrodes are formed by laser ablation of a previously screen printed carbon-based rectangle, which in this study resulted in an average channel length equal to 25 µm. All other processing steps rely on screen printing, allowing for large-area manufacturing of OECTs and OECT-based circuits on flexible substrates. This approach results in a manufacturing yield of 89%; 178 out of a total of 200 OECTs exhibited an ON/OFF ratio exceeding 1000 with a statistical mean value of 28 000 and reproducible switching performance. OECT-based circuits, here demonstrated by a logic inverter, provide a reasonably high voltage gain of 12. The results thus demonstrate another reliable OECT manufacturing process, based on the combination of laser ablation and screen printing.

Control Of Particle Adhesion On InGaAs Surface In Basic Solution By The Addition Of Cationic Surfactant

InGaAs has a higher electron mobility and saturation velocity than Si, making it a potential candidate for a channel material of next generation metal-oxide-semiconductor devices. To introduce InGaAs into semiconductor devices as a channel material, a series of chemical mechanical polishing (CMP) processes are required after InGaAs deposition processes [1]. However, silica particles may remain on the InGaAs surface after CMP processes, and the particles reduce the yield of semiconductor manufacturing. In order to remove silica particles from the InGaAs surface, post-CMP cleaning process is required. However, the behavior of silica particles on the InGaAs surface has not been extensively investigated yet. In this study, the behavior of silica particles on the InGaAs surface in ammonium hydroxide (NH4OH)–hydrogen peroxide (H2O2)–H2O mixture (APM) solution containing cationic surfactant was investigated. Also, the interaction forces between the silica particle and the InGaAs surface in the APM solution with different concentrations of hexadecyltrimethylammonium bromide (CTAB) were examined. To investigate the behavior of silica particles on the InGaAs surface in the APM solution, silica particles were intentionally contaminated on the InGaAs surface by dipping the InGaAs in the solution where silica particles were dispersed. CTAB was added to the APM solution at the concentrations of 10-4–10-2 M to modify the interaction forces between the silica particle and the InGaAs. To estimate the interaction forces (van der Waals force, acid–base force and electrostatic force) between the silica particle and the InGaAs surface in the solution, the surface properties of InGaAs and silica particle, such as zeta potential, surface energy components, acid–base energy constant and Hamaker constant, were examined from the contact angles and surface charges. As shown in Fig. 1, the number of particles per InGaAs surface area was observed to be 4.5×105 particles/mm2 after dipping the InGaAs in particle-dispersed APM solution. When 10-4 M CTAB was added to the APM solution, the number of particles per InGaAs surface area slightly increased, but it decreased the concentration of CTAB in the APM solution increased to 10-2 M. It is believed that the addition of CTAB to the APM solution changes the interaction force between silica particles and the InGaAs surface, thereby determining the adhesion behavior of silica particle to the InGaAs surface. The interaction force between the silica particle and the InGaAs surface in the APM solution is obtained by sum of the attraction (van der Waals) and the repulsions (acid–base and electrostatic). Since van der Waals force, acid–base force and electrostatic force were proportional to Hamaker constant, acid–base energy constant and zeta potential, respectively, the change of each force was estimated from the change of surface property. Compared to their surface properties in the APM solution without CTAB, Hamaker constant, acid–base energy constant and zeta potential were reduced by the addition of 10-4 M CTAB. The results suggest that van der Waals force, acid–base force and electrostatic force decrease in the APM solution with the addition of 10-4 M CTAB. However, since the decrement in acid–base force and electrostatic force was larger than that in van der Waals force, the attraction was dominant over the repulsion in the 10-4 M CTAB-added APM solution. Therefore, the adhesion of silica particles in the APM solution with the CTAB addition of 10-4 M may be facilitated by attraction force. When 10-2 M CTAB was added to the APM solution, Hamaker constant, acid–base energy constant and zeta potential increased, indicating that van der Waals, acid–base and electrostatic forces are enhanced. However, since the increments in acid–base force and electrostatic force were larger than that in van der Waals force, the repulsion was dominant over the attraction in the 10-2 M CTAB-added APM solution. It is suggested that the adhesion of silica particles to the InGaAs surface is suppressed by repulsion force. From the estimation for the change in the interaction forces, it is proposed that the APM solution with the addition of 10-2 M CTAB capable of suppressing the adhesion of silica particles may be a potential candidate for the InGaAs surface cleaning. Reference [1] E. E. Remsen, S. Anjur, D. Boldridge, M. Kamiti, S. Li, T. Johns, C. Dowell, J. Kasthurirangan, P. Feeney, J. Electrochem. Soc., 153, G453–G461 (2006). Figure 1

Redefining Monitoring Rules for Intelligent Fault Detection and Classification via CNN Transfer Learning for Smart Manufacturing

Fault detection and classification has been employed to enhance yield and product quality for smart semiconductor manufacturing. For early detection of abnormal events that cause defects, the status variables identification data collected by the sensors embedded in advanced machines can be analyzed to derive the actions for advanced process control and advanced equipment control. However, the validity and effectiveness of fault detection and classification technologies may highly depend on domain knowledge and experience of the process engineers who should redefine the monitoring rules quickly when new process excursion occurred especially when ramping up new technologies and products. Motivated by realistic needs, this study aims to propose a novel strategy to empower intelligent fault detection and classification that employed convolutional neural network to analyze the feature SVID data and determine the conditions of the wafers, while shorten the cycle time for self-learning from domain knowledge and redefining new monitoring rules for fault classification in real time. This approach is validated with an empirical study in a leading semiconductor manufacturing company in Taiwan. The results have demonstrated the practical viability of the developed solution.

Study, implementation and testing of radiation tolerant design for testability solutions for CMS OT FE ASICs

The MPA and SSA development is approaching the production phase with an approximate volume of more than 200k ASICs, corresponding to 1200 wafers. The limited manufacturing yield requires testing strategies able to identify defective units and guarantee the correct functionality of the tracker modules. This contribution presents innovative methods to replace the currently used functional tests for the digital part of the ASICs, showing limited testing accuracy and long testing time. The proposed solution exploits the concept of structural test and new testing algorithms such as Automatic Test Pattern Generation (ATPG) for general digital logic and March for memory elements. Design for Testability (DFT) hardware is integrated on chip to test SRAM memories, peripheral logic and MPA pixel array, providing internal control and observation points for the implementation of the those algorithms. Particular attention is given to power increase, timing and placement impact as well as radiation tolerance of the introduced circuitry, which must be fully transparent during the normal operation of the chip. A faster and more accurate testing approach is presented, from design methodology to implementation choices and silicon results, for a reliable and cost effective testing procedure.

Self-attenuating adenovirus enables production of recombinant adeno-associated virus for high manufacturing yield without contamination

Recombinant adeno-associated virus (rAAV) shows great promise for gene therapy, however scalability, yield and quality remain significant issues. Here we describe an rAAV manufacturing strategy using a ‘helper’ adenovirus that self-inhibits its major late promoter (MLP) to truncate its own replication. Inserting a tetracycline repressor (TetR) binding site into the MLP and encoding the TetR under its transcriptional control allowed normal adenovirus replication in the presence of doxycycline but only genome amplification and early gene expression (the ‘helper’ functions) in its absence. Using this self-inhibiting adenovirus we demonstrate delivery of adenoviral helper functions, AAV rep and cap genes, and the rAAV genome to yield up to 30-fold more rAAV vectors compared to the helper-free plasmid approach and significant improvements in particle infectivity for a range of serotypes. This system allows significant improvements in the production of serotypes rAAV2, rAAV6, rAAV8 and rAAV9, and enables propagation of existing rAAV without transfection, a process that improves batch quality by depleting reverse packaged DNA contaminants. We propose this as a high-yielding, contaminant-free system suitable for scalable rAAV manufacture.

Lithography Hotspot Detection Method Based on Transfer Learning Using Pre-Trained Deep Convolutional Neural Network

As the designed feature size of integrated circuits (ICs) continues to shrink, the lithographic printability of the design has become one of the important issues in IC design and manufacturing. There are patterns that cause lithography hotspots in the IC layout. Hotspot detection affects the turn-around time and the yield of IC manufacturing. The precision and F1 score of available machine-learning-based hotspot-detection methods are still insufficient. In this paper, a lithography hotspot detection method based on transfer learning using pre-trained deep convolutional neural network is proposed. The proposed method uses the VGG13 network trained with the ImageNet dataset as the pre-trained model. In order to obtain a model suitable for hotspot detection, the pre-trained model is trained with some down-sampled layout pattern data and takes cross entropy as the loss function. ICCAD 2012 benchmark suite is used for model training and model verification. The proposed method performs well in accuracy, recall, precision, and F1 score. There is significant improvement in the precision and F1 score. The results show that updating the weights of partial convolutional layers has little effect on the results of this method.

レーザー散乱光の多方向偏光検出によるSiウエハ上微小欠陥の高精度凹凸分類

Wafer defect inspection is essential to control quality and yield of semiconductor device manufacturing. Wafer surface inspection tools with laser scattering method are employed for high-throughput and high-sensitivity inspection of defects with sizes of about several microns to sub-20 nm. In addition to detecting defects with various shapes and sizes, classification of defect types is required. Classification by multi-directional scattered light detection is known, which captures defect scattered light at multiple scatter direction and compares the intensities in different angles. We simulate concave-convex defect classification with multi-directional detection by analyzing polarized angular scattering distributions, obtained with discrete dipole approximation method, from defects that differ in shapes, sizes, and materials. As a result of classification performance evaluation with support vector machine classifier, when using only unpolarized light intensities, the maximum defect diameter that is accurately classified is limited to from 0.62 times as much as the illumination wavelength. By using both +45 and -45 deg linearly polarized light intensities, the limit is extended to from 1.47 times as much as the wavelength.

A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability

The power consumption of modern highly complex chips during scan test is significantly higher than the power consumed during functional mode. This leads to substantial heat dissipation, excessive IR drop, and unrealistic timing failures of the integrated circuits (ICs) under test. In this brief, a ByPassable Scan Data Retention Flip-Flop (BPS-DRFF) is proposed for low-power IC test. The proposed flip-flop contains two secondary latches. The output of the “function” secondary latch goes to the following combinational circuits, while the other “shadow” secondary latch is used to shift test vectors during scan test. By gating the output of the function secondary latch, the redundant switching activity in the combinational circuits is eliminated during scan shift, thereby reducing the test power consumption significantly. The suppressed switching activity also leads to lower IR drop across the chip, increasing the chip manufacturing yield. Furthermore, the shadow latch is reused for data retention in the sleep mode while performing power gating, thereby alleviating the area cost of the shadow latch. The proposed BPS-DRFF also eases the hold time sign-off in the test mode due to the elongated clock-to-Q contamination delay that is brought in by the shadow latch. The proposed design is applied to an AES-128 crypto core in a UMC 55-nm low power CMOS technology. Experiment results show that 68.5% power is saved during scan test with the proposed BPS-DRFF, compared to the standard scan retention flip-flop.