Magnitude Of Common-mode Voltage Research Articles

A novel partitioned hybrid PWM strategy to reduce the common‐mode voltage in three‐level neutral‐point‐clamped inverters

AbstractTo reduce the common‐mode voltage (CMV) generated during the operation of the three‐level neutral‐point‐clamped (3L‐NPC) inverters, this study proposes a partitioned hybrid pulse width modulation (PHPWM) strategy. In this strategy, the three‐level vector space is divided into high‐modulation region and low‐modulation region according to the modulation index. The reference voltage is synthesized by only medium and small basic vectors with low CMV magnitude. In the low‐modulation region, a clamped level method and a five‐segment asymmetric switching sequence are adopted to reduce the loss and current distortion. In the high‐modulation region, it repartitions the vector space by medium vectors and takes a seven‐segment asymmetric switching sequence to reduce the loss and distortion slightly. The simulation results for the PHPWM strategy and the other two strategies are compared to demonstrate the superiority of PHPWM. The experiment results verify its feasibility. The results indicate that the PHPWM is capable of restricting the CMV within 1/6 of the DC‐linkage voltage and it can make a balance between efficiency and output total harmonic distortion.

Mitigation of common mode voltage in ultra sparse matrix converters using auxiliary shoot‐through switches for wind energy systems

SummaryThis paper targets to minimize the peak common mode voltage (CMV) in ultra sparse matrix converters (USMC) by applying new zero vectors for the space vector modulation technique (SVM). Conventional zero vectors in the SVM raise the peak CMV by 42.23%. An increased magnitude of CMV is associated with the occurrence of leakage current, hence resulting in insulation degradation. So, the reduction of peak CMV is necessary for USMC. The proposed method offers suitable switching arrangements using auxiliary shoot through (AST) switches to minimize the peak‐to‐peak CMV. This proposed method holds the advantages of the conventional method, like a wide range of modulation index and zero current switching at the rectifier side, and also reduces the CMV problem. This paper also provides a comparative analysis of the existing reported methods and the proposed method. The effectiveness of the proposed method is validated through both simulation and experimental results.

A Novel Modulation Scheme for Simultaneous Common-Mode Voltage Reduction and Neutral-Point Voltage Balance in the Reduced Switch Count Quasi-Z-Source Three-Level Inverter

The reduced switch count quasi-Z-source three-level inverter (RSC-QZS-TLI) not only maintains the advantages of continuous input current in the conventional quasi-Z-source three-level inverter (C-QZS-TLI), but also reduces the number of power switches and system cost. However, it inevitably faces the challenges of high common-mode voltage (CMV) and neutral-point voltage (NPV) imbalance, which threaten system safety and reliability. Moreover, due to the inherent features of this topology, the medium vectors cannot be generated, which means that the traditional modulation method is not applicable any more. To address the above challenges, a novel modulation method is proposed. The pre-selected basic vectors are optimized primarily, which restrict the CMV magnitude within one-sixth of dc-link voltage. Then, for the particularity of RSC-QZS-TLI, the distribution factor of small vector and its limitation range are introduced for the first time, and an indirect calculating approach is developed to obtain the duty cycles of the pre-selected four vectors, which maintains the correct ac output voltage and dc voltage boosting ability. Meanwhile, according to sector number and output of NPV controller, the distribution factor is modified to control the NPV balance. Compared with the traditional modulation method, the CMV magnitude of the proposed method is reduced by 50 %, and the balanced NPV is controlled actively. Simulated and experimental results verify the feasibility of the proposed scheme.

Reduction of common mode voltage for grid-connected multilevel inverters using fuzzy logic controller

Cascaded multilevel three-phase inverters are increasing in industries of electric drives and renewable energy because of their large capacity and suffering from high voltage shock. However, the high magnitude of common mode voltage is one of the drawbacks. Thus, the techniques of modulation and control in these multilevel inverters significantly affect the power quality of the output voltage of inverters. This paper presents a technique using fuzzy logic technique for grid-connected cascaded multilevel 3-phase inverters. This technique has completely removed the current controllers and the conventional modulation using carriers. It also helps reduce the magnitude of common mode voltage and increase the dynamic response. Moreover, the ability to reduce harmonics and switching count also helps decrease the switching loss of inverter. The simulation results on a grid-connected cascaded 5-level 3-phase inverter have validated the effectiveness of the presented technique compared with that of the conventional method using phase opposition disposition (POD) and PI current controllers.

Hybrid Space Vector Modulation Scheme to Reduce Common-Mode Voltage Magnitude and Frequency in Three-Level Quasi-Z-Source Inverter

The three-level quasi-Z-source inverter (TLQZSI) is an attractive topology that is suitable for voltage buck and boost operation. This article further presents a hybrid space vector modulation (HSVM) scheme to reduce the common-mode voltage (CMV) magnitude and frequency simultaneously. At first, the selection of basic vectors is optimized. Six medium vectors, six small vectors that have low CMV magnitudes, one zero vector, and three shoot-through vectors are utilized to produce the ac output voltage. The shoot-through state is properly inserted within the zero vector without affecting the normal ac output voltage. The effective small vector is selected according to the neutral-point voltage (NPV). Duty cycles of the adopted vectors are updated accordingly, and the restriction of the duty cycle of effective small vector is also derived. When comparing with the conventional SVM method, the CMV magnitude for the proposed scheme is suppressed by half. Furthermore, the CMV frequency is reduced by comparison to the conventional CMV reduction method. The feasibility of the proposed scheme has been tested by using the Simulink platform and a hardware-based test rig.

Performance Investigation on SVPWM Sequences Based on Reduced Common-Mode Voltage in Dual Three-Phase Asymmetrical Machine

This paper presents Space Vector Modulation (SVM) sequences that reduce Common Mode Voltage (CMV) in Dual Three-phase Asymmetrical Induction Motor (DTAIM). At first, two existing SVM techniques such as Reference SVM (RSVM) and CMV1 are studied. Additionally, three new switching sequences are developed as CMV2, CMV3 and DCMV3, which reduce peak magnitude of CMV by 66.8% in comparison with RSVM technique. In SVM techniques, to obtain least CMV, zero vectors are usually replaced by two opposite large Active voltage Vectors (AV) with equal time duration. In such topologies like CMV1, total six AVs are utilized to synthesize the reference vector. The proposed SVM technique CMV2 utilizes only five large AVs to synthesize the reference vector and reduces CMV. Selection of five neighbouring AVs is reflected in reduction of harmonic flux trajectories and stator current ripple in proposed techniques. Additionally, two more switching sequences (CMV3 and DCMV3) are developed related to utilization of specific zero voltage vectors in all sectors (7 and 56) that produce zero CMV. These two switching sequences also provide easy implementation feature during the development of c-code program. In this study, CMV and stator current ripple are considered as performance parameters for different SVM techniques. All SVM techniques are analysed by analytical results, computer simulations, and using prototype test setup of DTAIM fed by Dual Three-phase Voltage Source Inverters (DTVSIs).

A four-state CBPWM technique for common-mode voltage reduction in two-level inverter

Common-mode voltage (CMV) leads to a large number of failures in power electronics systems, for example, in two level voltage source inverter (2L VSI)-based circuits. This paper presents a four-state (4S) carrier-based pulse-width modulation (CBPWM) technique which yields the reduced CMV (RCMV) for a 2L VSI. The proposed algorithm is called as 4S RCMV CBPWM. The principle of 4S RCMV CBPWM technique is based on the four-state space vector modulation (4S SVM), which removes the zero vectors in the switching sequence and utilizes the active vectors so that the magnitude of CMV is limited to one-sixth of DC source voltage. In addition, the proposed technique also considers the target of minimizing average CMV values on the whole operation area of the space vector diagram. To implement the proposed algorithm, the CMV function is firstly analyzed so that the requirements for minimized average CMV values are achieved. Control voltages for 2L VSI is deduced from the reference voltages and offset function, thus the required average CMV is achieved. Carrier implementation for proposed algorithm is also analyzed. The theory study is verified by simulation and experiment models the quality of proposed method is evaluated in terms of harmonics distortion factors.

Hybrid SHM-PWM for Common-Mode Voltage Reduction in Three-Phase Three-Level NPC Inverter

This article proposes hybrid selective harmonic mitigation (SHM)-pulsewidth modulation (PWM) that is characterized by both features harmonic mitigation and elimination aimed to reduce the common-mode voltage (CMV) and to mitigate the selected nontriplen harmonics in a three-phase neutral-point-clamped (NPC) inverter. As CMV harmonic modeling only shows triplens, the specified triplens are eliminated using the selective harmonic elimination (SHE) operation to control CMV pulsewidths and consequently to mitigate CMV magnitude that appears as its root-mean-square (rms) reduction. The determined nontriplen harmonics are also mitigated using the SHM approach by the same cost function. The proposed hybrid SHM-PWM empowered by both harmonic elimination and mitigation is implemented on a three-phase NPC inverter to confirm its performance on reducing CMV through experimental and theoretical analyses. It is shown that hybrid SHM is superior over pure SHE or SHM in dealing with multiobjective system, including CMV reduction and no ntriplen harmonics mitigation.

Double Vector Model Predictive Control to Reduce Common-Mode Voltage Without Weighting Factors for Three-Level Inverters

The conventional model predictive control (MPC) suffers from high common-mode voltage (CMV) magnitude and large current ripples. In this article, the reduced CMV MPC strategy with double vector (RCMV-MPCDV) is proposed for three-level inverters, which adopts double vector to reduce the CMV and current ripples simultaneously in per-sampling period. First, based on geometric relationship of median, a novel cost function that evaluates median line distance is proposed to reduce the computational complexity, rather than evaluating the closest distance. Second, in order to reduce the computational burden, the double vector preselection algorithm is presented with fewer evaluation times. Third, the candidate vectors are reclassified and regrouped from partial basic vectors, which restricts CMV magnitude within one-sixth of dc-link voltage. In addition, to select more satisfactory double vectors for RCMV-MPCDV scheme, two improved methods are proposed to compensate the losing candidate vectors. The simulation and experimental results with steady-state performance and dynamic response validate the effectiveness of the proposed method.

Common-Mode Reduction SVPWM for Three-Phase Motor Fed by Two-Level Voltage Source Inverter

Aiming at the problem of large magnitude and high frequency of common-mode voltage (CMV) when space vector pulse width modulation (SVPWM) is used in a three-phase motor fed by a two-level voltage source inverter, a common-mode reduction SVPWM (CMRSVPWM) is studied. In this method, six new sectors are obtained by rotating six sectors of conventional SVPWM by 30°. In odd-numbered sectors, only three non-zero vectors with odd subscripts are used for synthesis, while in even-numbered sectors, only three non-zero vectors with even subscripts are used for synthesis. The actuation durations of three non-zero vectors in each switching period in each sector are given. Simulation and experimental results show that, compared with the conventional SVPWM, the CMV magnitude of CMRSVPWM is reduced by 66.67% and the CMV frequency of CMRSVPWM is reduced from the original switching frequency to the triple fundamental frequency. At the same time, the current, torque and speed of the motor are still good.

Phase-Disposition PWM Based 2DoF-Interleaving Scheme for Minimizing High Frequency ZSCC in Modular Parallel Three-Level Converters

This paper proposes a two-degree-of-freedom (2DoF) interleaving scheme based on phase-disposition (PD) PWM for minimizing the high-frequency zero-sequence circulating current (ZSCC) in modular interleaved three-level converters. The method incorporates an internal interleaving by phase-shifting the carriers in each individual converter, and an external interleaving by phase-shifting the carriers of the different converters. A general harmonic distribution analysis which is valid for all types of voltage source converters is carried out to simplify the evaluation of the proposed method. A comprehensive evaluation of the proposed method shows that the PD-2DoF interleaving scheme produces the lowest ZSCC maximum value as compared to existing approaches. Moreover, it can achieve comparable performances as existing methods do in terms of output quality and common mode voltage magnitude, showing a great potential for practical implementation. Simulation and experimental results are obtained to demonstrate the performance of the proposed method. Generalization of the 2DoF interleaving scheme to high-level converter is also discussed in this paper.

An Optimized Zero-Sequence Voltage Injection Method for Eliminating Circulating Current and Reducing Common Mode Voltage of Parallel-Connected Three-Level Converters

Parallel three-level inverters have attracted considerable attention due to the advantages to increase the power rating and the flexibility of power conversion systems. However, this type of configuration requires to suppress the zero-sequence circulating current (ZSCC) through either modulation or active control strategies, to avoid overloading problems of a single three-level inverter. For the operation of paralleled three-level T-type inverters, another requirement is to reduce the common mode voltage (CMV) associated with a pulsewidth modulation method. To better solve these problems simultaneously, an optimized zero-sequence voltage injection method is proposed to both reduce CMV and eliminate ZSCC for multiparallel-connected three-level inverters. A generalized CMV reduction strategy is developed, which can reduce the magnitude of CMV to one half of the value using the conventional space vector modulation. The highlight of the method is that ZSCC is eliminated by adding an optimal compensation value to the reference duty signals with lower CMV. This compensation value is calculated simply by ZSCC, duty cycles, and filter parameters. The better ZSCC suppression performance can be obtained in both steady and transient states with the proposed scheme, thus, improving the quality of currents.

Improved Space Vector Modulation Technique for Neutral-Point Voltage Oscillation and Common-Mode Voltage Reduction in Three-Level Inverter

Three-level inverter has an outstanding performance and is more advantageous in the switching vector selection than two-level inverter. In particular, the neutral-point voltage unbalance and common-mode voltage (CMV) reduction of three-level inverter should be carefully regulated for the appropriate operation, both of which, however, are mutually coupled resulting that the conventional space vector modulation (SVM) scheme cannot deal with them properly. To overcome this limitation, this paper proposes an improved space vector modulation (ISVM) technique to reduce the CMV and neutral-point voltage imbalance simultaneously. The generating mechanism of neutral-point voltage oscillation is derived. Based on the analysis, the proposed ISVM method adopts four voltage vectors (large, medium, small, and zero vectors) with adjusted dwell times to eliminate the ac unbalance of the neutral-point voltage. Considering the occurrence of neutral-point voltage disturbances, the dc neutral-point unbalance voltage is controlled by selecting the P-type or N-type small vector and adjusting the dwell times of small vectors for neutral-point voltage recovery. In addition, a novel switching sequence arrangement method with the minimal number of switches transition in one switching cycles and between switching cycles is proposed to reduce the total switching loss. Theoretical analysis and verification results show that the proposed ISVM scheme can reduce the magnitude of CMV to half of value using the conventional SVM, and an accurate control of ac and dc unbalanced neutral-point voltage can be obtained.

Design of Passive Common-Mode Attenuation Methods for Inverter-Fed Induction Motor Drive With Reduced Common-Mode Voltage PWM Technique

This paper investigates the influence of active zero vector pulsewidth modulation (AZPWM-1) and space vector pulsewidth modulation (SVPWM) on the design of passive common-mode (CM) attenuation methods to reduce CM current and shaft voltage in inverter-fed V/f-controlled induction motor drives. The passive CM attenuation methods examined here are the CM choke, the CM electromagnetic interference (EMI) filter, and the CM transformer. The attenuation requirement of AZPWM-1 and SVPWM is identified to design the passive CM choke and EMI filter. Based on the attenuation requirement, the design guidelines are revisited for SVPWM, and design rules are proposed for AZPWM-1. However, the CM transformer is designed based on the step change in magnitude of CM voltage of both the pulsewidth modulations (PWMs). The limitations in design, regarding switching frequency and component size for each case, are also established. It is shown that to have a similar attenuation in the considered two PWM cases, AZPWM-1 requires smaller passive components compared to SVPWM. The proposed design guidelines are substantiated with experimental results on a 1.1-kW induction motor drive.

Simultaneous Common-Mode Voltage Reduction and Neutral-Point Voltage Balance Scheme for the Quasi-Z-Source Three-Level T-Type Inverter

The conventional three-level inverter only has voltage buck capability. The quasi-Z-source three-level T-type inverter (QZS 3LT $^2$ I) has been proposed to realize voltage buck–boost operation. In this paper, we further propose a novel modulation scheme for the QZS 3LT $^2$ I to realize voltage boosting, reduce the common-mode voltage (CMV), and control the neutral-point voltage balance simultaneously. The proposed scheme adopts a large vector, a medium vector, a small vector with low CMV magnitude, a zero vector, and a shoot-through vector to generate the output voltage. According to sector number and neutral-point voltage difference, a p-type or n-type small vector with low CMV magnitude is properly selected to balance the neutral-point voltage. Shoot-through states are inserted within zero vector to boost the dc input voltage without affecting the ac output voltage. Dwell times of basic vectors are calculated through the revised volt–second balance equation. Furthermore, a coordinate control strategy between neutral-point voltage balance and voltage boosting is proposed. Doing so, the CMV magnitude can be restricted within one-sixth of dc-link voltage and neutral-point voltage imbalance can be effectively mitigated. The effectiveness of the proposed scheme is verified by simulations and experiments.

SVM Strategies for Simultaneous Common-Mode Voltage Reduction and DC Current Balancing in Parallel Current Source Converters

Parallel-connected current source converters (CSCs) can be used to increase the power capacity and the flexibility of power conversion systems. However, this type of configuration needs to obtain proper dc current balancing through either passive methods or active PWM (pulse width modulation) strategies, in order to avoid overloading problems of a single converter. For the operation of transformer-less CSCs, another requirement is to reduce the common-mode voltage (CMV) associated with PWM strategies. As these two issues are mutually coupled, the conventional space vector modulation (SVM) and various types of enhanced methods reported so far cannot address them properly at the same time. To overcome this limitation, a modified SVM via two-layer small vector selection criteria is developed. Theoretical analysis and verification results show that the proposed method can reduce the magnitude of CMV to one-third of the value using the conventional SVM, and the accurate control of dc current balancing with reduced ripples can be obtained at both the steady and transient states.

A Three-Level Space Vector Modulation Scheme for Paralleled Converters to Reduce Circulating Current and Common-Mode Voltage

For high-power applications, paralleling converters is a popular approach to increase the power capacity of the system. Circulating current has been a major concern for the implementation of paralleled converters. This paper proposes a three-level space vector modulation (SVM) scheme for a system with two paralleled voltage-source converters (VSCs) with common-mode inductor (CMI) or single-phase inductors. The proposed scheme aims to reduce the zero-sequence circulating current (ZSCC) and the magnitude of common-mode voltage (CMV) of the system simultaneously. The ZSCC patterns with respect to modulation schemes are first analyzed to provide a clear understanding of the generation of ZSCC. Based on the analysis, the proposed three-level modulation scheme is introduced. Furthermore, performance regarding the ZSCC peak value, impact on the common-mode current (CMC), CMI scaling analysis, and switching losses are analyzed and compared with the existing methods. The proposed method has been verified in both simulation and experiment.

A Predictive Capacitor Voltage Control of a Hybrid Cascaded Multilevel Inverter With a Single DC-Link and Reduced Common-Mode Voltage Operation

For cascaded multilevel inverter topologies with a single dc supply, closed-loop capacitor voltage control is necessary for proper operation. This paper presents zero and reduced common-mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. Each phase of the inverter is realized by cascading two- three-level flying capacitor inverters with a half-bridge module in between. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state that minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96%, the inverter can operate with reduced CMV magnitude ( $V_{\rm dc}/18$ ) and reduced CMV switching frequency using the new space-vector pulsewidth modulation (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop $V/f$ control scheme.

Reduced common‐mode voltage operation of a new seven‐level hybrid multilevel inverter topology with a single DC voltage source

In this study, analysis of extending the linear modulation range of a zero common-mode voltage (CMV) operated n-level inverter by allowing reduced CMV switching is presented. A new hybrid seven-level inverter topology with a single DC supply is also presented in this study and inverter operation for zero and reduced CMV is analysed. Each phase of the inverter is realised by cascading two three-level flying capacitor inverters with a half-bridge module in between. Proposed inverter topology is operated with zero CMV for modulation index <86% and is operated with a CMV magnitude of V-dc/18 to extend the modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilising the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology.

Carrier Based Common Mode Voltage Reduction Techniques in Neutral Point Clamped Inverter Based AC-DC-AC Drive System

Common mode voltage (CMV) generation is a major problem in switching power converter fed induction motor drive systems. CMV is the zero sequence voltage generated due to the switching action of power converters. Even a small magnitude of CMV with a high rate of change may circulate large bearing currents which may damage a machine’s bearings and shorten its life. There are several methods of controlling CMV. This paper presents 3-level sinusoidal pulse width modulation based techniques to control the magnitude and rate of change of CMV in multilevel AC-DC-AC drive systems. Simulation and experimental investigations have been presented to validate the performance of proposed technique to control CMV in 3-level neutral point clamped inverter based AC-DC-AC system.