Magnetic Tunnel Junction Resistance Research Articles

Granular vortex spin-torque nano oscillator for reservoir computing

In this paper, we investigate the granularity in the free layer of the magnetic tunnel junctions (MTJ) and its potential to function as a reservoir for reservoir computing where grains act as oscillatory neurons while the device is in the vortex state. The input of the reservoir is applied in the form of a magnetic field which can pin the vortex core into different grains of the device in the magnetic vortex state. The oscillation frequency and MTJ resistance vary across different grains in a non-linear fashion making them great candidates to be served as the reservoir's outputs for classification objectives. Hence, we propose an experimentally validated area-efficient single granular vortex spin-torque nano oscillator (GV-STNO) device in which pinning sites work as random reservoirs that can emulate neuronal functions. We harness the nonlinear oscillation frequency and resistance exhibited by the vortex core granular pinning of the GV-STNO reservoir computing system to demonstrate waveform classification.

Methodology of backside preparation applied on a MRAM to lead a logical investigation with a near-field probe

This paper presents a method for the preparation of a magnetic random access memory (MRAM) whose data are stored in magnetic tunnel junctions (MTJ) as resistance states, in order to read them by near-field probing.The goal is to be able to visualize a difference of resistance between bits at ‘0’ and at ‘1’ thanks to the current passing through several MTJs. To do so, the MRAM needs to be prepared to create an electrical access to both sides of the MTJs. The main issue is the polishing of both sides as the stack of metallization being less than 10 μm thick. A chemical etch would in that case be encouraged by literature but we take a different approach since we choose to open further than the transistors. The preferred method is a backside preparation technique that creates a bevel allowing us to access the bottom side of the MTJs through vias and the top of them thanks to the bitlines. Since the resulting chip no longer has electrical connections, we also create a dedicated electrical path thanks to a focused ion beam (FIB) operation. At the end, it is then possible to collect the current flowing through the MTJs with a near-field probe.To probe the MTJ resistance, two near-field techniques are investigated: conductive atomic force microscopy (C-AFM) and scanning spreading resistance microscopy (SSRM). C-AFM provides a quite high resistivity probably due to its sensitivity to contact resistance. Using SSRM, a resistance of 12–16 kΩ and 17–22 kΩ were determined for “0” and “1” bits, which is in agreement with literature.

Spin Control and Multifunctional Photocurrent Switch in Chiral Hybrid Organic–Inorganic Perovskites

Chiral-induced spin selectivity effect provides a new strategy for manipulating electron spin, which has potential applications in various spin-related fields. Here, the spin-selective electronic transport and photocurrent response of (R,S-MBA)2PbI4 are investigated systematically by first-principles calculations. The minimum periodic chiral hybrid system has stable spin filtering ability. Different from achiral magnetic tunnel junctions (MTJs), the resistance of chiral MTJs depends on the chirality of (R,S-MBA)2PbI4 and magnetization arrangement of ferromagnetic electrodes. Additionally, the photon energy and magnetization arrangement of electrodes can be used to switch the spin channel and photocurrent direction. At a photon energy of 3.0 eV, chiral MTJs can transfer from separating spin into outputting highly spin-polarized photocurrent by changing the magnetization arrangement of electrodes. Chiral spin control and multifunctional photocurrent switch of Fe/(R,S-MBA)2PbI4/Fe MTJs provide important information for the design of chiral spintronic and nanoscale electronic devices.

Electrical Detection of Magnetic Skyrmions in a Magnetic Tunnel Junction

AbstractMagnetic skyrmions are promising information carriers for dense and energy‐efficient information storage owing to their small size, low driving‐current density, and topological stability. Electrical detection of skyrmions is a crucial requirement to drive skyrmion devices toward applications. The use of a magnetic tunnel junction (MTJ) is commonly suggested for this purpose as MTJs are key spintronic devices for large‐scale commercialization that can convert magnetic textures into electrical signals. To date, however, it has been challenging to realize skyrmions in MTJs due to incompatibility between standard skyrmion materials and highly efficient MTJ electrodes. Here, a material stack combining magnetic multilayers, which host 100 nm scale skyrmions, with a perpendicularly magnetized MTJ, is reported. The devices are designed so that the skyrmions in the multilayer are imprinted into the MTJ's free layer via magnetostatic interactions. The electrical response of a single skyrmion is successfully identified by employing simultaneous imaging of the magnetic texture and the electrical measurement of the MTJ resistance. The results are an important step toward all‐electrical detection of skyrmions.

Sub-pT magnetic field detection by tunnel magneto-resistive sensors

We developed tunnel magneto-resistive (TMR) sensors based on magnetic tunnel junctions (MTJs) that are able to detect a weak, sub-pT, magnetic field at a low frequency. Small detectivities of 0.94 pT/Hz1/2 at 1 Hz and 0.05 pT/Hz1/2 at 1 kHz were achieved by lowering the resistance of MTJs and enhancement of the signal using a thick CoFeSiB layer and magnetic flux concentrators. We demonstrated real-time measurement of magnetocardiography (MCG) and nuclear magnetic resonance (NMR) of protons using developed sensors. This result shows that both MCG and NMR can be measured by the same measurement system with ultra-sensitive TMR sensors.

Compact Model of Dzyaloshinskii Domain Wall Motion-Based MTJ for Spin Neural Networks

Recent progress has demonstrated that current-induced domain wall motion (CIDWM) is able to achieve efficient and ultrafast magnetic switching in the case of spin–orbit torque (SOT) and Dzyaloshinskii–Moriya interaction (DMI). CIDWM-based devices are taken as promising candidates for the next-generation nonvolatile artificial neurons and synapses due to its excellent programmability, fast operation speed, low write power, and so on. In this article, we present a physics-based model of CIDWM magnetic tunnel junction (MTJ), which exhibits high performance based on experimental results. The proposed model integrates the CIDWM dynamics and nanowire MTJ resistance, showing great agreement with extensive physical simulation. A learning circuit based on CIDWM-MTJ, as a hybrid MTJ/CMOS circuit example, has been designed and simulated to validate its functionality. The proposed SPICE-compatible compact model will be useful for high-performance circuit and system evaluation and is expected to promote the research and development of CIDWM-based spintronics devices.

Single-shot dynamics of spin-orbit torque and spin transfer torque switching in three-terminal magnetic tunnel junctions.

Current-induced spin-transfer torques (STT) and spin-orbit torques (SOT) enable the electrical switching of magnetic tunnel junctions (MTJs) in non-volatile magnetic random access memories. To develop faster memory devices, an improvement in the timescales that underlie the current-driven magnetization dynamics is required. Here we report all-electrical time-resolved measurements of magnetization reversal driven by SOT in a three-terminal MTJ device. Single-shot measurements of the MTJ resistance during current injection reveal that SOT switching involves a stochastic two-step process that consists of a domain nucleation time and propagation time, which have different genesis, timescales and statistical distributions compared to STT switching. We further show that the combination of SOT, STT and the voltage control of magnetic anisotropy leads to reproducible subnanosecond switching with the spread of the cumulative switching time smaller than 0.2 ns. Our measurements unravel the combined impact of SOT, STT and the voltage control of magnetic anisotropy in determining the switching speed and efficiency of MTJ devices.

SPICE-Only Model for Spin-Transfer Torque Domain Wall MTJ Logic

The spin-transfer torque domain wall (DW) magnetic tunnel junction (MTJ) enables spintronic logic circuits that can be directly cascaded without deleterious signal conversion circuitry and is one of the only spintronic devices for which cascading has been demonstrated experimentally. However, experimental progress has been impeded by a cumbersome modeling technique that requires a combination of micromagnetic and SPICE simulations. This paper, therefore, presents a SPICE-only device model that efficiently determines the DW motion resulting from spin accumulation and calculates the corresponding MTJ resistance. This model has been validated through comparison to the authoritative micromagnetic-based model, enabling reliable prediction of circuit behavior as a function of device parameters with a 10 000 $\times $ reduction in the simulation time. This model thus enables deeper device and circuit investigation, advancing the prospects for nonvolatile spintronic computing systems that overcome the von Neumann bottleneck.

Increasing the signal-to-noise ratio of magnetic tunnel junctions by cryogenic preamplification

Cryogenic preamplification using silicon–germanium heterojunction bipolar transistors has proven to be effective in increasing the signal-to-noise ratio of the tunnel magnetoresistance of high resistance magnetic tunnel junctions at 8 K. The magnetic tunnel junctions used have resistances greater than 1 MΩ, and the cryogenic measurement system still has sufficient bandwidth for the 1/f noise to roll off. A noise model for the system has been proposed and evaluated experimentally. The noise temperature and minimum noise temperature of the transistor used in the experiment are calculated and compared. The signal-to-noise ratio of the junction alone and the transistor-junction system is derived from the sample and circuit parameters and compared. Experimental data show a signal-to-noise ratio increase by a factor of 6.62 after adding in the cryogenic preamplifier. An increase in 1/f noise in the antiparallel state of the tunneling junction as opposed to the parallel state is also observed giving evidence of 1/f noise dependence on the magnetic state of the junction.

A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs

A combination of semiconductor integrated circuits (IC) and a dense array of scaled magnetic tunnel junctions (MTJ) makes promising Spin-Transfer Torque Random Access Memory (STT-RAM). This emerging memory minimizes the leakage power consumption and provides a high density at scaled technologies. In this paper, we propose a novel non-destructive self-reference sensing scheme for STT-RAM. The proposed technique overcomes the large bit-to-bit variation of MTJ resistance. In the proposed scheme, the stored value in the STT-RAM cell preserves, hence, the long write-back operation is eliminated. Besides, the sensing scheme is accomplished in one step. In this scheme, the Bit-Line is pre-charged and then discharged during read operation. The MTJ resistance state can be found by comparing the time constant of discharging. The simulation results show the overall sensing time is 4 ns when the Bit-Line capacitance is equal to 200 fF.

Bolometric Properties of a Spin-Torque Diode Based on a Magnetic Tunnel Junction

Spin caloritronics opens up a wide range of potential applications, one of which can be the thermoelectric rectification of a microwave signal by spin-diode structures. The bolometric properties of a spin-torque diode based on a magnetic tunnel junction (MTJ) in the presence of a thermal gradient through a tunnel junction are discussed. Theoretical estimates of the static and dynamic components of the microwave sensitivity of the spin-torque diode, related to thermoelectric tunnel magneto-Seebeck effect and the thermal transfer of spin angular momentum in the MTJ under nonuniform heating, are presented. Despite the fact that the thermal contribution to the microwave sensitivity of the spin-torque diode is found to be relatively small in relation to the rectification effect related to the modulation of the MTJ resistance by a microwave spin-polarized current, nevertheless, the considered bolometric effect can be successfully utilized in some real-world microwave applications.

Optical Receiver With Helicity-Dependent Magnetization Reversal

In this paper, we propose helicity-dependent switching (HDS) of magnetization in Co/Pt for an energy efficient optical receiver. Designing a low-power optical receiver for optical-to-electrical signal conversion has proven to be very challenging. Current day optical receivers use a photodiode that produces a photocurrent in response to input optical signals, and power hungry transimpedance amplifiers are required to amplify the small photocurrents. These limitations can be overcome by using light helicity-induced switching of magnetization which can avoid the requirement of photodiodes and subsequent transimpedance amplification by sensing the change in magnetization with a magnetic tunnel junction (MTJ). Magnetization switching of a thin ferromagnet layer using circularly polarized laser pulses has recently been demonstrated which shows a one-to-one correspondence between light helicity and the magnetization state. We use these phenomena to directly switch the magnetization state of a thin Co/Pt ferromagnet layer at the receiver via circularly polarized laser pulses. The circular polarization is controlled in accordance with digital input data which establishes a one-to-one correspondence between the transmitted data and output magnetization state. The Co/Pt layer is used as the free layer of an MTJ, the resistance of which is modified by the laser pulses. Since the output magnetization state is controlled by the input data, the MTJ resistance is directly converted to a digital output signal. Our device-to-circuit level simulation results indicate that HDS-based optical receiver circuit consumes only 0.124 pJ/bit energy, which is much lower than existing techniques.

Capacitively Driven Global Interconnect With Energy-Efficient Receiver Based on Magneto-Electric Switching

We model a capacitively driven, low-swing, global interconnect circuit based on a receiver that utilizes magnetization switching induced by the magneto-electric (ME) effect. Capacitively driven wire was recently shown to be effective in improving the performance of global interconnects. Such techniques can reduce the signal swing in the interconnect with the use of a capacitive divider network, which does not require an additional voltage supply. However, the large reduction in signal swing makes it necessary to use differential signaling and amplification for successful regeneration at the receiver, which add wire area and require static power. The ME effect has been shown to reverse the magnetization of a nanomagnet by applying a low voltage to an adjacent multiferroic oxide. Here, we propose a receiver based on the ME effect that uses the low voltage at the receiving end of the global wire to switch a nanomagnet. The nanomagnet is also used as the free layer of a magnetic tunnel junction (MTJ), the resistance of which is tuned through the ME effect. This change in MTJ resistance is converted to full-swing binary signals with simple digital components. This process allows capacitive, low-swing interconnection without differential signaling or amplification, which leads to significant energy efficiency. Our simulation results indicate that for 5–10 mm long global wires in IBM 45 nm technology, the capacitive ME design consumes one third the energy of a full-swing complementary metal-oxide semiconductor (CMOS) design and one half the energy of a differential amplifier low-swing capacitive CMOS design.

On the Hardware Implementation of MRAM Physically Unclonable Function

Intrinsic properties of magnetic tunnel junctions (MTJs) are exploited for low-power security electronics. The combination of: 1) fast and nonvolatile storage; 2) stochastic nature of subcritical switching; and 3) random variation in the magnetic anisotropy of MTJ make MRAM array ideal for implementing physically unclonable function (PUF). We develop two bit-pattern randomization procedures, one of which can be exercised at wafer level in process line, while the other can be completed in the in-line tester. The procedures generate unpredictable and unclonable bit patterns in a spin-transfer torque (STT)-MRAM array and store them securely in the array. We show the resistance of MTJ is stable through rounds of thermal baking, the readback from the PUF shows no ambiguity from 25 °C to 75 °C. A single embedded STT-MRAM PUF can cover many needs of security electronics.

Reliability-Enhanced Hybrid CMOS/MTJ Logic Circuit Architecture

Benefitting from its non-volatility, nearly infinite endurance, good scalability, and great CMOS compatibility, magnetic tunnel junction (MTJ) embedded in conventional CMOS logic circuits has been proposed as one potentially powerful solution to introduce non-volatility in today’s programmable logic circuits, which is envisioned to achieve low power and high area efficiency. However, the recently proposed hybrid CMOS/MTJ logic circuits and prototypes based on such a logic-in-memory architecture suffers from a severe reliability issue, which is the precise transformation from MTJ resistance to electric signals due to its limited tunnel magnetoresistance ratio (TMR $\leq$ 150%), i.e., the requirement of nearly zero sensing error for logic applications. In this paper, to overcome this sensing reliability issue, a novel sense amplifier (SA) with high sensing margin is proposed for such hybrid CMOS/MTJ logic circuit architecture. By using a commercial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ transient and Monte Carlo statistic simulations have been conducted to demonstrate the functionality of the proposed SA and evaluate its performance, respectively.

Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing

Spin-Transfer-Torque RAM (STTRAM) is a promising technology for high-density on-chip cache due to low standby power and high speed. However, the process variation of the Magnetic Tunnel Junction (MTJ) and access transistor poses a serious challenge to sensing. Nondestructive sensing suffers from reference resistance variation, whereas destructive sensing suffers from failures due to unoptimized selection of data and reference currents. Furthermore, the sense speed is tightly coupled with the reference/data current requirement. In this work, we study the process variation effect on a self-reference sensing scheme to eliminate bit-to-bit process variation in MTJ resistance. Read current modulation is proposed to overcome the failures due to process variation. Simulation results reveal <0.01% failures at the cost of 9ns sense time and 190uW power consumption.

Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design

Rapidly increasing demands for memory capacity and severe technical scaling challenges of conventional memory technologies motivated recent investments on next-generation nonvolatile memory technologies. As a promising candidate, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive properties, such as nanosecond access time, high integration density, nonvolatility, and excellent CMOS integration compatibility. However, similar to all other nano-devices, the performance and reliability of STT-RAM cells are greatly affected by process variations, device operating uncertainties, and environmental fluctuations. As a result, the read and write operations of STT-RAM demonstrate some variabilities and errors. In this paper, we systematically analyze the impacts of CMOS and magnetic tunneling junction (MTJ) process variations, MTJ resistance switching randomness that are induced by intrinsic thermal fluctuations, and working temperature changes on STT-RAM cell designs. The STT-RAM cell reliability issues in both read and write operations are first investigated. A combined circuit and magnetic simulation platform is then established to quantitatively study the persistent and nonpersistent errors in STT-RAM cell operations. Our analysis proved the importance of a full statistical design method in STT-RAM designs for design pessimism minimization.

A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less

Spin-transfer torque magnetoresistance random access memory is a major contender for static random access memory replacement in embedded caches at advanced fin field effect transistor nodes. It suffers, however, from the low resistance difference between the bistable states of the magnetic tunnel junction (MTJ). Variability on MTJ resistance and access transistors makes reliable read-out even more challenging. This triggered the use of complementary cells for low level caches needing high performance. This paper, focusing on the lower level caches, shows an improved 3T 2MTJ cell with a ground grid and a novel three transistor read and write operation to improve area density, sense margin, write performance, and write energy consumption. Despite the cell’s three transistors, the improved array configuration reduces the cell area by 22% as compared with the 2T 2MTJ cell, making it only 55% larger than a 1T 1MTJ cell. The novel mismatch tolerant read operation uses all three transistors and increases the sense margin by up to 88%. The novel variation resilient write operation also uses all three transistors and takes advantage of the inherent MTJ characteristics and complementary operation of the cell. This increases the write performance by $2\times $ and reduces the write energy by $3\times $ compared with the 2T 2MTJ cell and by $1.5\times $ compared with the 1T 1MTJ cell.

Stochastic macromodel of magnetic tunnel junction resistance variation and critical current dependence on resistance variation for SPICE simulation

The resistance distribution of a magnetic tunnel junction (MTJ) shows nonuniformity according to various MTJ parameters. Moreover, this resistance variation leads to write-current density variation, which can cause serious problems when designing peripheral circuits for spin transfer torque magnetoresistance random access memory (STT-MRAM) and commercializing gigabit STT-MRAM. Therefore, a macromodel of MTJ including resistance, tunneling magnetoresistance ratio (TMR), and critical current variations is required for circuit designers to design MRAM peripheral circuits, that can overcome the various effects of the variations, such as write failure and read failure, and realize STT-MRAM. In this study, we investigated a stochastic behavior macromodel of the write current dependence on the MTJ resistance variation. The proposed model can possibly be used to analyze the write current density in relation to the resistance and TMR variations of MTJ with various parameter variations. It can be very helpful for designing STT-MRAM circuits and simulating the operation of STT-MRAM devices considering MTJ variations.

$1\times$ - to $2\times$ -nm perpendicular MTJ Switching at Sub-3-ns Pulses Below $100~\mu$ A for High-Performance Embedded STT-MRAM for Sub-20-nm CMOS

Magnetization switching is confirmed for sub-3-ns pulses below $100~\mu \text{A}$ in perpendicular magnetic tunnel junctions (MTJs) down to 16 nm in diameter. The magnetoresistance ratio exceeded 150%, satisfying requirements for fast read conditions. Using sub-30-nm MTJs, write-error rates of up to an order of −6 (10−6) are demonstrated. Read and write current margins, which are important device designs, are sufficiently large to avoid read disturbances. Moreover, $1\times $ -to- $2\times $ -nm MTJs have sufficient data retention for level-2 or level-3 cache requirements. Furthermore, the MTJ resistance remains stable after 1012 write events. To the best of our knowledge, this is the first demonstration of $1\times $ - to $2\times $ -nm MTJs supporting cache memory along with read–write current margins, fast read operations, low power consumption, sufficient retention, and high endurance.