M3 Processor Research Articles

Improved RSA with Enhanced Security on STM32 @ 84MHz

Enhanced computations resulted in the evolution of cyber-physical systems (CPS). These systems are highly vulnerable to security threats. This work addresses the security concerns for a reliable CPS in the Internet of Things (IoT) through an improvised RSA with enhanced security features. The proposed method renders data throughput encryption at 11.67[Formula: see text]Kbps with an overall average execution time of 0.02[Formula: see text]s. The proposed algorithm exhibits the unique feature of being asymmetric, lightweight & enhanced security owing to randomization (average entropy of 0.98). The performance metrics of the proposed method are compared with other state-of-art techniques. This algorithm is implemented on commercially competent architecture STM32F401RET6 with cortex M4 processor running @ 84[Formula: see text]MHz. The proposed encryption method exhibits great features thus making it a potential real-world solution.

Type-1 and type-2 fuzzy logic-based space vector modulation for two-level inverter fed induction motor

Two-level inverter control with type-1 and type-2 fuzzy logic-based space vector pulse-width modulation (PWM) method for induction motor drive (IMD) is presented in this paper. A new sampling time independent strategy with type-1 and type-2 fuzzy based methods are used in generating three phase duty ratios which are directly obtained without mathematical equations. The conventional method of space vector modulation (SVM) produces the duty ratios for the inverter which are sampling time dependent. However, in type-1 and type-2 fuzzy based space vector PWM algorithms, the three phases duty ratios generated are sampling time independent and with a new integrated dead-time insertion in SVM itself, can be implemented practically for any switching frequency. As the rule-base for Mamdani non-singleton interval type-1 and type-2 fuzzy inference systems are designed manually, with the expert knowledge of conventional space vector PWM, the duty ratios of the inverter are generated such that the performance of the IMD is improved. The simulation studies for aforementioned cases is performed in matrix laboratory (MATLAB) and experimental validation for the proposed space vector PWM algorithms is validated using real-time sacraetheologiae magister (STM) hardware with STM32F429I Cortex M4 processor for a 1 hp IMD.

A Power-Efficient Brain-Machine Interface System With a Sub-mw Feature Extraction and Decoding ASIC Demonstrated in Nonhuman Primates.

Intracortical brain-machine interfaces have shown promise for restoring function to people with paralysis, but their translation to portable and implantable devices is hindered by their high power consumption. Recent devices have drastically reduced power consumption compared to standard experimental brain-machine interfaces, but still require wired or wireless connections to computing hardware for feature extraction and inference. Here, we introduce a Neural Recording And Decoding (NeuRAD) application specific integrated circuit (ASIC) in 180 nm CMOS that can extract neural spiking features and predict two-dimensional behaviors in real-time. To reduce amplifier and feature extraction power consumption, the NeuRAD has a hardware accelerator for extracting spiking band power (SBP) from intracortical spiking signals and includes an M0 processor with a fixed-point Matrix Acceleration Unit (MAU) for efficient and flexible decoding. We validated device functionality by recording SBP from a nonhuman primate implanted with a Utah microelectrode array and predicting the one- and two-dimensional finger movements the monkey was attempting to execute in closed-loop using a steady-state Kalman filter (SSKF). Using the NeuRAD's real-time predictions, the monkey achieved 100% success rate and 0.82 s mean target acquisition time to control one-dimensional finger movements using just 581 μW. To predict two-dimensional finger movements, the NeuRAD consumed 588 μW to enable the monkey to achieve a 96% success rate and 2.4 s mean acquisition time. By employing SBP, ASIC brain-machine interfaces can close the gap to enable fully implantable therapies for people with paralysis.

Three-phase inverter with a variable control algorithm

The paper presents the construction of a three-phase frequency converter with the possibility of choosing the type of PWM modulation and a smooth change of the frequency of the modulated signal. In a practical way, various inverter control algorithms were implemented in the same hardware system using the STM ARM Cortex M3 processor. The use of THIPWM modulation allowed to reduce the harmonic content in the output signal and effectively use the possibilities of the power source. The system can choose one of two scalar control algorithms, with the option of compensation for the influence of the stator resistance on the motor shaft torque in the initial range of the linear control characteristic at a constant voltage to frequency ratio. The research confirmed that the most advantageous type of PWM in this system is unipolar double-edge modulation. The use of the THIPWM method resulted in a gain in the amplitude of the fundamental harmonic of the output voltage for the three-phase inverter operation mode compared to the SPWM method. The appropriate precision of the frequency control step was also obtained, and the test results confirmed the functionality of the converter.

A hardware system with ARM-based data processing for nano satellites

<span>The Institute of Scientific and Technical Research for Defense in Argentina (Instituto de Investigaciones Científicas y Técnicas para la Defensa - CITEDEF) is developing a processing hardware module based on a ARM Cortex M4 processor from STMicroelectronics. The microcontroller (MCU) has the capacity to run at a maximum clock frequency of 180 MHz, integrates a Floating Point Unit (FPU). An 8MB SDRAM was included for dynamic data allocation. This hardware will host and process the algorithms to calculate and determine the nanosatellite’s attitude. The module is intended to be Cubesat compatible, possess a flexible design, handles various inertial sensors and can manage backups on microSD memory cards with sizes up to 32GB.</span>

Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode

Stringent power budgets in battery powered platforms have led to the development of energy saving techniques such as Dynamic Voltage and Frequency scaling (DVFS). For embedded system designers to be able to ripe the benefits of these techniques, support for efficient design space exploration must be available in system level simulators. The advent of the edge computing paradigm, with power constraints in the mW domain, has rendered this even more essential. Without a fast and accurate methodology for architecture simulation and energy estimation, the benefit of new ideas and solutions cannot be evaluated. In this paper, we propose a non-intrusive application controlled DVFS management implementation in the GEM5 simulator, used with GEM5’s system call emulation mode. We also propose a novel architecture independent energy model based on categorization of different measurable workload classes. Our energy model is parametrized and calibrated with power measurements on a SAM4L microcontroller board, containing an ARM Cortex M4 processor. Together with the GEM5 output statistics, the model accurately estimates the total energy consumption of our simulated system. The results from our modified GEM5 simulator are validated with representative signal processing applications. After correction of systematic offset errors, our results deviate with less than 4% compared to measurements from the SAM4L microcontroller. Our contributions in this paper can easily be tailored to other processor models in GEM5 and to future versions of GEM5. It will therefore enable system architects to explore new techniques and compare the improvements relative to existing architectures.

CAD-Base

Fabless semiconductor companies design system-on-chips (SoC) by using third-party intellectual property (IP) cores and fabricate them in offshore, potentially untrustworthy foundries. Owing to the globally distributed electronics supply chain, security has emerged as a serious concern. In this article, we explore electronics computer-aided design (CAD) software as a threat vector that can be exploited to introduce vulnerabilities into the SoC. We show that all electronics CAD tools—high-level synthesis, logic synthesis, physical design, verification, test, and post-silicon validation—are potential threat vectors to different degrees. We have demonstrated CAD-based attacks on several benchmarks, including the commercial ARM Cortex M0 processor [1].

Samsung M3 Processor

The M3 Processor is Samsung's third-generation custom microarchitecture. As performance demands continue to grow, major design improvements are required. In this generation, the core is enhanced with a 6-wide microarchitecture, deeper out-of-order resources, and faster instructions. The M3 delivers a new level of performance to the Android eco-system.

Instruction Level Energy Consumption Estimation of Embedded Processor

Embedded systems are portable battery powered devices that have limited power resource. Hence, most of embedded systems need to meet energy constraint. Performance and energy consumption are the most important metrics for embedded system design. Estimation of performance, energy utilization and its validation are essential for embedded system design. Attempt has been made to precisely measure software energy consumption by three methods on ARM Cortex M4 processor. The results are validated with five benchmark programs. Tedious calculation of inter instruction cost has been minimized by taking it as certain percent of total energy. Percentage error between actual and estimated energy is found to be less than 5%.

Instruction Level Energy Consumption Estimation of Embedded Processor

Embedded systems are portable battery powered devices that have limited power resource. Hence, most of embedded systems need to meet energy constraint. Performance and energy consumption are the most important metrics for embedded system design. Estimation of performance, energy utilization and its validation are essential for embedded system design. Attempt has been made to precisely measure software energy consumption by three methods on ARM Cortex M4 processor. The results are validated with five benchmark programs. Tedious calculation of inter instruction cost has been minimized by taking it as certain percent of total energy. Percentage error between actual and estimated energy is found to be less than 5%.

Design of a high speed drawing frame monitoring system based on IoT using MQTT protocol

Online monitoring for sliver quality is an important part of the drawing process. This paper presents a high-speed drawing frame monitoring system based on Internet of Things (IoT) using Message Queuing Telemetry Transport (MQTT) protocol, which consists of drawing frame IoT terminal equipment, the cloud server and PC or mobile terminal equipments. Drawing frame IoT terminal equipment takes Cortex-A7 and Cortex-M4 of series of i.MX7 as its control cores. The A7 processor publishes IoT data as a communication gateway while the M4 processor collects sensor data and executes local on-line detection program. Two processors run Linux and FreeRTOS as operating system respectively, and the data exchange between them adopt rpmsg pattern. The communication gateway using MQTT publishes data of the IoT terminal to the cloud server for remoting monitoring and intelligent diagnosis, when the local on-line detection system aims at acquiring real-time status of the sliver on drawing frame. Users can check the real-time status of the drawing frame at the subscription end of IoT and on the computer or mobile phone end by subscribing message by theme. Experiments show that the system operates with reliability, and is good compatible with other devices because of the modular design. The adoption of this system can promote the digitization and the intelligentialize of the drawing frame.

Performance Test Results of a Precision Data Acquisition and Control Platform for 200°C+ High Temperature Environments

Abstract In recent years there has been an increasing selection of commercially available electronic components specified for very high temperature (200C+) operation, driven by the needs of harsh-environment applications such as oil and gas exploration/production, aerospace, heavy industrial, and automotive. However, there remains a significant technical challenge to integrate these components into reliable, high performance systems. We previously presented a complete reference design of a precision multichannel sensor data acquisition and control system rated to 200C, including characterized hardware, firmware, and software. The design is based around low power 16 bit SAR ADCs and an ARM® Cortex®-M0 processor and is optimized for high resolution and high throughput measurements while maintaining low power and a small footprint. In this paper we present the test results of this system over temperature. The reference platform is available off the shelf, including hardware design files, processor firmware source code, and PC software for data logging and display, providing engineers a rapid development tool for prototyping and a faster path to production for complex harsh-environment applications.

Smart Grid System Architecture over Embedded System using Internet of Things

This paper refers advanced smart Grid architecture executed with the help of internet of things. Internet of things contains a set for Web administrations have highest priority over internet enabled embedded devices. The Web program on computer could go an interface over service provided by this web of things. Those Embedded devices such as ARM Cortex M3 Processor built gadgets with Ethernet abilities. CMSIS Real time embedded systems will be utilized to transform control on each on these electronic gadgets. LwIP Protocol stack may be actualized on highest priority on each of these units along with the IP connectivity. Those Web interfaces gatherings give us constant majority of the data for each of the energy meters that are introduced with respect to webpage and communicate with web units utilizing MODBUS correspondence protocol. Constant real time energy source scheduling and selection, energy association and separation are some of the administrations that would be given with a on-line verifed client. The inserted embedded systems lab framework at the TIFAC center to 3G/4G correspondence toward national institute of science and technology might have been utilized for that equipment testing of the embedded modules. We were mostly helped by the product developers during NIST innovation consultancy administrations over outlining those web provisions and also interface for our Web of things construction modeling.

Performance Evaluation of SHA-3 Final Round Candidate Algorithms on ARM Cortex–M4 Processor

SHA-3 was an open competition initiated by NIST to design new generation of hash functions. This competition was a necessity to overcome the challenges imposed by multiple attacks on MDx family of hash functions including SHA-0 and SHA-1. For this competition, NIST announced a reference platform which did not cover Embedded and Mobile machines. This paper compares the performance of SHA-3 final round candidate algorithms on ARM Cortex-M4 processor (embedded processor) and presents the results. Cycles per Byte is used as performance metric. Cortex-M4 based Stellaris® LM4F232 Evaluation Board (EK-LM4F232) from Texas Instruments is used for performance evaluation.

An Efficient ECG Lossless Compression System for Embedded Platforms With Telemedicine Applications

This paper presents a method for wireless ECG compression and zero lossless decompression using a combination of three different techniques in order to increase storage space while reducing transmission time. The first technique used in the proposed algorithm is an adaptive linear prediction; it achieves high sensitivity and positive prediction. The second technique is content-adaptive Golomb–Rice coding, used with a window size to encode the residual of prediction error. The third technique is the use of a suitable packing format; this enables the real-time decoding process. The proposed algorithm is evaluated and verified using over 48 recordings from the MIT-BIH arrhythmia database, and it shown to be able to achieve a lossless bit compression rate of $2.83{\times}$ in Lead V1 and $2.77{\times}$ in Lead V2. The proposed algorithm shows better performance results in comparison to previous lossless ECG compression studies in real time; it can be used in data transmission methods for superior biomedical signals for bounded bandwidth across e-health devices. The overall compression system is also built with an ARM M4 processor, which ensures high accuracy performance and consistent results in the timing operation of the system.

Circuit and System Designs of Ultra-Low Power Sensor Nodes With Illustration in a Miniaturized GNSS Logger for Position Tracking: Part II—Data Communication, Energy Harvesting, Power Management, and Digital Circuits

This two-part paper reviews recent innovations in circuit design that have accelerated the miniaturization of sensor nodes. In this second part of the paper, we focus on key building blocks of miniaturized sensor nodes, such as data transceivers, energy harvesters, power management units, and digital logic circuits. System level design considerations are also discussed to provide guidelines for the design of a miniaturized system. As an example prototype design, a 2.7-cm3 global navigation satellite system (GNSS) logger is proposed. This paper includes a die-stacked sensor platform composed of an ARM cortex M0 processor, energy harvester, power management unit, solar cell, optical receiver, sensor layer, and RF transmitter that exploits the discussed design techniques for ultra-low power operation. The GNSS logger can store GNSS signals of >1 k positions on a single battery charging without additional energy harvesting.

A Simplified Method for Instruction Level Energy Estimation for Embedded System

Embedded systems are used extensively in all spheres of life. Size, cost and power are the major issues in design and marketing of these products. In embedded system, the processor has to perform given task repeatedly. Power optimization need to be achieved not only at hardware level, but also at software level. Because software power contributes substantially in overall power consumption of embedded system. In this paper, a simplified method for instruction level energy estimation is presented for ARM Cortex M4 processor. Results obtained are compared with micro benchmark programs. The result shows less than -2% error in energy consumption estimation.

A Simplified Method for Instruction Level Energy Estimation for Embedded System

Embedded systems are used extensively in all spheres of life. Size, cost and power are the major issues in design and marketing of these products. In embedded system, the processor has to perform given task repeatedly. Power optimization need to be achieved not only at hardware level, but also at software level. Because software power contributes substantially in overall power consumption of embedded system. In this paper, a simplified method for instruction level energy estimation is presented for ARM Cortex M4 processor. Results obtained are compared with micro benchmark programs. The result shows less than -2% error in energy consumption estimation.

Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure

In this paper, we present a novel coarse-grained technique for monitoring online the bias temperature instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during standby operations, the value of which depends on the threshold voltage of the CMOS devices in a power-gated design (PGD). It does not require any distributed sensors, because the virtual-power-network is already distributed in a PGD. It consists of a hardware block for measuring the discharge time concurrently with normal standby operations and a processing block for estimating the BTI aging status of the PGD according to collected measurements. Through SPICE simulation, we demonstrate that the BTI aging estimation error of the proposed technique is less than 1% and 6.2% for PGDs with static operating frequency and dynamic voltage and frequency scaling, respectively. Its area cost is also found negligible. The power gating minimum idle time (MIT) cost induced by the energy consumed for monitoring the discharge time is evaluated on two scalar machine models using either x86 or ARM instruction sets. It is found less than $1.3\times $ and $1.45\times $ the original power gating MIT, respectively. We validate the proposed technique through accelerated aging experiments conducted with five actual chips that contain an ARM cortex M0 processor, manufactured with a 65 nm CMOS technology.

Flying-Domain DC–DC Power Conversion

This paper presents a new power conversion method that can achieve both high efficiency and high power density by obviating the need for an area-consuming flying capacitor and replacing it with a flying digital load. The proposed flying-domain (FD) power conversion concept enables higher conversion efficiency than a conventional switched-capacitor converter by reducing charge-sharing and bottom-plate parasitic losses, while also enabling higher power density by eliminating the area occupied by the flying passive itself. This paper presents state-space analysis that shows that the proposed FD concept is well posed and reaches a valid steady state, while also presenting experimental results of several FD converters implemented in 180 nm SOI. With no flying passives, the fabricated FD converter achieves a peak efficiency of 99.2%, delivers up to 11.8 W/mm2 (2.3 W/mm2 with decoupling) at 91.7% efficiency, and can directly power a cofabricated Cortex M0 processor that communicates via flying I/O level shifters.