LUT-based Field Programmable Gate Arrays Research Articles

FERMAT: FPGA energy reduction method by approximation theory

Today’s field programmable gate arrays (FPGAs) offer a significant computational power and are commonly used in modern commercial digital designs. However, they generally suffer from a large power consumption, which makes them unfit for battery-operated handheld devices. This paper addresses this problem by bringing the notion of approximate computing into the realm of reconfigurable devices such as LUT-based FPGAs. The proposed approximation is done by altering LUT contents in an exact design. The impact of this kind of approximation on output accuracy as well as design power consumption will be discussed. Once the theoretical foundation is established, we propose a method, called FERMAT (FPGA Energy Reduction Method by Approximation Theory), which takes an exact FPGA design and converts it into an approximated equivalent with a considerably reduced power consumption given a maximum error constraint. The effectiveness of FERMAT is shown by measuring the actual power consumption of an FPGA device performing an image processing application. Experimental results show about 8.5% power saving with an imperceptible loss in image quality.

Low Power QC-LDPC Decoder Based on Token Ring Architecture

The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimization. Then the clock gating of the decoder building blocks allows for a significant reduction in energy consumption without deterioration in other parameters of the decoder, particularly its error correction performance. We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder with the proposed architecture can be designed. The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature.

Technology Mapping of FSM Oriented to LUT-Based FPGA

The main purpose of the paper is to present technology mapping of FSM (finite state machine) oriented to LUT (look-up table)-based FPGA (field-programmable gate array). The combinational part of an automaton, which consists of a transition block and an output block, was mapped in LUT-based logic blocks. In the paper, the idea of carrying out the combinational part of FSM was presented and leads to the reduction of the number of LUTs needed to carry out an automaton. The essence of this method is a simultaneous synthesis of the whole combinational block described in the form of multi-output function. The proposed idea makes it possible to conduct decomposition that may enable to share logic blocks, which can lead to the reduction of using resources of FPGA. The decomposition process was conducted using the analyzed DECOMP system. The effectiveness of the proposed idea of the FSM description was also confirmed by conducting decomposition with the usage of the ABC system. The obtained results prove the efficiency of the proposed synthesis method of FSM in comparison with the separate synthesis of a transition block and an output block.

An alternative carry-save arithmetic for new generation field programmable gate arrays

In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than conventional binary multiply-add implementations.

Le syndrome de Pancoast et Tobias malin (à propos de 40 cas)

A group-testing-based fault resolution is incorporated into SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) to provide an evolvable hardware system with self-healing and self-organizing properties. The proposed approach employs adaptive group testing techniques to autonomously maintain FPGA resource viability information as an organic means of transient and permanent fault resolution. Reconfigurability of the SRAM-based FPGA is leveraged to locate faulty logic resources which are successively excluded by group testing using alternate device configurations. This simplifies the system architect’s role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance vs. availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an observer–controller model. The proposed group testing method operates on the output response produced for real-time operational inputs, which eliminates the need for dedicated test vectors. The proposed system was demonstrated using a Data Encryption Standard (DES) core on 4-input and 6-input LUT-based Xilinx FPGA models. With a single simulated stuck-at fault, the system identifies a completely validated replacement configuration within a few test stages. Results also include approaches for optimizing group size, resource redundancy, and availability. The approach demonstrates a readily-implemented yet robust organic hardware application that features a high degree of autonomous self-control.

Self-healing reconfigurable logic using autonomous group testing

A group-testing-based fault resolution is incorporated into SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) to provide an evolvable hardware system with self-healing and self-organizing properties. The proposed approach employs adaptive group testing techniques to autonomously maintain FPGA resource viability information as an organic means of transient and permanent fault resolution. Reconfigurability of the SRAM-based FPGA is leveraged to locate faulty logic resources which are successively excluded by group testing using alternate device configurations. This simplifies the system architect’s role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance vs. availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an observer–controller model. The proposed group testing method operates on the output response produced for real-time operational inputs, which eliminates the need for dedicated test vectors. The proposed system was demonstrated using a Data Encryption Standard (DES) core on 4-input and 6-input LUT-based Xilinx FPGA models. With a single simulated stuck-at fault, the system identifies a completely validated replacement configuration within a few test stages. Results also include approaches for optimizing group size, resource redundancy, and availability. The approach demonstrates a readily-implemented yet robust organic hardware application that features a high degree of autonomous self-control.

Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs

This paper presents complexity analysis [both in application-specific integrated circuits (ASICs) and on field-programmable gate arrays (FPGAs)] and efficient FPGA implementations of bit parallel mixed Karatsuba-Ofman multipliers (KOM) over GF(2m) . By introducing the common expression sharing and the complexity analysis on odd-term polynomials, we achieve a lower gate bound than previous ASIC discussions. The analysis is extended by using 4-input/6-input lookup tables (LUT) on FPGAs. For an arbitrary bit-depth, the optimum iteration step is shown. The optimum iteration steps differ for ASICs, 4-input LUT-based FPGAs and 6-input LUT-based FPGAs. We evaluate the LUT complexity and area-time product tradeoffs on FPGAs with different computer-aided design (CAD) tools. Furthermore, the experimental results on FPGAs for bit parallel modular multipliers are shown and compared with previous implementations. To the best of our knowledge, our bit parallel multipliers consume the least resources among known FPGA implementations to date.

Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits

Experimental results show that parallel programs can be evolved more easily than sequential programs in genetic parallel programming (GPP). GPP is a novel genetic programming paradigm which evolves parallel program solutions. With the rapid development of lookup-table-based (LUT-based) field programmable gate arrays (FPGAs), traditional circuit design and optimization techniques cannot fully exploit the LUTs in LUT-based FPGAs. Based on the GPP paradigm, we have developed a combinational logic circuit learning system, called GPP logic circuit synthesizer (GPPLCS), in which a multilogic-unit processor is used to evaluate LUT circuits. To show the effectiveness of the GPPLCS, we have performed a series of experiments to evolve combinational logic circuits with two- and four-input LUTs. In this paper, we present eleven multi-output Boolean problems and their evolved circuits. The results show that the GPPLCS can evolve more compact four-input LUT circuits than the well-known LUT-based FPGA synthesis algorithms.

Improvements to Technology Mapping for LUT-Based FPGAs

This paper presents several orthogonal improvements to the state-of-the-art lookup table (LUT)-based field-programmable gate array (FPGA) technology mapping. The improvements target the delay and area of technology mapping as well as the runtime and memory requirements. 1) Improved cut enumeration computes all K-feasible cuts, without pruning, for up to seven inputs for the largest Microelectronics Center of North Carolina benchmarks. A new technique for on-the-fly cut dropping reduces, by orders of magnitude, the memory needed to represent cuts for large designs. 2) The notion of cut factorization is introduced, in which one computes a subset of cuts for a node and generates other cuts from that subset as needed. Two cut factorization schemes are presented, and a new algorithm that uses cut factorization for delay-oriented mapping for FPGAs with large LUTs is proposed. 3) Improved area recovery leads to mappings with the area, on average, 6% smaller than the previous best work while preserving the delay optimality when starting from the same optimized netlists. 4) Lossless synthesis accumulates alternative circuit structures seen during logic optimization. Extending the mapper to use structural choices reduces the delay, on average, by 6% and the area by 12%, compared with the previous work, while increasing the runtime 1.6 times. Performing five iterations of mapping with choices reduces the delay by 10% and the area by 19% while increasing the runtime eight times. These improvements, on top of the state-of-the-art methods for LUT mapping, are available in the package ABC

Optimality Study of Logic Synthesis for LUT-Based FPGAs

Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few years has slowed considerably (with some notable exceptions). It seems natural to then question whether the current logic-synthesis and technology-mapping algorithms for FPGA designs are producing near-optimal solutions. Although there are many empirical studies that compare different FPGA synthesis/mapping algorithms, little is known about how far these algorithms are from the optimal (recall that both logic-optimization and technology-mapping problems are NP-hard, if we consider area optimization in addition to delay/depth optimization). In this paper, we present a novel method for constructing arbitrarily large circuits that have known optimal solutions after technology mapping. Using these circuits and their derivatives (called Logic synthesis Examples with Known Optimal (LEKO) and Logic synthesis Examples with Known Upper bounds (LEKU), respectively), we show that although leading FPGA technology-mapping algorithms can produce close to optimal solutions, the results from the entire logic-synthesis flow (logicoptimization+mapping) are far from optimal. The LEKU circuits were constructed to show where the logic synthesis flow can be improved, while the LEKO circuits specifically deal with the performance of the technology mapping. The best industrial and academic FPGA synthesis flows are around 70 times larger in terms of area on average and, in some cases, as much as 500 times larger on LEKU examples. These results clearly indicate that there is much room for further research and improvement in FPGA synthesis

SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits

In this paper, we present the condition for the effective wire addition in Look-Up-Table-based (LUT-based) field programmable gate array (FPGA) circuits, and an optimization procedure utilizing the effective wire addition. Each wire has different characteristics, such as delay and power dissipation. Therefore, the replacement of one critical wire for the circuit performance with many non-critical ones, i.e., many-addition-for-one-removal (m-for-1) is sufficiently useful. However, the conventional logic optimization methods based on sets of pairs of functions to be distinguished (SPFDs) for LUT-based FPGA circuits do not make use of the m-for-1 manipulation, and perform only simple replacement and removal, i.e., the one-addition-for-one-removal (1-for-1) manipulation and the no addition-for-one-removal (0-for-1) manipulation, respectively. Since each LUT can realize an arbitrary internal function with respect to a specified number of input variables, there is no sufficient condition at the logic design level for simple wire addition. Moreover, in general, simple addition of a wire has no effects for removal of another wire, and it is important to derive the condition for non-simple and effective wire addition. We found the SPFD-based condition that wire addition is likely to make another wire redundant or replaceable, and developed an optimization procedure utilizing this effective wire addition. According to the experimental results, when we focused on the delay reduction of LUT-based FPGA circuits, our method reduced the delay by 24.2% from the initial circuits, while the conventional SPFD-based logic optimization and the enhanced global rewiring reduced it by 14.2% and 18.0%, respectively. Thus, our method presented in this paper is sufficiently practical, and is expected to improve the circuit performance.

Highly efficient, limited range multipliers for LUT-based FPGA architectures

A novel design technique for deriving highly efficient multipliers that operate on a limited range of multiplier values is presented. Using the technique, Xilinx Virtex field programmable gate array (FPGA) implementations for a discrete cosine transform and poly-phase filter were derived with area reductions of 31%-70% and speed increases of 5%-35% when compared to designs using general-purpose multipliers. The technique gives superior results over other fixed coefficient methods and is applicable to a range of FPGA technologies.

Area-optimized implementation of quadrature direct digital frequency synthesizers on LUT-based FPGAs

This paper deals with an field-programmable gate array (FPGA)-implementation of quadrature direct digital frequency synthesizers (QDDFS), and, in particular, with those based on CORDIC, interpolation, and memory compression. We provide results of maximum throughput, i.e., 302 MHz, when mapping QDDFS architectures on current look-up-table (LUT)-based field-programmable technology. We take into account those VLSI design guidelines that work well on FPGAs and architectural considerations to design efficient (in terms of area and throughput) QDDFS, up to 56% faster than commercial cores. Finally, we present a design map that combines the phase-to-amplitude techniques reviewed in this paper so as to minimize the overall area.

Technology mapping algorithm for heterogeneous field programmable gate arrays

To maximise device utilisation, a heterogeneous field programmable gate array (FPGA) provides either an array of homogeneous lookup tables (LUTs) of different sizes or an array of physically heterogeneous LUTs. It is shown that heterogeneous FPGAs have a significant number of desirable attributes. A technology mapping algorithm is proposed for heterogeneous FPGAs. The technology mapping problem is first formulated as a flow network problem. Then, an algorithm based on the min-cost max-flow algorithm is presented to select a proper set of feasible LUTs for various objectives. Two objectives: (i) the minimum number of LUTs; and (ii) the total area composed of LUTs and routing area are discussed. The algorithm is tested on the MCNC benchmark circuits and produces better characteristics than existing LUT-based FPGA mapping algorithms.

Testing Configurable LUT-Based FPGAs

A novel approach to testing lookup table (LUT) based field programmable gate arrays (FPGAs) is proposed in this paper. A general structure for the basic configurable logic array blocks (CLBs) is assumed. We group k CLBs in the column into a cell, where k denotes the number of inputs of an LUT. The whole chip is configured as a group of one-dimensional iterative logic arrays of cells. We assume that in each linear cell array, there is at most one faulty cell, and that multiple faulty CLBs in the same cell can be detected. For the LUT, a fault may occur at the memory matrix, decoder, input or output lines. The switch stuck-on and stuck-off fault models are adopted for multiplexers. New conditions for C-testability of programmable reconfigurable arrays are also derived. Our idea is to configure the cells so as to make each cell function bijective. This property is helpful for applying pseudoexhaustive test patterns to each cell and propagating errors to the observable outputs. In order to detect all the faults defined, k+2 configurations are required, and the resulting number of test patterns is 2(superscript k). A novel built-in self-test structure is also proposed in this paper. The input patterns can be easily generated with a k-bit counter. The number of configurations for our BIST structures is 2k+4. Our BIST approaches also have the advantage of requiring fewer hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, three test sessions are required. However, the maximum number of configurations for diagnosing a faulty CLB is k+4.

ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping

In this paper, we propose an iterative area/performance tradeoff algorithm for look-up table (LUT)-based field programmable gate array (FPGA) technology mapping. First, it finds an area-optimized, performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can efficiently provide a complete set of mapping solutions from the area-optimized one to the performance-optimized one for the given design. Furthermore, these two extreme solutions produced by our algorithm outperform the results provided by most existing algorithms. Therefore, our algorithm is very useful for the timing-driven, LUT-based FPGA synthesis.

Direct mapping of RTL structures onto LUT-based FPGA's

The problem of mapping synthesized RTL structures onto look-up table (LUT)-based field programmable gate arrays (FPGAs) is addressed in this paper. The key distinctive feature of this work is a novel approach to perform the mapping by utilizing the iterative nature of the data path components. The approach exploits the regularity of data path components by slicing the components and mapping slices of one or more connected components together. This is in contrast to other FPGA mapping techniques which start from Boolean networks. Both cost optimal and delay optimal mappings are supported. The objective in cost optimal mapping is to cover a given data path network with minimum number of CLBs. Similarly in delay optimal mapping, the objective is to reduce the number of CLB levels in the critical combinational logic paths. Implementation of these mapping techniques with LUT based FPGAs as target technology results in a significant reduction in cost (CLB count) and critical path delays (CLB levels).

Tradeoff literals against support for logic synthesis of LUT-based FPGAs

The paper deals with logic synthesis of lookup-table (LUT) based field-programmable gate arrays (FPGAs). Because each LUT can implement any k input Boolean function with the same area cost, the optimisation criterion of literal count, generally used in other multi-level logic synthesis methods, is not suitable for LUT-based technologies. Therefore a new logic optimisation criterion is proposed, which trades off literals against support. Based on this criterion, five logic operations in logic optimisation are analysed, and made to evaluate the circuit cost in accordance with the target technology. Using these techniques of logic optimisation, a good starting point for technology mapping of LUT-based FPGAs has been obtained. In the technology mapping phase, LUT-directed decomposition is applied. Experimental results indicate that synthesised circuits are much smaller and more routable than the circuits synthesised by other tools.

LUT-based FPGA technology mapping under arbitrary net-delay models

The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. Most existing algorithms for performance-driven technology mapping for Lookup-table (LUT)-based FPGA designs are based on the unit-delay model. In this paper we study the technology mapping problem under arbitrary net-delay models. We show that if the net delay can be determined or estimated before mapping, the problem can be optimally solved in polynomial time based on efficient network flow computation. We have implemented the algorithm and tested it on a number of MCNC benchmark examples.

FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. In the past few years, a number of heuristic algorithms have been proposed for technology mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean networks and little is known about how far their solutions are away from the optimal ones. This paper presents a theoretical breakthrough which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time. A key step in our algorithm is to compute a minimum height K-feasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUT's by maximizing the volume of each cut and by several post-processing operations. Based on these results, we have implemented an LUT-based FPGA mapping package called FlowMap. We have tested FlowMap on a large set of benchmark examples and compared it with other LUT-based FPGA mapping algorithms for delay optimization, including Chortle-d, MIS-pga-delay, and DAG-Map. FlowMap reduces the LUT network depth by up to 7% and reduces the number of LUT's by up to 50% compared to the three previous methods. >