Low Programming Voltage Research Articles

Laser writing of memristive logic gates and crossbar arrays

Memristor-based logic circuits are gaining a lot of attention due to the potential for high logic density hardware and novel in-memory computing applications. Readily available methods for fabricating of memristor logic structures that are suitable for integration with conventional computer hardware are a growing need. This work presents a direct laser writing process capable of rapidly fabricating memristor logic circuits by laser irradiation of metal salt precursor solutions. Planar memristor patterns are fabricated, and their I–V response is characterized. Boolean logic gates are fabricated from planar memristor pairs that exhibit low programming voltages and rapid switching. Cu/Cu2O/Cu and Ag/Cu2O/Cu memristors are also fabricated in crossbar arrays, showing the ability to be programmed to multiple resistance states through ultrashort voltage pulses. The devices also show the potential to have high endurance and nonvolatile resistance state retention.

Analysis of Mechanical Stress on Fowler-Nordheim Tunneling for Program Operation in 3D NAND Flash Memory

This study investigated the relationship between mechanical stress and program efficiency in three-dimensional (3D) NAND flash memory devices. A stacked memory array transistor (SMArT) 3D NAND flash structure was modeled using a technology computer-aided design (TCAD) simulation. The mechanical stress distribution in the device depended on the deposition temperature (TD) of the constituent material. In particular, the TD of tungsten (TD,W) dominated the mechanical stress. The tensile stress on the polycrystalline silicon (poly-Si) channel increased as the TD,W decreased, and the compressive stress on the tunneling oxide (Tox) decreased. Consequently, the barrier height between Tox and poly-Si, and the effective electron mass decreased as the electric field in the Tox increased. These changes significantly increased the Fowler-Nordheim (FN) tunneling process and program efficiency, indicating the crucial performance of 3D NAND flash. Moreover, the mechanical stress caused by the differences in TD,W improved the program efficiency at a lower program voltage (VPGM). Therefore, a change in the mechanical stress based on decreasing TD,W improved the program efficiency through a higher FN tunneling process.

Uniform Oxide Layer Integration in Amorphous IGZO Thin Film Transistors for Enhanced Multilevel-Cell NAND Memory Performance

In this work, the implementation of HfZrO layers for the tunneling, charge trapping, and blocking mechanisms within the device offer benefits in terms of programmability and data retention. This configuration has resulted in a memory device that can achieve a significant difference in threshold voltage of around 2 V per memory level. This difference is crucial for effectively distinguishing between multiple levels of memory in MLC applications. Additionally, the device operates at low programming voltages below 14 V. Furthermore, the device showcases impressive endurance and data retention capabilities, maintaining a large memory window over extended periods and under varying temperature conditions. The advancement in the a-IGZO-based memory device, characterized by its uniform oxide stacking, presents a viable solution to the industry’s requirement for memory storage options that are efficient, dependable, and economical.

A String-Select-Line Separation Patterning Scheme for Low Voltage and High-Speed Program Operation in 3D NAND Flash Memory with Separated Source-Line

A String-Select-Line Separation Patterning Scheme for Low Voltage and High-Speed Program Operation in 3D NAND Flash Memory with Separated Source-Line

BEOL-Compatible Bilayer Reprogrammable One-Time Programmable Memory for Low-Voltage Operation

In this work, an engineered submicrometer-scale bilayer stacking in via-type one-time programmable (OTP) memory and self-rectified resistive switching memory [resistive random access memory (ReRAM)] is demonstrated. The current development has achieved that co-existing memory functionality (OTP and ReRAM) with mitigating scaling requirement (fuse voltage trending with via size scaling), low fabrication complexity [via-fuse vs. gate-dielectric anti-fuse (AF)], and match with the current metal fuse technology ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$ </tex-math></inline-formula> 2 V). In addition, an electrode engineered has been proposed to realize low programming voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula> 1.9 V) in via-fuse OTP featuring by metal–insulator–metal advanced back-end-of-line (BEOL) process with ruthenium materials. The impact of via-size, programming window, stacked structures, and integration capability has been extensively studied. Our results provide a pathfinding of high density, integration capability, low programming voltage, multifunctionality between programmable read-only memory (PROM), and resistive switching memory co-existing in future embedded applications.

Dynamical Effects of Excess Carriers on SOI FeFET Memory Device Operations

We study the carrier dynamics of memory program (PGM) and readout operations for an n-type silicon-on-insulator (SOI) ferroelectric field-effect transistor (FeFET) through TCAD simulations. We found that gate-induced drain leakages (GIDL) during the PGM operation with large negative gate biases can result in excess hole concentrations as high as 7.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10^{{20}}$ </tex-math></inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-{3}}$ </tex-math></inline-formula> in the potential well formed in the SOI channel. The hole accumulation causes a large electric field across the ferroelectric (FE) layer and results in a polarization boost at a low PGM voltage. For a nano-scale SOI channel, the retention time of the excess holes can exceed microseconds according to our simulations. The outflow of the excess holes leads to a transient effect in the drain current during the readout operation, and we observed additional retention effects for the FeFET memory window due to the hole dynamic effects on the electrostatics and the FE polarizations. While the excess holes result in a ~100 ps delay in the readout phase before a large read margin can be detected, they have boosted the PGM speed and polarization window. The boosted polarization can be retained for milliseconds, and potentially beyond, resulting in an appreciable ON/OFF ratio during readout. Therefore, such effects can be utilized for low-power memory applications through proper SOI FeFET designs with the awareness of excess carrier dynamics.

Ferroelectric Field-Effect Transistors for Binary Neural Network With 3-D NAND Architecture

Ferroelectric field-effect transistor (FeFET) can be operated as a nonvolatile memory device with low programming voltage based on polarization. In particular, it can be used as a synaptic device in a neuromorphic system based on the NAND flash array structure. We demonstrate a Hf0.5Zr0.5O2 (HZO)-based FeFET device fabricated on a silicon-on-insulator (SOI) substrate with high ON/OFF ratio and reliability characteristics. The HZO-based FeFET is utilized as a synaptic device based on the 3-D NAND architecture. It is verified with the binarization of input–output signals and weight value for efficient vector–matrix multiplication (VMM) operation using the 3-D NAND architecture. In addition, a neural network layer-mapping method increasing synaptic cell efficiency is proposed. A system-level simulation is performed based on the FeFET single-device experimental data. The VMM operation is verified through the SPICE Berkeley short-channel IGFET model (BSIM), and off-chip (ex-situ) learning with binary neural network (BNN) is performed for the Modified National Institute of Standards and Technology Database MNIST and fashion-MNIST data. The results confirm that the proposed FeFET-based BNN can perform accurate VMM operations and is robust to variations due to the binary weight state.

SiO2 Fin-Based Flash Synaptic Cells in AND Array Architecture for Binary Neural Networks

An oxide fin-based AND flash memory synaptic device is proposed and fabricated using a spacer patterning technology for a hardware-based binary neural network (BNN). A fin-like curved channel structure provides local electric field enhancement, which improves programming efficiency compared to planar-type flash synaptic devices. The fin-based AND flash cell exhibits a high on/off current ratio (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> ) with sub-pA off current, and a low programming voltage (< 9 V) is used to achieve a sufficient dynamic range of synaptic weights (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ) for BNNs. Furthermore, a hardware-based BNN using novel two cell-based synaptic devices arranged in AND array architecture is proposed to implement parallel XNOR operation and bit-counting. Proposed BNN using the synapse model with measured dynamic range and retention property shows only < 0.5 % degradation of classification accuracy compared to the baseline accuracy, which is suitable to perform off-chip event-driven computation using parallel read-out operations.

Analysis of the Effect of Residual Holes on Lateral Migration During the Retention Operation in 3-D NAND Flash Memory

In this article, we analyze the effect of residual holes on lateral migration (LM) mechanism at low program voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\mathrm {PGM}}$ </tex-math></inline-formula> ) during the retention operation in 3-D NAND flash memories. In the previous study, we suggested that the failure mechanism by the residual holes is a major charge loss component as the program verify (PV) level lowered. Through TCAD simulation, we analyzed the impact of residual holes on LM in detail, and this influence was redefined with the focus of electron movement during the retention operation. In addition, we separated the LM affected by adjacent cells into another failure mechanism and analyze the effect of residual holes and adjacent cells on retention characteristics at various <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\mathrm {PGM}}$ </tex-math></inline-formula> using the three failure mechanisms associated with LM. For low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\mathrm {PGM}}$ </tex-math></inline-formula> and the specific pattern, the retention characteristics are also affected by the number of holes stored in adjacent cells. In this case, it was founded that the Z-interference component is considered in the stretched exponential function through the analysis of the erase time and spacer length.

Unipolar Parity of Ferroelectric-Antiferroelectric Characterized by Junction Current in Crystalline Phase Hf1-xZrxO2 Diodes.

Ferroelectric (FE) Hf1−xZrxO2 is a potential candidate for emerging memory in artificial intelligence (AI) and neuromorphic computation due to its non-volatility for data storage with natural bi-stable characteristics. This study experimentally characterizes and demonstrates the FE and antiferroelectric (AFE) material properties, which are modulated from doped Zr incorporated in the HfO2-system, with a diode-junction current for memory operations. Unipolar operations on one of the two hysteretic polarization branch loops of the mixed FE and AFE material give a low program voltage of 3 V with an ON/OFF ratio >100. This also benefits the switching endurance, which reaches >109 cycles. A model based on the polarization switching and tunneling mechanisms is revealed in the (A)FE diode to explain the bipolar and unipolar sweeps. In addition, the proposed FE-AFE diode with Hf1−xZrxO2 has a superior cycling endurance and lower stimulation voltage compared to perovskite FE-diodes due to its scaling capability for resistive FE memory devices.

Low‐Voltage Electrochemical LixWO3 Synapses with Temporal Dynamics for Spiking Neural Networks

Neuromorphic computing has the great potential to enable faster and more energy‐efficient computing by overcoming the von Neumann bottleneck. However, most emerging nonvolatile memory (NVM)‐based artificial synapses suffer from insufficient precision, nonlinear synaptic weight update, high write voltage, and high switching latency. Moreover, the spatiotemporal dynamics, an important temporal component for cognitive computing in spiking neural networks (SNNs), are hard to generate with existing complementary metal–oxide–semiconductor (CMOS) devices or emerging NVM. Herein, a three‐terminal, LixWO3‐based electrochemical synapse (LiWES) is developed with low programming voltage (0.2 V), fast programming speed (500 ns), and high precision (1024 states) that is ideal for artificial neural networks applications. Time‐dependent synaptic functions such as paired‐pulse facilitation (PPF) and temporal filtering that are critical for SNNs are also demonstrated. In addition, by leveraging the spike‐encoded timing information extracted from the short‐term plasticity (STP) behavior in the LiWES, an SNNs model is built to benchmark the pattern classification performance of the LiWES, and the result indicates a large boost in classification performance (up to 128×), compared with those NO‐STP synapses.

Overcoming bit loss mechanism in self‐amplified multilevel silicon‐oxide‐nitride‐oxide‐silicon memory cell

AbstractThis work reports on the triple‐level NAND flash cell realized from self‐amplified (SA) double gate (DG) tunneling‐based silicon‐oxide‐nitride‐oxide‐silicon (T‐SONOS) memory device. Through calibrated simulations, we show that capacitive coupling between the front gate and back gate can be used to store eight states (or 3 bits), that is, from “000” to “111,” in a T‐SONOS memory device with the readable difference between each level at lower programming voltages. The performance of the multilevel T‐SONOS cell is compared with the inversion mode SONOS (I‐SONOS) multilevel cell. Results highlight that gate length (Lg) scaling from 100 to 25 nm significantly deteriorates the threshold voltage associated with the lower states in the I‐SONOS multilevel cell. However, highly stable eight states can be achieved in a multi‐level T‐SONOS cell at Lg = 25 nm. The results highlight the potential of SA T‐SONOS cell for designing multilevel memory cell arrays.

Effect of the switching layer on CBRAM reliability and benchmarking against OxRAM devices

We thoroughly benchmark the reliability of Cu-based CBRAM stacks with different switching layers against state-of-the-art OxRAM stacks. We optimize the switching conditions for maximizing the endurance lifetime in three CBRAM stacks, outlining the impact of the switching layer on the energy required for the switching operation and on the memory window. We show that CBRAM provide a larger memory window than OxRAM, but the switching energy is systematically higher, and the endurance lifetime is shorter. We also demonstrate that the larger memory window of CBRAM degrades over time and is thus only an apparent advantage with respect to OxRAM. Therefore, this study reveals that OxRAM devices investigated in this work are more suitable candidates than for applications targeting long data retention and low programming voltage.

A Low Program Voltage Enabled Flash like AlGaN/GaN Stack Layered MIS-HEMTs Using Trap Assisted Technique

In this paper, a flash like Al2O3/SiO2 stacked layer AlGaN/GaN-based metal insulator semiconductor high electron mobility transistor (MIS-HEMT) was fabricated using trap assisted technique. The MIS-HEMT showed a large positive shifting of threshold voltage (∆VTH) of 4.6 V after applying a low program voltage (VP) of 3 V, resulting in a very low threshold voltage of −0.3 V with a decent maximum drain current (IDMAX) of 575 mA mm−1. A ultraviolet-ozone (UV/O3) surface treatment was done prior to gate dielectric deposition to produce a thin gallium oxynitride (GaOXNY) layer at GaN/oxide interface, which correspondingly acts as a charge trapping layer, resulting in the reduction in VP. The capacitance-voltage (C–V) measurements revealed that the traps contributing to the significant positive shifting of VTH had a density of 5.7 × 1012 cm−2. These traps were attributed to the border or oxide defects. A significant reduction in gate leakage current (IG) of more than three orders of magnitude was found in MIS-HEMT, due to the high quality Al2O3/SiO2 stack gate dielectric layer compared to conventional HEMT. The flash like stack layered programmed MIS-HEMT exhibited a GMMAX of 123 mS mm−1, on-off ratio of 1.7 × 107, subthreshold slope of 121 mV dec−1 with a reduced gate leakage current of 7.5 × 10−9 A mm−1.

Electrical Conduction Characteristic of a 2D MXene Device with Cu/Cr2C/TiN Structure Based on Density Functional Theory.

The electronic structure and the corresponding electrical conductive behavior of the Cu/Cr2C/TiN stack were assessed according to a newly developed first-principle model based on density functional theory. Using an additional Cr2C layer provides the metal-like characteristic of the Cu/Cr2C/TiN stack with much larger electrical conduction coefficients (i.e., mobility, diffusivity, and electrical conductivity) than the conventional Ag/Ti3C2/Pt stack due to the lower activation energy. This device is therefore capable of offering faster switching speeds, lower programming voltage, and better stability and durability than the memristor device with conventional Ti3C2 MXene.

Low power high speed 3-bit multilevel resistive switching in TiO2 thin film using oxidisable electrode

Multilevel cell (MLC) capability of a memory device is an attractive alternative to realise high integration density of memory arrays. In addition, power efficient memory cell along with MLC capability has huge potential in neuromorphic computing and data storage applications. In this study low power, high speed and 3-bit multilevel bipolar resistance switching operation is reported in TiO2 thin films where copper is used as counter electrode. On account of using an oxidisable electrode, low programming voltages (∼+0.2 V, −0.1 V) along with low reset current (∼10 µA) are observed, thereby ensuing low power (∼µW) memory operation. Additionally, observation of fast switching (∼250 ns) translated to ultra-low energy (∼pJ) consumption. By varying compliance current (IC) from 25 µA to 1.6 mA during the set process, eight distinct non-volatile resistance states are reliably obtained, which showed statistically significant and non-overlapping resistance distribution. The multilevel resistive switching in Cu/TiO2/Pt device is explained by considering filamentary the widening phenomenon in the electrochemical metallization memory cell. Numerical calculations revealed that increase in the diameter of the metallic conducting filament from ∼3 nm to 70 nm with increasing IC is accountable for multiple low resistance states. The results of this study are promising towards realisation of emerging memory devices with low operating power, fast switching operation and high spatial density.

Electrical and Data-Retention Characteristics of Two-Terminal Thyristor Random Access Memory

Two-terminal (2-T) thyristor random access memory (TRAM) based on nanoscale cross-point vertical array is investigated in terms of lengths and doping concentrations of storage regions for long data retention time ( T ret). For high device scalability and low program voltage ( V P), lengths of the storage regions are determined by the sum of depletion widths of N- and P-storage regions. When doping concentrations of two storage regions are equal to each other at 1018 cm−3, 2-T TRAM exhibits the longest T ret of 100 ms and the lowest impact ionization of the device can suppress various reliability issues such as hot carrier injection and junction degradation. Although T ret of 2-T TRAM can be reduced from 100 ms to 1.5 ms due to decreased read voltage with operating temperature rising from 300 K to 360 K, T ret can be further improved to >10 s by applying standby voltage ( V standby). The effective way to set minimum V standby is presented using the I A- V A characteristics with 1000-s fall time. Moreover, the optimal V standby is set to 0.60 V by considering disturbance in array operation. Consequently, the proposed design and operation guidelines can provide a pathway to realize nanoscale 2-T TRAM for capacitor-less 4F2 1T DRAM technology.

Low switching voltage, high-stability organic phototransistor memory based on a photoactive dielectric and an electron trapping layer

An organic phototransistor memory is presented with a photoactive dielectric layer of 6-[4'-( N , N -diphenylamino)phenyl]-3-ethoxycarbonylcoumarin (DPA-CM) doped into poly(methyl methacrylate) (PMMA) and an electron-trapping layer of poly(perfluoroalkenyl vinyl ether) (CYTOP). The dielectric gate layer functioned as an insulator in the dark and as a charge generator and/or conductive layer under photoirradiation, which resulted in a low program voltage and an operation with long-term stability. A shift in the phototransistor threshold voltage could be reversibly tuned from −5.8 to 6.2 V with a low switching voltage (≤8 V) under UV irradiation. Programmed/erased states were obtained by applying gate pulse voltages of −8/5 V under UV irradiation from an external light source. The phototransistor memory exhibited high stability with a large on/off current ratio of ~10 5 for a retention time up to 2 × 10 6 s with a reliability greater than 10 3 programming/erasing testing cycles. These findings introduce a new approach for organic phototransistor non-volatile memory with high stability. • A low switching voltage, highly stable organic phototransistor memory was fabricated. • The gate dielectric functions as a charge source or conductor under UV light and an insulator under dark. • The memory effect originates from trapping and detrapping electrons at an interface of CYTOP/DPA−CM:PMMA. • The memory device exhibits an on/off ratio up to ~10 5 at retention time of 2 × 10 6 s.

Analysis and optimization of read/write reliability for 12F2 cross-point ultra-fast phase change memory

Phase change memory (PCM) device using a diode as selector exhibits a high level of integration based on 40 nm process, but it still has some reliability problems, such as read disturbance and writing performance. In this paper, we test and improve the read/write reliability of one diode and one resistor (1D1R) structure cell in array with cell size of 12F2 (0.16 μm × 0.12 μm). The 1D1R device has good performance with ultra-high speed (20 ns) and low programming voltage (3.3 V). The cell programmed by current pulse has a better performance than that of voltage operation in amorphous state with respect to read disturb immunity. The ratio of reset/set resistance can be improved by choosing appropriate parameter of write operation. In addition, the endurance characteristics of the devices are investigated. The optimization in read/write operation guarantee that 1D1R device can satisfy the requirements for the high-speed and high-density applications.

Vulnerabilities and Reliability of ReRAM Based PUFs and Memory Logic

Resistive Random-Access Memory (ReRAM) devices have caught significant research attention as scalable nonvolatile memory technology for high-density data storage in 3-D crossbar architectures. ReRAM devices can switch with low programming voltages (<±1 V) at fast time-scales (≍10–100 ns) that make them an attractive option for not only off-chip data storage but also for on-chip embedded memory applications. ReRAM devices have also been explored for applications as reconfigurable switches in field programmable gate arrays (FPGAs). The random variabilities in the switching performance of ReRAM has been exploited to design Physically Unclonable Function (PUF) for hardware authentication, trust, and security. However, intrinsic vulnerabilities in ReRAM devices and its implications are not well-understood. Therefore, there is an urgent need to understand these so that the ReRAM-based circuits can be made robust against such attacks. This paper discusses our research on understanding the vulnerabilities in ReRAM through experimental studies and its implications on ReRAM based PUF operations. The Process, Voltage, Temperature (PVT) variabilities in ReRAM is experimentally studied and modeled. Some other ReRAM specific vulnerabilities, such as insertion of parasitic capacitances and Trojans by adversaries and its impact on ReRAM switching behavior is discussed. Based on experimental studies, models are created to capture these behaviors in ReRAM. Using these models, a 1 KB array of ReRAM devices in a crossbar architecture and its behavior is simulated. The challenge–response pairs of these ReRAM-based arrays were studied under ideal Trojan free conditions as well as with vulnerabilities models of ReRAM. Potential solutions are then proposed to make the PUF architecture and ReRAM devices more resistant to these vulnerabilities.