Low Power Operation Research Articles

Effects of combustor wall cooling structure on combustor performances

For lean premixed low-emissions gas turbine combustors, the amount of air used for combustion chamber cooling is relatively low to maintain a “lean” state of the flame. However, the wall cooling structures may have significant effects on combustor performances such as pollutant emissions, outlet temperature distributions, and boundary temperatures since it can change the near-wall temperature distributions. Most of the existing studies focus on the influence of cooling hole structures on heat transfer characteristics, and few studies comprehensively investigate the comprehensive effects on the wall heat transfer, outlet temperature distribution, pollutant generation characteristics, flow field structure, and flame morphology. To explore the feasibility of enhancing combustor performance through the implementation of combustor wall cooling structures, this study conducted a series of experimental and numerical investigations using two combustion chamber liners. Results show that although the burner structure remains unchanged, using the improved liner can widen the low-emissions operation ranges, and will reduce CO emissions by 49.34 % under low-power operating conditions and NOx emissions by 7.95 % under high-power operation conditions. This is because it optimizes the distribution of the wall temperature gradient and the shape of the corner recirculation zone. Besides, the improved structure enhances the boundary wall heat transfer by about 10 %, which leads to a 14.31 K lower and more uniform temperature of the liner. This is because it eliminates the cooling air incident vortex and improves the heat transfer between different rows of cooling holes. Due to the change of flow-field and near-wall temperature distribution, the optimum fuel supply strategy is different for the two liner structures. In particular, the optimal fuel staging strategy for the original liner necessitates a higher inner stage equivalence ratio than that required for the improved liner configuration. The results of this study offer a solution strategy for effectively improving combustor performances by employing suitable liner cooling tactics.

Improving Freight Train Wheel Monitoring with Smart Sensors

Onboard monitoring of freight car axleboxes enhances safety, reduces maintenance costs, and improves track conditions by preventing secondary damage. Installing wireless sensors on freight cars without a nearby power source should be cost-effective, given the large quantities involved. To address this, a new wireless smart sensor node has been deployed. The sensor automatically recognizes stable operating conditions, detects wheel rotational speed from vibrations, performs real-time condition monitoring, and transmits the results to the cloud. This study outlines the smart sensor concept and the pilot field test conducted with real freight cars. The results demonstrate the ability to estimate wheel rotational speed from vibrations and the potential for detecting wheel out-of-roundness (OOR) using a newly developed condition indicator for low-power real-time operations.

Multi-Task Agent Hybrid Control in Sparse Maps and Complex Environmental Conditions

With the rapid development of space exploration technology, the detection of extraterrestrial bodies has become increasingly important. Among these, path planning and target recognition and positioning technologies are particularly critical for applications in intelligent agents with low computational power operating in complex environments. This paper presents a novel approach to path planning on low-resolution lunar surface maps by introducing an improved A* algorithm with an adaptive heuristic function. This innovation enhances robustness in environments with limited map accuracy and enables paths that maintain maximum distance from obstacles. Additionally, we innovatively propose the Dynamic Environment Target Identification and Localization (DETIL) algorithm, which identifies unknown obstacles and employs spatiotemporal clustering to locate points of interest. Our main contributions provide valuable references for the aerospace industry, particularly in lunar exploration missions. The simulation results demonstrate that the improved A* algorithm reduces the maximum elevation difference by 55% and the maximum cumulative elevation difference by 68% compared to the traditional A* algorithm. Furthermore, the DETIL algorithm’s obstacle identification component successfully recognizes all the obstacles along the path, and its spatiotemporal clustering improves the average number of target discoveries by 152% over the conventional DBSCAN clustering approach.

A New Back-End-Of-Line Ferroelectric Field-Effect Transistor Platform via Laser Processing.

The discovery of ferroelectricity in hafnia-based materials has revitalized interest in realizing ferroelectric field-effect transistors (FeFETs) due to its compatibility with modern microelectronics. Furthermore, low-temperature processing by atomic layer deposition offers promise for realizing monolithic three-dimensional (M3D) integration toward energy- and area-efficient computing paradigms. However, integrating ferroelectrics with channel materials in FeFETs for M3D integration remains challenging due to the dual requirement of a high-quality ferroelectric-channel interface and low-power operation, all while maintaining back-end-of-line (BEOL)-compatible fabrication temperatures. Recent studies on 2D semiconductors and metal oxide channels highlight these challenges. Polycrystalline silicon (poly-Si), a channel material long integrated into the semiconductor industry, presents a promising alternative; however, its high fabrication temperature has hindered its applications to M3D integration. To overcome this challenge, wedemonstrates a BEOL-compatible FeFET platform using poly-Si channels fabricated via locally-confined laser thermal processing and hafnia-based ferroelectrics by low-temperature atomic layer deposition with wafer-scale uniformity. The local nature of the laser processing mitigates the trade-off between the high-temperature crystallization for the quality of the interface and BEOL thermal budget constraints. The laser-processed FeFETs boast the largest effective memory widow for all BEOL-compatible FeFETs. Moreover, the fabricated FeFETs are integrated into wafer-scale synaptic arrays for neuromorphic computing, achieving record-high energy efficiency. Therefore, this work establishes a promising BEOL-compatible FeFET materials platform toward M3D integration.

Static Approximate Modified Mirror—Full Adder for High Speed and Low Power Operations Using 32 nm CNTFET Technology

ABSTRACTThe error tolerance nature of the digital multimedia applications enables the implementation of approximate digital circuits to achieve the benefits of high speed of operation and low power consumption. This paper proposes a static approximate modified mirror full adder (SAMM‐FA) circuit designed using logic level approximation to reduce the number of transistors in the circuit. Owing to the balanced electrical characteristics, better stability and higher on‐current to off‐current ratio (Ion/Ioff), 32 nm carbon nanotube field effect transistor (CNTFET) technology has been used for implementing the proposed circuit in the Cadence Virtuoso tool. Featuring only 10 transistors and operating at a supply voltage of 0.5 V, the proposed SAMM‐FA has a low power dissipation of just 4.14 nW, and propagation delay of just 3.82 ps. The power delay product and energy delay product figure of merits of the proposed circuit are found to be excellent when compared with the contemporary designs.

Multistate Ferroelectric Diodes with High Electroresistance Based on van der Waals Heterostructures.

Some van der Waals (vdW) materials exhibit ferroelectricity, making them promising for novel nonvolatile memories (NVMs) such as ferroelectric diodes (FeDs). CuInP2S6 (CIPS) is a well-known vdW ferroelectric that has been integrated with graphene for memory devices. Here we demonstrate FeDs with self-rectifying, hysteretic current-voltage characteristics based on vertical heterostructures of 10 nm thick CIPS and graphene. By using vdW indium-cobalt top electrodes and graphene bottom electrodes, we achieve a high electroresistance (on- and off-state resistance ratios) of ∼106, an on-state rectification ratio of 2500 for read/write voltages of 2 V/0.5 V, and a maximum output current density of 100 A/cm2. These metrics compare favorably with state-of-the-art FeDs. Piezoresponse force microscopy measurements show that stabilization of intermediate net polarization states in CIPS leads to stable multibit data retention at room temperature. The combination of two-terminal design, multibit memory, and low-power operation in CIPS-based FeDs is potentially interesting for compute-in-memory and neuromorphic computing applications.

Investigation in improving the Cs-free negative hydrogen ion production with short-pulse low power in the afterglow of pulse-power-modulated plasma sources

Abstract Pulse plasma ion sources have been shown to be capable of achieving high negative hydrogen ion densities ( n H − ) or currents. The fast cooling of the electrons and reduction in the electron density (n e) provide favorable plasma conditions to improve the H− production, with a high density ratio of negative hydrogen ions to electrons during the pulse-off period. The purpose of this research is to further improve the performance of volume-produced H− ion sources based on the pulse power modulation. In this study, a time-modulated negative hydrogen plasma sustained by 10 kHz pulse power at the typical gas pressure of 0.3 Pa was numerically investigated using a global model. The model is compared with measurements obtained in a pulsed radio frequency ion source and shows a reasonable agreement. A steplike low-high power strategy in the active glow period and a short-pulse low power in part of the afterglow period are employed to mitigate overshoot of the electron temperature (T e) in the initial stage of the pulse period and to optimize H− production in the afterglow, respectively. The model predicts that a small-magnitude, short-duration low power operation in the afterglow increases n H − and decreases n e from the onset of the low power until the beginning of the next high power pulse, due to a modest temporary increase in the T e (less than 2 eV). It facilitates dissociative electron attachments and thus H− formation. The reduction in the n e indicates that positive ions lost to the walls cannot be compensated by weak ionization. H− production with a low number of co-extracted electrons can be optimized by adjusting the magnitude and duration of the low power in the afterglow.

Cancer radiotherapy with mini neutron/gamma-ray generators

Recent advancements in negative hydrogen (H-) or negative deuterium (D-) ion source technology as well as the commercial availability of high-frequency AC high-voltage power supplies have enabled the development of mini neutron/gamma-ray generators using low-energy nuclear reactions. These generators can provide a useful flux of high-energy neutrons or gamma photons in either pulsed or continuous operations. With the new mini generator, intraoperative radiotherapy as well as treatment of tumors in the brain, skin, breast, salivary gland, pancreas, liver, and kidney can be performed using external or internal neutron/gamma-ray beams. The new radiotherapy system is very compact and requires very low power for operation, enabling its location inside an operation room of a hospital or clinical facility.

Review on spiking neural network-based ECG classification methods for low-power environments.

This paper reviews arrhythmia classification studies using electrocardiogram (ECG) signals. Research on automatically diagnosing arrhythmia in daily life has been actively underway for early detection and treatment of heart disease. Development of automatic arrhythmia classification using ECG signal began based on handcrafted morphological feature extraction and machine learning-based classification methods. As deep neural networks (DNN) show excellent performance in the signal processing field, studies using various types of DNN are also being conducted in ECG classification. However, these DNN-based studies have extremely high computational complexity, making it challenging to perform real-time classification, and are unsuitable for low-power environments such as wearable devices due to high power consumption. Currently, research based on spiking neural network (SNN), which mimics the low-power operation of the human nervous system, is attracting attention as a method that can dramatically reduce complexity and power consumption. The classification accuracy of the SNN-based ECG classification studies is close to that of the DNN-based studies. When combined with neuromorphic hardware, it shows ultra-low-power performance, suggesting the possibility of use in lightweight devices. In this paper, the SNN-based ECG classification studies for low-power environments are mainly reviewed, and prior to this, conventional and DNN-based ECG classification studies are also reviewed. We hope that this review will be helpful to researchers and engineers interested in the field of ECG classification.

Controlled Fabrication of Native Ultra‐Thin Amorphous Gallium Oxide From 2D Gallium Sulfide for Emerging Electronic Applications

AbstractOxidation of 2D layered materials has proven advantageous in creating oxide/2D material heterostructures, opening the door for a new paradigm of low‐power electronic devices. Gallium (II) sulfide (β‐GaS), a hexagonal phase group III monochalcogenide, is a wide bandgap semiconductor with a bandgap exceeding 3 eV in single and few‐layer form. Its oxide, gallium oxide (Ga2O3), combines a large bandgap (4.4–5.3 eV) with a high dielectric constant (≈10). Despite the technological potential of both materials, controlled oxidation of atomically‐thin β‐GaS remains under‐explored. This study focuses on the controlled oxidation of β‐GaS using oxygen plasma treatment, addressing a significant gap in existing research. The results demonstrate the ability to form ultrathin native oxide (GaSxOy), 4 nm in thickness, upon exposure to 10 W of O2, resulting in a GaSxOy/GaS heterostructure where the GaS layer beneath remains intact. By integrating such structures between metal electrodes and applying electric stresses as voltage ramps or pulses, their use for resistive random‐access memory (ReRAM) is investigated. The ultrathin nature of the produced oxide enables low operation power with energy use as low as 0.22 nJ per operation while maintaining endurance and retention of 350 cycles and 104 s, respectively. These results show the significant potential of the oxidation‐based GaSxOy/GaS heterostructure for electronic applications and, in particular, low‐power memory devices.

Dynamic modeling of polymer electrolyte membrane fuel cells under real-world automotive driving cycle with experimental validation on segmented single cell

A 1+1D transient non-isothermal and multiphase polymer electrolyte membrane fuel cell model is developed. The model is validated on experimental data gathered on a segmented single cell and representative of a real-world automotive driving cycle, derived from the stack protocol defined in the ID-FAST H2020 project. During Low-Power operation, cell voltage response is mainly controlled by platinum oxide and water dynamics: the low hydration significantly affects cathode inlet performance. Throughout High-Power operation, instead, voltage transients are ascribable to local mass-transport related phenomena: in particular, liquid water accumulation along the channel strongly decreases the efficiency of cathode outlet region. Finally, the effect of relative humidity at cathode channel inlet is investigated: an increase in the humidification of the air inlet stream from 30% to 50% leads to a better proton conductivity and, therefore, to a significant enhancement of the performance of cathode inlet regions, which also means a slight improvement in the average stack efficiency from 62.2% to 62.8%. Lowering RH of the air-inlet stream from 30% to 15%, a worsening of proton conductivity is observed, which exacerbates performance heterogeneities and leads to a reduction of the average stack efficiency from 62.2% to 61.5%, consistently with experimental results.

Picosecond Femtojoule Resistive Switching in Nanoscale VO2 Memristors.

Beyond-Moore computing technologies are expected to provide a sustainable alternative to the von Neumann approach not only due to their down-scaling potential but also via exploiting device-level functional complexity at the lowest possible energy consumption. The dynamics of the Mott transition in correlated electron oxides, such as vanadium dioxide, has been identified as a rich and reliable source of such functional complexity. However, its full potential in high-speed and low-power operation has been largely unexplored. We fabricated nanoscale VO2 devices embedded in a broadband test circuit to study the speed and energy limitations of their resistive switching operation. Our picosecond time-resolution, real-time resistive switching experiments and numerical simulations demonstrate that tunable low-resistance states can be set by the application of 20 ps long, <1.7 V amplitude voltage pulses at 15 ps incubation times and switching energies starting from a few femtojoule. Moreover, we demonstrate that at nanometer-scale device sizes not only the electric field induced insulator-to-metal transition but also the thermal conduction limited metal-to-insulator transition can take place at time scales of 100s of picoseconds. These orders of magnitude breakthroughs can be utilized to design high-speed and low-power dynamical circuits for a plethora of neuromorphic computing applications from pattern recognition to numerical optimization.

Ultrafast reverse saturable absorption and all-optical computing with boron dipyrromethene (BODIPY) chromophore derivatives

Ultrafast reverse saturable absorption (RSA) in chromophore-based borondipyrro-methenes (BODIPYs) derivatives, 1,7-Diphenyl-3,5-bis(9,9-dimethyl-9H-fluoren-2-yl)-boron-diuoride-azadipyrromethene (ZL-61) and 1,7-Diphenyl-3,5-bis(4-(1,2,2-triphenyl-vinyl)phenyl)-boron-diuoride azadipyrromethene (ZL-22), has been theoretically analyzed with femtosecond (fs) laser pulses at 800 nm and 850 nm. The results are in good agreement with the reported experimental results. The effect of input pulse intensity, pulse width, nonlinear absorption (NLA) coefficients, sample thickness and laser pulse shaping on transmittance has been studied and optimized for high contrast and low-power operation. All-optical fs NOT and the universal NOR and NAND Boolean logic gates have been designed with ZL-61 and ZL-22. The logic gates with top-hat input pulse profile have a sharp switch ON/OFF time compared to the Gaussian input laser profile. Ultrafast operation at relatively low pump intensities opens up exciting prospects for the applicability of BODIPY derivatives for ultrafast low-power all-optical computing and information processing.

A Comprehensive Review of Power Consumption in Digital Logic Circuits at Ultra-Low Subthreshold CMOS Levels

In the anticipated spectrum, a lot of work has gone into managing the trade-offs between power, location, and efficiency in the moderate efficiency, moderate power region. However, research into the extremities of this spectrum remains restricted. In particular, there hasn't been enough research done on the extremes of extraordinarily low power consumption with appropriate efficiency and extraordinary efficiency with energy that is within realistic bounds. In this work, very low subthreshold power levels are used to study the power consumption characteristics of digital logic circuits in static Complementary Metal-Oxide-Semiconductor (CMOS) devices. The study shows that operating transistors below their threshold voltage might result in significant energy savings. This research emphasises the significance of subthreshold design strategies for contemporary electronic circuits that aspire for low-power operation without sacrificing efficiency. The results highlight the potential for significant progress in energy-efficient circuit design and highlight the delicate balance between preserving performance and cutting power usage. As a result, this research adds to our understanding of low-power electronics and provides information that may lead to the development of future technologies that are more efficient and sustainable. Keywords— Power consumption analysis, Digital logic circuits, Ultra-low power, Subthreshold operation, Static CMOS gates

Enabling Seamless Connectivity: Networking Innovations in Wireless Sensor Networks for Industrial Application.

The wide-ranging applications of the Internet of Things (IoT) show that it has the potential to revolutionise industry, improve daily life, and overcome global challenges. This study aims to evaluate the performance scalability of mature industrial wireless sensor networks (IWSNs). A new classification approach for IoT in the industrial sector is proposed based on multiple factors and we introduce the integration of 6LoWPAN (IPv6 over low-power wireless personal area networks), message queuing telemetry transport for sensor networks (MQTT-SN), and ContikiMAC protocols for sensor nodes in an industrial IoT system to improve energy-efficient connectivity. The Contiki COOJA WSN simulator was applied to model and simulate the performance of the protocols in two static and moving scenarios and evaluate the proposed novelty detection system (NDS) for network intrusions in order to identify certain events in real time for realistic dataset analysis. The simulation results show that our method is an essential measure in determining the number of transmissions required to achieve a certain reliability target in an IWSNs. Despite the growing demand for low-power operation, deterministic communication, and end-to-end reliability, our methodology of an innovative sensor design using selective surface activation induced by laser (SSAIL) technology was developed and deployed in the FTMC premises to demonstrate its long-term functionality and reliability. The proposed framework was experimentally validated and tested through simulations to demonstrate the applicability and suitability of the proposed approach. The energy efficiency in the optimised WSN was increased by 50%, battery life was extended by 350%, duplicated packets were reduced by 80%, data collisions were reduced by 80%, and it was shown that the proposed methodology and tools could be used effectively in the development of telemetry node networks in new industrial projects in order to detect events and breaches in IoT networks accurately. The energy consumption of the developed sensor nodes was measured. Overall, this study performed a comprehensive assessment of the challenges of industrial processes, such as the reliability and stability of telemetry channels, the energy efficiency of autonomous nodes, and the minimisation of duplicate information transmission in IWSNs.

Fabrication Techniques for a Tuneable Room Temperature Hybrid Single-electron Transistor and Field-effect Transistor

Hybrid room-temperature (RT) silicon single-electron – field effect transistors (SET-FETs) provide a means to switch between ‘classical’, high current FET, and low-power SET operation, using a gate voltage. While operating as a SET, charge on a silicon quantum dot (QD) within the current channel, can be controlled at the one-electron level using the Coulomb blockade effect. This paper investigates nanofabrication methods for sub-10 nm ‘fin’ channel hybrid RT SET-FETs, and their influence on the energy band diagram, and formation of tunnel barriers and QDs, along the channel. Devices are fabricated in heavily n-doped SOI material using electron beam lithography, with thermal oxidation to reduce the as-defined fin width. Effective channel dimensions, following oxidation and excluding Si/SiO2 interface dopant deactivation, are ∼2.4 nm × 32 nm × 20 nm. Dopant disorder, fin width variation at the nanometre scale, and quantum confinement effects are considered as mechanisms for the formation of tunnel barriers and QDs, with dopant disorder the most likely reason. Arrhenius plots of Ids vs. 1/T allow extraction of a potential barrier energy ∼0.2 eV along the fin channel. For 180devices fabricated on four chips, 37% show RT SET-FET operation, ∼3 times higher than the corresponding yield observed in previous work on point-contact silicon SETs.

Programmed Heterostructures for Enhanced Electrical Conductivity.

Interfacial electron transport in multicomponent systems plays a crucial role in controlling electrical conductivity. Organic-inorganic heterostructures electronic devices where all the entities are covalently bonded to each other can reduce interfacial electrical resistance, thus suitable for low-power consumption electronic operations. Programmed heterostructures of covalently bonded interfaces between ITO-ethynylbenzene (EB) and EB-zinc ferrite (ZF) nanoparticles, a programmed structure showing 67 978-fold enhancement of electrical current as compared to pristine NPs-based two terminal devices are created. An electrochemical approach is adopted to prepare nearly π-conjugated EB oligomer films of thickness ≈26nm on ITO-electrode on which ZF NPs are chemically attached. A "flip-chip" method is employed to combine two EB-ZnFe2O4 NPs-ITO to probe electrical conductivity and charge conduction mechanism. The EB-ZnFe2O4 NPs exhibit strong electronic coupling at ITO-EB and EB-NPs with an energy barrier of 0.13eV between the ITO Fermi level and the LUMO of EB-ZF NPs for efficient charge transport. Both the DC and AC-based electrical measurements manifest a low resistance at ITO-EB and EB-ZF NPs, revealing enhanced electrical current at ± 1.5V. The programmed heterostructure devices can meet a strategy to create well-controlled molecular layers for electronic applications toward miniaturized components that shorten charge carrier distance, and interfacial resistance.

DC-biased Suzuki stack circuit for Josephson-CMOS memory applications

Josephson-CMOS hybrid memory leverages the high speed and low power operation of single-flux quantum logic and the high integration densities of CMOS technology. One of the commonly used type of interface circuits in Josephson-CMOS memory is a Suzuki stack, which is a latching high-voltage driver circuit. Suzuki stack circuits are typically powered by an AC bias voltage that has several limitations such as synchronization and coupling effects. To address these issues, a novel DC-biased Suzuki stack circuit is proposed in this paper. As compared to a conventional AC-biased Suzuki stack circuit, the proposed DC-biased design can provide similar output voltage levels and parameter margins, approximately two times higher operating frequency, and three orders of magnitude lower heat load of bias cables.

A review of transforming neuromorphic computing with 2D material memtransistors

In the pursuit of advancing neuromorphic computing, 2D material-based memtransistors have emerged as a promising avenue. These memtransistors offer a unique blend of attributes, including tiny dimensions, compactness, and low-power operation, making them ideal candidates to mimic human brain functionality for artificial intelligence applications. This review focuses on various 2D materials such as MoS2, WSe2, h-BN, and In2Se3, and their suitability for bio-synapse applications, highlighting their advantages over other synaptic devices. Additionally, the review suggests the development of multi-terminal memtransistor-based synaptic devices with innovative operational principles for in-memory computing applications. Finally, concludes by discussing both the current state of development and the prospects and challenges that lie ahead, aiming to inspire further progress in information storage and neuromorphic computing.

Implementation of two-step gradual reset scheme for enhancing state uniformity of 2D hBN-based memristors for image processing

In-memory computing facilitates efficient parallel computing based on the programmable memristor crossbar array. Proficient hardware image processing can be implemented by utilizing the analog vector-matrix operation with multiple memory states of the nonvolatile memristor in the crossbar array. Among various materials, 2D materials are great candidates for a switching layer of nonvolatile memristors, demonstrating low-power operation and electrical tunability through their remarkable physical and electrical properties. However, the intrinsic device-to-device (D2D) variation of memristors within the crossbar array can degrade the accuracy and performance of in-memory computing. Here, we demonstrate hardware image processing using the fabricated 2D hexagonal boron nitride-based memristor to investigate the effects of D2D variation on the hardware convolution process. The image quality is evaluated by peak-signal-to-noise ratio, structural similarity index measure, and Pratt’s figure of merit and analyzed according to D2D variations. Then, we propose a novel two-step gradual reset programming scheme to enhance the conductance uniformity of multiple states of devices. This approach can enhance the D2D variation and demonstrate the improved quality of the image processing result. We believe that this result suggests the precise tuning method to realize high-performance in-memory computing.