Low In-band Phase Noise Research Articles

A phase-locked loop with a jitter of 50 fs for astronomy applications

AbstractRadio telescopes are among the applications with the highest demands on a local oscillator (LO), which is used to receive and process the signals coming from the sky. Therefore the modules providing the required LO signal have traditionally been big and complicated. To overcome this disadvantage, we implement our own integrated frequency synthesizer inside a small LO module in this article. With this synthesizer we are able to achieve a jitter of only 50 fs integrated from 10 Hz to 2.5 GHz offset at a carrier frequency of 75 GHz. This is in part achieved by a very low in-band phase noise of −111.8 dBc at 10 kHz offset. The stabilizable frequency range is 62–88 GHz. Thus achieving promising results to fulfill this very demanding task with integrated frequency synthesizers in the future.

Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur

This article presents a low jitter, low power, low reference spur LC oscillator-based reference oversampling digital phase locked loop (OSPLL). The proposed reference oversampling architecture simultaneously offers a low in-band phase noise, a wide-bandwidth, and a low spur. In addition, this article proposes an LC digitally controlled oscillator (DCO) for the proposed OSPLL to achieve a fast frequency update and fine frequency resolution, while its varactor switching timing is set optimally for low jitter using the proposed DCO tuning pulse timing control scheme. The proposed OSPLL was fabricated in a 28-nm CMOS process. The integrated rms jitter of the PLL was measured at 67.1 fs for an output frequency of 4 GHz. The in-band phase noise of the PLL was −129.2 and −132.5 dBc/Hz at 1- and 5-MHz offset frequencies. The measured reference spur of the PLL was −78.1 dBc. Total PLL power consumption was 5.2 mW, resulting in −256.3-dB PLL jitter-power FoM, while occupying 0.17-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

A C-Band FMCW SAR Transmitter Based on Synthetic Bandwidth Technique

A $C$ -band frequency-modulated continuous wave (FMCW) transmitter based on synthetic bandwidth technique for synthetic aperture radar (SAR) imaging is presented. A 500-MHz narrowband chirp signal is up-converted to two adjacent carriers to obtain 1-GHz chirp at the $C$ -band. The adjacent carriers are obtained through fast switching subharmonic injection locking oscillator (SHILO) technique with 14-ns settling time. For narrowband chirp, a wideband fractional- $N$ phase locked loop (PLL) is used, covering 1.8–2.3 GHz and achieving low in-band phase noise of −115 to 120 dBc/Hz. The proposed technique achieves reconfigurable chirp period ranging from 0.3 to 6.3 ms. It can also be easily extended for wider chirp bandwidth by simply increasing the number of SHILO carriers. The chip consumes 84 mW, while occupying a total active area of 2.24 mm2.

Digital Fractional-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$N$ &lt;/tex-math&gt; &lt;/inline-formula&gt; PLLs Based on a Continuous-Time Third-Order Noise-Shaping Time-to-Digital Converter for a 240-GHz FMCW Radar System

Frequency-modulated continuous-wave (FMCW) radar requires low in-band phase noise, fast-settling high-frequency phase-locked loops (PLLs). We propose a new third-order continuous-time time-to-digital converter (TDC) that shapes quantization noise so that the TDC quantization noise no longer determines the in-band phase noise of a digital PLL. The new TDC allows a digital PLL to have an in-band phase noise performance similar to that of an analog PLL. Prototype 30- and 40-GHz PLLs, fabricated in 65-nm CMOS as sources for a 240-GHz scanning FMCW radar, consume 34.8 and 40 mW, respectively. The 30-GHz prototype PLL has a normalized phase noise of −213 dBc/Hz2 (at 100-kHz offset) and an FoMJitter of −230 dB (from 10 kHz to 1 MHz), thanks to the measured 182 fs integrated rms noise of TDC.

0.75 V 2.6 GHz digital bang–bang PLL with dynamic double‐tail phase detector and supply‐noise‐tolerant g m ‐controlled DCO

A compact low-supply-voltage yet low-noise digital bang–bang PLL (DBBPLL) is proposed. The bang–bang phase detector is based on a dynamic double-tail latch which enables high time-to-voltage gain and low input-referred noise under tight power-supply headroom. The ring-based digitally controlled oscillator (DCO) is made of multiple g m-controlled delay units and a constant-g m-biased current DAC. By combining these two blocks, the DCO can now better tolerate supply noise and process variations. A prototype DBBPLL has been implemented in a mainstream 28 nm CMOS process with a compact die area of 0.014 mm2. When operating at 2.6 GHz, it consumes 2.9 mW with 0.75 V supply and achieves low in-band phase noise of −105 dBc/Hz.

A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation

This brief presents a spread-spectrum clock generator (SSCG) based on a subsampling phase-locked loop (SSPLL) by calibrating the spreading ratio. The proposed SSCG has a low jitter performance owing to the low in-band phase noise performance of the SSPLL. To achieve a spread-spectrum clocking, the direct voltage-controlled oscillator modulation method is used owing to the absence of a frequency divider. However, the spreading ratio ( ${\delta }$ ) can be varied by process, voltage, and temperature variations. Automatic calibration technique is proposed for a 5000-ppm spreading ratio at 5 GHz. The proposed SSCG achieves a 21-dB electromagnetic interference reduction, has a −104-dBc/Hz phase noise at 200-kHz offset, and consumes 7 mW and occupies a 0.39-mm2 area in a 65-nm CMOS process.

A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise

This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital phase-locked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC). The TDC employs a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizing an error-feedback topology. Such an error-feedback unit of a first-order $\Delta \Sigma $ -TDC can be cascaded as a multi-stage noise shaping configuration to achieve higher-order noise-shaping and, thereby, low in-band phase noise (PN) of the ADPLL. A digitally controlled oscillator with a transformer and a pair of cross-coupled NMOS amplifiers exploits magnetic and capacitive coupling to achieve nearly an octave frequency coverage, i.e., 1.73–3.38 GHz (after a $\div $ 2 division). Fabricated in 40-nm CMOS, the ADPLL achieves better than −110-dBc/Hz in-band PN and occupies an active area of 0.5 mm2. With a 50-MHz reference clock, a 2-GHz output RF clock, and a loop bandwidth of 800 kHz, this prototype achieves 420-fs $_{{\mathrm{rms}}}$ jitter, integrated from 1-kHz to 30-MHz offset, while drawing 10.7 mW.

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC

This paper presents a fractional-N digital phase-locked loop (PLL) that achieves low in-band phase noise. Phase detection is carried out by a proposed 10-bit, 0.8 ps resolution time-to-digital converter (TDC) using a charge pump and a successive-approximation-register analog-to-digital converter (SAR-ADC) with low power and small area. The latency of the TDC is addressed by the designed building blocks. The fractional spurs are reduced by dual-loop least-mean-square (LMS) calibration. A $\Delta \Sigma $ -less and MOS varactor-less LC digitally-controlled oscillator (DCO) is proposed whose frequency resolution is enhanced to 7 kHz (or a unit variable capacitance of 2.6 aF) using a bridging capacitor technique. A prototype chip is fabricated using a 65 nm CMOS process, occupying an active area of 0.38 mm2 and consuming a power of 9.7 mW at a reference frequency of 50 MHz. The measured in-band phase noise is 107.8 dBc/Hz to 110.0 dBc/Hz with a loop bandwidth of 1 to 5 MHz.

A Fractional-&lt;italic&gt;N&lt;/italic&gt; Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

A fractional- $N$ sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined phase-interpolator and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation. This technique can be used for designing a fractional- $N$ PLL with low in-band phase noise and low spurious tones with low power consumption. The short-current-free pipelined phase-interpolator used in this work is capable of achieving high-linearity with low-power while minimizing the intrinsic jitter. A number of other circuit techniques and layout techniques are also employed in this design for ensuring high-performance operation with minimal chip area and power consumption. The proposed fractional- $N$ PLL is implemented in standard 65 nm CMOS technology. The PLL has an operating range of 600 MHz from 4.34 GHz to 4.94 GHz. In fractional- $N$ mode, the proposed PLL achieves -249.5 dB FoM and less than -59 dBc fractional spurs.

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad

This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance $({{-g}}_{m})$ of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves $-78.5\; \text{dBc/Hz}$ at 100 kHz offset, $-122\text{dBc/Hz}$ at 10 MHz offset, and a figure-of-merit (FoM) of $-236\text{dB}$ .

A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

A low-noise divider-less PLL, employing a subsampling locked loop, samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. The frequency synthesizer achieves a low in-band phase noise of -112 dBc/Hz at a 2.3 GHz output frequency. The analysis for the frequency synthesizer, especially for the nonlinear characteristics of the circuits, is proposed. Fabricated in a 0.18 μm CMOS technology, the frequency synthesizer consumes 9.6 mA and achieves figure-of-merit of -239.1 dB, corresponding to 266 fs rms jitter.

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter

A 2.1-GHz dividerless PLL with low power, low reference spur and low in-band phase noise is introduced in this paper. A new phase detection mechanism using aperture-phase detector (APD) and phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error between reference and VCO, and then controls the current amplitude of the following charge pump (CP). The charging and discharging currents in the proposed CP have equal pulse width and equal small amplitude in locked state, which reduces the reference spur and power consumption of the CP effectively. Moreover, compared to the conventional CP with the same bias current in locked state, the proposed CP can contribute a much lower noise to the PLL output. In addition, a method of tunable loop gain with theoretical analysis is introduced to reduce the PLL output jitter. The proposed PLL is fabricated in a standard 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex></formula> m CMOS process. It consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex> </formula> 0.86 mm. The reference spur of the proposed PLL is measured to be <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}80$</tex></formula> dBc/ <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}74$</tex></formula> dBc and an in-band phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}103$</tex> </formula> dBc/Hz at 100 kHz offset is achieved.