Low-voltage Analog Circuits Research Articles

Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization

Low-power analog design is a hot topic for various power efficient applications. Sizing low-power analog circuits is not easy because the increasing uncertainties from low-voltage techniques magnify process variation effects on the design yield. Simulation-based approaches are often adopted for analog circuit sizing because of its high accuracy and adaptability in different cases. However, if process variation is also considered, the huge number of simulations becomes almost infeasible for large circuits. Although there are some recent works that adopt machine learning (ML) techniques to speed up the optimization process, the process variation effects are still hard to be considered in those approaches. Using the popular evolutionary algorithm (EA) as an example, this paper proposes an ML-assisted prediction model to speed up the variation-aware circuit sizing technique for low-voltage analog circuits. By predicting the likelihood for a design that has worse performance, the enhanced EA process is able to skip many unnecessary simulations to reduce the convergence time. Moreover, a novel force-directed model is proposed to guide the optimization toward better yield. Based on the performance of prior circuit samples in the EA optimization, the proposed force model is able to predict the likelihood of a design that has better yield without time-consuming Monte Carlo simulations. Compared with prior works, the proposed approach significantly reduces the number of simulations in the yield-aware EA optimization, which helps to generate practical low-voltage designs with high reliability and low cost.

A technique to enhance the transconductance of micro-power improved recycling folded cascode operational transconductance amplifier with reasonable phase margin

To keep a pace with the modern digital circuits, a development of a high performance low voltage and low power analog circuits is one of the challenging tasks. This paper presents a low voltage low power advanced folded cascode operational transconductance amplifier (OTA) with an improved transconductance and DC gain. The proposed structure adopts a power efficient current recycling folded cascode structure with an asymmetrical current split input stage. To achieve a low voltage and low power operation, all the transistors are biased in a weak inversion region. The proposed structure shows a significant enhancement in transconductance outcomes in the increased DC gain and gain bandwidth product (GBW) with a comparative phase margin for the same value of a load capacitor in a low voltage environment. The proposed OTA is implemented in 0.18 um CMOS technology. It shows approximately 8.96° advancement in a phase margin and 2.76 dB hike in a DC gain with an equal GBW compared to its original OTA counterpart structure at 0.5 V supply voltage.

Active Current Mirrors for Low-Voltage Analog Circuit Design

In this work, active current mirrors using sensing resistors and a pass transistor in a feedback loop will be examined in detail. First, several non-idealities in this family of circuits, such as offset, noise, output impedance, or bandwidth, are addressed, showing no performance degradation under certain circumstances. Then, the design and measurement results of a 10-\(\upmu \hbox {A}\) (nominal) active current mirror that can operate down to just 80 mV voltage drop are presented. Finally, two simple amplifier stages using classic and active current mirrors are compared, the latter operating almost at a third of the supply voltage. It is possible to conclude that active current mirrors can be a very valuable building block for low-voltage analog circuits.

LOW POWER LOW VOLTAGE OPERATION OF OPERATIONAL AMPLIFIER

The increasing demand for high performance, battery-operated, system-on-chip (SoC) in communication and computing has shifted the focus from traditional constraints (such as area, performance, cost and reliability) to power consumption. With the increasing integration level, energy consumption has become an important issue. Consequently much effort has been put in achieving lower dissipation at all levels of the design process. Minimizing power saves energy, simplifies cooling and contributes to device longibility.The low power design can increase operation time and /or utilize a smaller size and a light-weight battery. Low voltage operation is demanded because it is desirable to use as few batteries as possible for size and weight consideration. Low voltage analog circuit design techniques considerably differ from high voltage design technique .There are so many strategies available for low voltage design. In the field of Analog electronics we generally apply ±15 V or ±12V for proper operation of operational amplifier. In this paper it is shown that if we apply ±5V, then also all the op-amp electrical parameters(such as input offset voltage, input bias current, input offset current, CMRR) maintain datasheet specification for a particular type of IC. Here LM741C IC has been chosen to represent the operation of operational amplifier at ±5V. Here MULTISIM is used for the simulation purpose and the change in the external biasing circuitry is made to meet the datasheet specification of LM741 IC. Research is needed to provide intelligent policies for careful management of the power consumption while still providing the appearance of continuous connection to system service and application.

A Novel Carbon Nanotube Field Effect Transistor based Arithmetic Computing Circuit for Low-power Analog Signal Processing Application

Abstract There is a need to explore circuit application in new emerging technologies for their rapid commercialization as the CMOS technology is approaching its limits. Carbon Nanotube Field-Effect Transistor (CNFET) is a promising candidate for future electronic devices for low-power low-voltage digital or analog circuit application. In this paper, we presented a low-power, low- voltage CNFET operational amplifier (OPAMP) based analog arithmetic computing circuit such as inverting amplifier, non- inverting amplifier, summer, substractor, differentiator, and integrator for low-power analog signal processing application. The proposed computing circuits operation are studied by using HSPICE software for circuit simulation at 0.9 V input supply voltage. Simulation results show that the proposed computing circuits well suited for low-power low-voltage analog signal processing application for their lower power consumption, and high speed operation.

Ultra low-voltage CMOS transconductance amplifiers

Simple and symmetrical ultra low-voltage current mode analog circuits and autozeroing amplifiers are presented. The low-voltage analog circuits are based on low-voltage inverters resembling precharge digital logic. Ultra low-voltage analog circuits can be operated at supply voltages down to 250 mV with rail-to-rail input and output swing. The output current of the ultra low-voltage symmetrical transconductance amplifier can be quite large due to a current boost technique. Ultra low-voltage analog circuits can be operated at supply voltages down to 250 mV with rail- to-rail input and output swing. The current headroom is 3 μA and the supply voltage is 300 mV. For supply voltages down to 300 mV simulated data shows that the maximum clock frequency is approximately 600 MHz.

Low-voltage FGMOS based analog building blocks

Novel floating gate MOSFET (FGMOS) based low-voltage analog circuits such as current-to-voltage converter, current-mode divider and pseudo-exponential function generator are proposed in this paper. The inherent advantages of these circuits are their simplicity, accuracy and low power dissipation. The current-to-voltage converter is operated with a single power supply of 0.9V. The current-mode divider and pseudo-exponential function generator are operated at supply voltages of ±0.9V. It was observed that the power dissipation of the current-to-voltage converter is reduced to 12μW using a single power supply. The power dissipations of the current-mode divider and pseudo-exponential function generator are found to be 356 and 471μW, respectively. The proposed circuits are simulated using SPICE in 0.5μm CMOS process technology to demonstrate the feasibility and the effectiveness of the proposed circuits.

Automatic Design of Low-Power Low-Voltage Analog Circuits Using Particle Swarm Optimization with Re-Initialization

In this paper, we present application and effectiveness of Particle Swarm Optimization (PSO) for automatic sizing of analog circuits. An efficient re-initialization strategy is introduced to improve the performance of PSO Algorithm (referred as PSO-R). Four benchmark circuits, namely, (i) CMOS buffer chain, (ii) two-stage CMOS operational amplifier (op-amp), (iii) high-gain low-power low-voltage three-stage CMOS op-amp, and (iv) a recently reported ultra-low-power ultra-low-voltage CMOS Miller operational transconductance amplifier (OTA), are automatically designed using the PSO-R algorithm. For the purpose of comparison, these circuits are also designed using PSO, Hierarchical PSO (HPSO), and Genetic Algorithm (GA). Various CMOS technologies ranging from 0.35 μm down to 0.13 μm are used. PVT (process, voltage, and temperature) variations are taken into account and Spectre tool is used for circuit simulations. The PSO-R algorithm converges to a better solution compared to other algorithms for multiple design trials of various low-power low-voltage op-amp designs. For CMOS ultra-low-power ultra-low-voltage Miller OTA, even performance of the circuit designed by the PSO-R algorithm is better than that of recently reported manual design of the same circuit. For future ultra-low-voltage applications, this OTA is also designed in 0.4 V supply voltage. This 0.4 V OTA gives a DC gain of 75 dB, unity gain frequency of 50 MHZ, and dissipates a power of 550 nW. For this design, PSO-R algorithm has taken 19 minutes of CPU time on average on a Sun system with 1.2 GHz dual core processor and 8 GB RAM.

Optimizing Spacer-to-Straggle Ratio in Underlap Double Gate MOSFETs for Low Voltage Analog and Digital Circuits

In this work, we report on the significance of non-overlap channel architecture in nanoscale double gate (DG) FETs to improve performance of low-voltage analog and digital circuits. It is shown that the low-voltage operation of a cascoded Operational Transconductance Amplifier (OTA) and 6-T SRAM cell can be considerably enhanced using underlap gate-source/drain design. The present work provides new opportunities for realizing future low-voltage analog and digital circuits with underlap DG FETs.

Optimizing Spacer-to-Straggle Ratio in Underlap Double Gate MOSFETs for Low Voltage Analog and Digital Circuits

not Available.

Self Cascode: A Promising Low Voltage Analog Design Technique

Two current mirror (CM) structures incorporating the self cascode (SC) technique for low voltage (LV) analog and mixed mode circuits are proposed. One CM is implemented by 4 MOSFETs, has output resistance of 0.3 M? and bandwidth of 1.2 GHz, while the other requires 8 MOSFETs, has output resistance of 15 M? and bandwidth of 1.1 GHz. Both can operate at ± 0.5 V. P-Spice simulations confirm the high performance of these CMs in comparison with the conventional and regulated structures.A small part of this paper is similar to the one that appeared in WASET-Vienna, Aug 13-15, 2008, Conference Proceedings

Scalable High Voltage CMOS technology for Smart Power and sensor applications

Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics. HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller CMOS technology nodes or when integrating embedded non-volatile memory. In this work we propose a new 0.35 µm HVCMOS technology that can overcome the previous limitations in drive currents. It can match the low HV chip sizes (Rdson) of typical BCD processes while maintaining the low process complexity with only 2 mask level adders on top of CMOS. We also introduce a figure of merit (FOM) for comparing HV technologies. Key elements of making this newly proposed 0.35 µm HVCMOS so competitive to BCD technologies are discussed and a device lifetime of more than 10 years, operating temperatures of 150 °C and ESD robustness of 4 kV HBM and higher, as well as the integration of a highly robust embedded EEPROM/Flash technology is shown. We also provide first verification results of the scalability of the proposed 0.35 µm HVCMOS technology to 0.18 µm and beyond as well as to currents of up to 8 A.

ISSCC 2009 Feb 8–12 Preview

Focusing in 2009 on Adaptive Circuits and Systems, ISSCC will offer four plenary talks, approximately 250 technical papers, nine evening panels and special evening sessions, all included in the registration price. Information about these events and the eight ISSCC 2009 circuit design forums, ten 90-minute tutorials, and an all-day Short Course on Low-Voltage Analog and Mixed-Signal CMOS Circuit Design will be published on the conference website in November.

DTMOS Technique for Low-Voltage Analog Circuits

In this paper, the application of dynamic threshold MOS (DTMOS) technique for low-voltage analog circuits is explored. The body terminal of PMOS transistors in bulk CMOS technology can be used as the forth terminal to enhance the performance of low-voltage analog circuits. To show the effectiveness of this technique, we have designed a continuous time common mode feedback (CMFB) circuit for a sub 1-V opamp and a new sub 1-V, 1-bit quantizer. A 0.8-V opamp with embedded CMFB and a 0.8-V, 1-bit quantizer for low-voltage DeltaSigma modulators are implemented in 0.18-mum CMOS technology. The simulation results as well as the measurement data of these blocks are presented in this paper

Ultralow-power CMOS/SOI Circuit Technology

We have introduced an example of a system that embodies the concept of a ubiquitous communication service and explained the importance of low power consumption in the communicator that will serve as the bridge between the real world and the network for real-time services in which sensor data is acquired every second. An effective solution to the problem of high energy efficiency is to employ the synergy of combining low-voltage analog circuit technology and FD-SOI devices. Taking advantage of that synergy to reduce the power consumption of the communicator during operation to about 10 mW and employing intermittent operation with an activity rate of less than 1% would make it possible to support operation for one year or more with a commercial coin-type lithium battery.

Improved FGMOS-Based Low-Voltage Voltage Follower

The use of floating-gate MOSFETs (FGMOS) in designing low-voltage analog circuits is presented. A FGMOS based low-voltage voltage follower and its use in CCII structures is presented. Working of such CCII structures is ascertained by using them in current-mode and voltage-mode band-pass simulated filters.

Very Low Voltage MOS Translinear Loops Based on Flipped Voltage Followers

A novel technique for operating MOS Translinear loops at very low supply voltages is described, based on the use of Flipped Voltage Followers for biasing the loops. The resulting topologies, suited to standard CMOS processes, can be successfully applied to a varied repertory of low-voltage analog circuits, such as squarers, multipliers, filters, oscillators, and RMS-DC converters. Measurement results for a geometric-mean and a squarer/divider circuit demonstrate on silicon the usefulness of this technique.

Comparison of a BSIM3V3 and EKV MOSFET model for a 0.5 /spl mu/m CMOS process and implications for analog circuit design

Design requirements for high-density detector front-ends and other high-performance analog systems routinely force designers to operate devices in moderate inversion. However, CMOS models have traditionally not handled this operating region very well. In this paper, the Berkeley Short-Channel IFGET Model (BSIM3V3) and EKV 2.6 MOSFET models are evaluated in terms of their ability to model low-voltage analog circuits. Simulation results for a standard 0.5 /spl mu/m CMOS process are presented and compared to measured data. The data presented includes simulated and measured output conductance and transconductance efficiency for devices with channel lengths ranging from 0.5 /spl mu/m to 33 /spl mu/m. In addition, the models are compared in terms of their ability to handle the different operating regions of the MOS transistor (weak, moderate, and strong inversion). The results highlight the difficulty of obtaining a model that accurately predicts the operation of high-performance analog systems.

A new family of very low-voltage analog circuits based on quasi-floating-gate transistors

A new family of very low-voltage analog circuits is introduced. These circuits do not show the GB degradation that characterizes other low-voltage approaches based on floating-gate transistors. The proposed approach is validated with experimental results of a CMOS mixer in 0.5-/spl mu/m CMOS technology with 0.7-V input signal swing that operates on a single 0.8-V supply with transistor threshold voltages of 0.67 V.

A Current Mirror for Low Voltage, High Performance Analog Circuits

A current mirror for low voltage analog and mixed mode circuits is proposed. The current mirror has high input and output voltage swing capability and can operate at ±1.0 V supply. P-Spice simulations confirm the input current range of 1 μA to 500 μA with 2.5 GHz bandwidth for the proposed current mirror. Adaptive biasing increases the input voltage swing capability and decreases the undesired offset current. Resistive and capacitive compensation are used to increase its bandwidth.