Low-temperature Post-deposition Annealing Research Articles

Improved electrical performance for SiO2/β-Ga2O3 (001) MIS capacitor by post-deposition annealing

In this study, we have fabricated a high-performance SiO2/β-Ga2O3 (001) MIS capacitor and investigated the effect of low-temperature post-deposition annealing (PDA) on its electrical properties. The SiO2/β-Ga2O3 (001) MIS capacitor exhibits improved gate leakage current and breakdown electrical field after the PDA treatment. The high-frequency capacitance-voltage hysteresis curves reveal that the fixed charge density, as well as the fast and deep near-interfacial trapped charge densities, decreases with the PDA process. We achieved an interfacial trapped charge density as low as 1.6 × 1011 cm−2 eV−1 at an energy of 0.6 eV below the conduction band of β-Ga2O3 (001) through 400 °C annealing.

Low temperature crystallization of atomic-layer-deposited SrTiO3 films with an extremely low equivalent oxide thickness of sub-0.4 nm

Despite SrTiO3(STO) possessing a high dielectric constant, its application as a capacitor dielectric in dynamic random-access memory(DRAM) capacitors faces challenges due to the high-temperature annealing for crystallization, its compositional inhomogeneity, and the high leakage currents of STO films. To address these issues, we employ atomic layer deposition(ALD) of STO films onto Pt substrates at elevated temperatures(340–380 °C). The use of low-reactivity Pt electrodes effectively mitigates the initial growth of excess Sr, ensuring enhanced compositional uniformity along the film growth direction. Coupled with ALD at high temperatures, this approach facilitates the crystallization of STO films in the as-grown state, further enhancing the crystallinity with increasing film thickness. Subsequent low-temperature post-deposition annealing (PDA) at 400 and 500 °C achieves full crystallization. This process results in a remarkable increase in the dielectric constant, reaching approximately 150. Furthermore, the absence of microcracks after PDA, attributed to the formation of adequately dense films, contributes to substantially improved dielectric properties. Consequently, these STO films exhibit an exceptionally low equivalent oxide thickness of 0.34 nm coupled with an ultralow leakage current of 3.7 × 10−8 A/cm2 at an operation voltage of 0.8 V, promising for advancing DRAM capacitors. This study presents a pathway for the sustainable scaling of DRAMs, addressing challenges in ALD-grown STO films.

Surface inversion layer effective minority carrier mobility as one of the measures of surface quality of the p-aSi:H/i-aSi:H/cSi heterojunction solar cell

The lateral transport of minority carriers in the surface inversion layer of a crystalline silicon (cSi) surface for a p-aSi:H/i-aSi:H/cSi heterojunction (SHJ) solar cell was experimentally analyzed to study defects/traps at the aSi:H/cSi interface and/or on the cSi surface. To extract the lateral surface inversion layer current, a field-effect transistor type test element group device was designed and fabricated on a cSi wafer where SHJ cells were co-integrated. By analyzing the lateral surface inversion layer current, the effective surface minority carrier mobility was calculated. The extracted mobility was one order of magnitude smaller than that of a reference MoOx/i-aSi:H/cSi structure but it increased by low-temperature post-deposition annealing with respect to the reference. This method is highly sensitive to the quality of the aSi:H/cSi interface and/or the cSi surface. The density of trap sites was estimated to be of the order of 1011 cm−2 at the aSi:H/cSi interface and/or on the cSi surface.

Improving Retention Properties of ALD-AlxOy Charge Trapping Layer for Non-Volatile Memory Application

In this work, the charge retention properties of the thermal ALD-Al2O3 trapping layer with metal-oxide-oxide-oxide-silicon (MOOOS) gate stack have been investigated for non-volatile memory application. The precursor gas concentrations were changed to engineer the band gap of the AlxOy trapping layer and the effect of AlxOy post-deposition annealing on charge retention properties was studied. The Al2O3 layer with trimethyl aluminum (TMA): H2O gas flow ratio of 1:1 and deposition pulse time of 1 s per each cycle showed the band gap of 4.49 eV , which is suitable for charge trapping layer. The memory retention properties of the ALD-Al2O3 MOOOS device was investigated by performing high-frequency capacitance-voltage measurement and compared to the device having a SiNx charge trapping layer. The 10 nm AlxOy trapping layer showed the improvement in charge retention properties after low-temperature post-deposition annealing in N2 ambient as compared to that of SiNx trapping layer with relatively large flat band voltage shift of 2.79 V. The multilayer Al2O3-MOOOS gate stack is suitable for the non-volatile memory application with good retention properties as compared to different oxides non-volatile memory devices.

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (∼17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (∼87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH−1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Low-Temperature Fabrication of Amorphous Zinc-Tin-Oxide Thin Film Transistors with In-Situ Annealing Process

This study analyzes the effect of heating during deposition on the electrical and material properties of zinc tin oxide (ZTO) thin film transistors (TFTs). Instead of post-deposition annealing (PDA) at more than 300°C, the ZTO-TFTs were fabricated by heating the substrate to 150∼200°C with 0∼20% of oxygen in chamber and low temperature PDA in air atmosphere. As a result, it was possible to fabricate devices that show similar electrical characteristics with mobilities of 5.8–27.1 cm2 V−1 s−1, Ion/Ioff of 108, and subthreshold swing of 0.15∼1.7 V dec−1, while lowering the process temperature by more than 100°C. We also proceeded to fabricate a device on polymer substrate, which is the ultimate goal of lowering the process temperature. ZTO-TFTs possessing transparency and flexibility were successfully fabricated on 125 μm polyethylene naphthalate (PEN) substrates. They showed electrical properties with a mobility of 1.7 cm2 V−1 s−1, Ion/Ioff of 108, and subthreshold swing of 0.39 V dec−1.

Communication—Improving Optoelectronic Properties of Electrochemically Deposited Cuprous Oxide Thin-Films by Low-Temperature Post-Deposition Annealing

The effect of low-temperature post-deposition annealing (PDA) on electrochemically deposited cuprous oxide (ECD-Cu2O) thin-films was investigated. The PDA at 150°C drastically improved optoelectronic properties of ECD-Cu2O films regardless of annealing atmosphere. The films exhibits free exciton luminescence at room temperature and a high hole mobility about 18 cm2/V·s. Moreover, the diffusion length of photo-generated carriers increased around two times compared to the as-deposited film. On the other hands, the PDA at 200°C significantly deteriorated the optoelectronic properties presumably due to the increase of mid-gap defects in the Cu2O films.

Cytotoxicity of Pd nanostructures supported on PEN: Influence of sterilization on Pd/PEN interface

Non-conventional antimicrobial agents, such as palladium nanostructures, have been increasingly used in the medicinal technology. However, experiences uncovering their harmful and damaging effects to human health have begun to appear. In this study, we have focused on in vitro cytotoxicity assessment of Pd nanostructures supported on a biocompatible polymer. Pd nanolayers of variable thicknesses (ranging from 1.1 to 22.4nm) were sputtered on polyethylene naphthalate (PEN). These nanolayers were transformed by low-temperature post-deposition annealing into discrete nanoislands. Samples were characterized by AFM, XPS, ICP-MS and electrokinetic analysis before and after annealing. Sterilization of samples prior to cytotoxicity testing was done by UV irradiation, autoclave and/or ethanol. Among the listed sterilization techniques, we have chosen the gentlest one which had minimal impact on sample morphology, Pd dissolution and overall Pd/PEN interface quality. Cytotoxic response of Pd nanostructures was determined by WST-1 cell viability assay in vitro using three model cell lines: mouse macrophages (RAW 264.7) and two types of mouse embryonic fibroblasts (L929 and NIH 3T3). Finally, cell morphology in response to Pd/PEN was evaluated by means of fluorescence microscopy.

Complex Surface Chemistry of Kesterites: Cu/Zn Reordering after Low Temperature Postdeposition Annealing and Its Role in High Performance Devices

A detailed study explaining the beneficial effects of low temperature postdeposition annealing combined with selective surface etchings for Cu2ZnSnSe4 (CZTSe) based solar cells is presented. After performing a selective oxidizing surface etching to remove ZnSe secondary phases typically formed during the synthesis processes an additional 200 °C annealing step is necessary to increase device performance from below 3% power conversion efficiency up to 8.3% for the best case. This significant increase in efficiency can be explained by changes in the surface chemistry which results in strong improvement of the CdS/CZTSe heterojunction commonly used in this kind of absorber/buffer/window heterojunction solar cells. XPS measurements reveal that the 200 °C annealing promotes a Cu depletion and Zn enrichment of the etched CZTSe absorber surface relative to the CZTSe bulk. Raman measurements confirm a change in Cu/Zn ordering and an increase in defect density. Furthermore, TEM microstructural investigations indica...

Nanostructured silver coatings on polyimide and their antibacterial response

We report on antibacterial activity of the silver nanostructures prepared by DC sputtering on polyimide foil (Kapton® HN). Sputtered silver nanolayers were transformed into discrete nanoislands by low-temperature post-deposition annealing. The possibility of managing nanostructure size via controlling the thickness of silver nanolayers prior to the annealing is shown. Nanostructure morphology was studied by atomic force microscopy. Atomic concentration of elements in very sample surface was determined by X-ray photoelectron spectroscopy. Integrity of silver coatings was determined by measuring its electrical sheet resistance. Antibacterial properties of the polyimide foils both pristine and silver coated before and after annealing were examined by a drip method using two bacterial strains, Escherichia coli and Staphylococcus epidermidis frequently involved in infections associated with a biofilm formation.

Low-temperature post-deposition annealing investigation for 3D charge trap flash memory by Kelvin probe force microscopy

The influence of post-deposition annealing (PDA) temperature condition on charge distribution behavior of HfO2 thin films was systematically investigated by various-temperature Kelvin probe force microscopy technology. Contact potential difference profiles demonstrated that charge storage capability shrinks with decreasing annealing temperature from 1,000 to 500 °C and lower. Compared to 1,000 °C PDA, it was found that 500 °C PDA causes deeper effective trap energy level, suppresses lateral charge spreading, and improves the retention characteristics. It is concluded that low-temperature PDA can be adopted in 3D HfO2-based charge trap flash memory to improve the thermal treatment compatibility of the bottom peripheral logic and upper memory arrays.

Optimization of electrical properties of Al/LaAlO3/indium tin oxide capacitor by adjusting oxygen pressures in pulsed laser deposition and applying post-deposition annealing at low temperatures

This work presents a physicochemical analysis of the characteristics of high-k lanthanum aluminate LaAlO3 (LAO) that is deposited on indium tin oxide (ITO)/glass substrates by pulsed laser deposition at various oxygen pressures and then undergoes low-temperature post-deposition annealing (PDA). Samples that are deposited at a low oxygen pressure of 0.067Pa have a higher leakage current density than samples deposited at 0.27Pa oxygen pressure owing to the imperfect stoichiometry of LAO that rises from deficient oxygen atoms in LAO. The leakage current increased with the oxygen pressure over 0.27Pa because of the degradation of either surface roughness of LAO or the interfacial layer that is composed of a mixture of metal oxides. PDA treatment at a low temperature of 200 or 300°C in O2 was applied to samples that were deposited at an oxygen pressure of 0.27Pa. These samples had a relatively low leakage current density. PDA treatment at 300°C improved the leakage current density of samples by approximately an order of magnitude at an electrical field of 1MV/cm. The incorporation of oxygen atoms during PDA at 300°C in O2 ambient increases breakdown field of capacitors with an Al/LAO/ITO structure from 7 to 14MV/cm by reducing the surface roughness of LAO and improving the stoichiometry and bond structures of the LAO films.

Fabrication and Electrical Properties of Thermally Oxidized p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors on 4H-SiC C-Face

We characterized the SiO2/SiC interface by capacitance–voltage (C–V) measurement in order to obtain p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) on the 4H-SiC(0001̄) C-face. Wet gate oxidation was preferable for both n- and p-type MOS capacitors, but p-type MOS interface properties were inferior to those of n-type MOS capacitors. The cause of the large flat-band shift for the p-type sample was discussed on the basis of C–V measurements by the light illumination technique. We also investigated the influence of the high-temperature annealing process after gate oxidation on the MOS interface properties. The p-type MOS interface was more sensitive to the annealing process than the n-type MOS interface. We fabricated 4H-SiC C-face p-channel MOSFETs by wet gate oxidation and low-temperature postdeposition annealing in He–H2 ambient. The normal FET operation was accomplished on the 4H-SiC C-face for the first time. Those devices, however, indicated low channel mobility and large threshold voltage.

Compositional and metal-insulator transition characteristics of sputtered vanadium oxide thin films on yttria-stabilized zirconia

Vanadium dioxide (VO2) thin films have been shown to undergo a rapid electronic phase transition near 70 °C from a semiconductor to a metal, making it an interesting candidate for exploring potential application in high speed electronic devices such as optical switches, tunable capacitors, and field effect transistors. A critical aspect of lithographic fabrication in devices utilizing electric field effects in VO2 is the ability to grow VO2 over thin dielectric films. In this article, we study the properties of VO2 grown on thin films of Yttria-Stabilized Zirconia (YSZ). Near room temperature, YSZ is a good insulator with a high dielectric constant (\(\epsilon _{\rm r} > 25\)). We demonstrate the sputter growth of polycrystalline VO2 on YSZ thin films, showing a three order resistivity transition near 70 °C with transition and hysteresis widths of approximately 7 °C each. We examine the relationship between chemical composition and transition characteristics of mixed phase vanadium oxide films. We investigate changes in composition induced by low temperature post-deposition annealing in oxidizing and reducing atmospheres, and report their effects on electronic properties.

Effects of low temperature annealing on the ultrathin La2O3 gate dielectric; comparison of post deposition annealing and post metallization annealing

This work reports the effects of low-temperature post-deposition annealing (PDA) and post-metallization annealing (PMA) on the electrical properties of ultrathin (with EOT ranging from 1.29 nm to 2.33 nm) La2O3 gate dielectric films. We found that positive charges were generated during the PDA as evidenced by the negative flat-band voltage (VFB) shift. Forming of La-silicate interface layer and a reduction in the channel mobility are found for the PDA samples at temperature higher than 300°C. Better electrical characteristics were achieved by the PMA. The PMA sample has a peak channel mobility of 319 cm2 /Vs.

Correlation between scanning-probe-induced spots and fixed positive charges in thin HfO2 films

Scanning tunneling microscopy observations revealed unstable species that likely act as fixed positive charges in thin HfO2 films. The density of these species can be practically reduced by low-temperature postdeposition annealing (∼550°C). The results of various annealing conditions suggest that hydrogenous species created by the reaction of moisture with as-deposited HfO2 films causes this type of fixed positive charges in the films.