Low-temperature poly-Si Thin-film Transistors Research Articles

스텝 어닐링에 의한 저온 및 고온 n형 다결정 실리콘 박막 트랜지스터의 전기적 특성 분석

In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT's. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT's due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.

실리콘 게이트전극을 갖는 고온소자와 금속 게이트전극을 갖는 P형 저온 다결정 실리콘 박막 트랜지스터의 전기특성 비교 연구

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.

High-performance poly-silicon TFTs with high-k Y2O3 gate dielectrics

In this paper, we describe a poly-Si thin-film transistor (TFT) incorporating a high-k Y2O3 gate dielectric for different annealing times. The high-k Y2O3 poly-Si TFT device annealed in O2 gas for 60 min exhibited better electrical characteristics in terms of a high effective carrier mobility of 32.7 cm2 V−1 s−1, small subthreshold slope of 269 mV dec−1, and high Ion/Ioff current ratio of 1.83 × 107. This result is attributed to a smooth surface, structural relaxation, and a low trap-state density at the Y2O3/poly-Si interface after a long time thermal annealing. All of these results suggest that the 60 min annealed poly-Si Y2O3 TFT is a good candidate for high-performance low-temperature poly-Si TFTs.

Self-Aligned Metal Double-Gate Low-Temperature Polycrystalline Silicon Thin-Film Transistors on Glass Substrate Using Back-Surface Exposure

Improving the device structure and quality of polycrystalline silicon (poly-Si) films is essential for enhancing the performance of poly-Si thin-film transistors (TFTs). A multigate structure can potentially be used to realize ideal poly-Si TFTs. We combined a self-aligned metal double-gate structure (i.e., a structure with metal top and bottom gates) with a large-grained poly-Si film. Then, we fabricated high-performance n-channel (n-ch) and p-channel (p-ch) low-temperature poly-Si TFTs on a glass substrate at 550 °C. The nominal field-effect mobilities of the n-ch and p-ch TFTs were 638 and 156 cm2 V-1 s-1, respectively, and the s-values of both the TFTs were nearly 130 mV/dec.

(Invited) Stabilities of TFTs under Bias-Stress

The bias-induced instability in hydrogenated amorphous silicon (a-Si:H), amorphous indium-gallium-zinc-oxide (a-IGZO) and low temperature poly-Si (LTPS) thin-film transistors (TFTs) is investigated. Gate bias-induced charge trapping at the active-layer/gate-insulator interface and into the gate-insulator, is the origin of positive threshold voltage (Vth) shift in a-Si:H and a-IGZO TFTs. The time dependence of the Vth shift (Vth) in a-Si:H and a-IGZO TFTs is explained by the charge trapping model rather than bond breaking model. The swing degradation-related Vth in LTPS TFTs, originates from the generation of grain boundary trap states, interface trap states and fixed oxide charge, when a negative gate-bias is applied. A good fit of the measured results is obtained by the bond-breaking model. Analysis of the charge trapping and bond breaking mechanisms is used to understand the electrical stability of the three kinds of TFTs.

Embedded nonvolatile memory devices with various silicon nitride energy band gaps on glass used for flat panel display applications

Nonvolatile memory (NVM) devices with a nitride–nitride–oxynitride stack structure on a rough poly-silicon (poly-Si) surface were fabricated using a low-temperature poly-Si (LTPS) thin film transistor technology on glass substrates for application of flat panel display (FPD). The plasma-assisted oxidation/nitridation method is used to form a uniform oxynitride with an ultrathin tunneling layer on a rough LTPS surface. The NVMs, using a Si-rich silicon nitride film as a charge-trapping layer, were proposed as one of the solutions for the improvement of device performance such as the program/erase speed, the memory window and the charge retention characteristics. To further improve the vertical scaling and charge retention characteristics of NVM devices, the high-κ high-density N-rich SiNx films are used as a blocking layer. The fabricated NVM devices have outstanding electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low subthreshold swing, a low operating voltage of less than ±9 V and a large memory window of 3.7 V, which remained about 1.9 V over a period of 10 years. These characteristics are suitable for electrical switching and data storage with in FPD application.

Effects of $\hbox{CF}_{4}$ Plasma Treatment on the Electrical Characteristics of Poly-Silicon TFTs Using a $ \hbox{Tb}_{2}\hbox{O}_{3}$ Gate Dielectric

In this paper, we developed high-k Tb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> poly-Si thin-film transistors (TFTs) using different CF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> plasma power treatments. The high-k Tb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> poly-Si TFT device with a 20-W plasma power exhibited better electrical characteristics in terms of a highly effective carrier mobility, a high-driving current, a low-threshold voltage, a small subthreshold slope, and a high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> current ratio. This result is attributed to the incorporation of fluorine atoms into the Tb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /poly-Si interface to reduce the trap-state density. The high-k Tb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> poly-Si TFT prepared under a 20-W CF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> plasma power also enhanced electrical reliabilities, including hot carrier and positive bias temperature instability. All of these results suggest that the CF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> plasma-treated poly-Si Tb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> TFT is a good candidate for high-performance low-temperature poly-Si TFTs.

Fabrication of a Uniform Low Temperature Poly-Si TFT Array by Optimized Field Aided Lateral Crystallization

In this study, a 2 in. Ni field aided lateral crystallization (FALC) poly-Si thin-film transistor (TFT) array was fabricated at the maximum process temperature of using an optimized current density distribution design. We investigated the correlation between crystallization and transistor characteristics in terms of transistor position in the array. Because an identical current density in the channel region of each pixel transistor was favorable to achieve uniform crystallization, an optimal common electrode design was chosen via Mathcad simulation. After the crystallization process, it was confirmed that the crystallinity variation in the transistor channels agreed well with the predicted simulation results. Furthermore, the positional variation in important transistor parameters in the array showed a good match with that of crystallization. The mean threshold voltage was 5.9 V while the mean mobility was with a variation of 9.8%. These values suggested that the uniform Ni-FALC poly-Si TFT arrays fabricated by the optimal design of the electrode were applicable to the active matrix organic light emitting display backplane.

Development of a new hybrid silicon thin‐film transistor fabrication process

A new hybrid silicon thin‐film transistor (TFT) fabrication process using the DPSS laser crystallization technique was developed in this study to realize low‐temperature poly‐Si (LTPS) and a‐Si:H TFTs on the same substrate as a backplane of the active‐matrix liquid crystal flat‐panel display (AMLCD). LTPS TFTs were integrated into the peripheral area of the active‐matrix LCD panel for the gate driver circuit, and a‐Si:H TFTs were used as a switching device of the pixel electrode in the active area. The technology was developed based on the current a‐Si:H TFT fabrication process in the bottom‐gate, back‐channel etch‐type configuration. The ion‐doping and activation processes, which are required in the conventional LTPS technology, were thus not introduced, and the field effect mobility values of 4∼5 cm2/V·s and 0.5 cm2/V·s for the LTPS and a‐Si:H TFTs, respectively, were obtained. The application of this technology was demonstrated on the 14.1” WXGA+(1440 × 900) AMLCD panel, and a smaller area, lower power consumption, higher reliability, and lower photosensitivity were realized in the gate driver circuit that was fabricated in this process compared with the a‐Si:H TFT gate driver integration circuit

Electrical Characteristics of Low-Temperature Poly-Silicon Thin-Film Transistor Using a Stacked Pr2O3/SiOxNy Gate Dielectric

In this paper, we have developed a stacked Pr2O3/SiOxNy gate dielectric into low-temperature poly-Si thin-film transistors (TFTs). High-performance TFT devices can be achieved including a high effective carrier mobility, high driving current, small subthreshold swing, and high ION/IOFF current ratio. This phenomenon is attributed to the smooth Pr2O3/poly-Si interface and the low interface trap density provided by N2O plasma treatment. The presence of an SiOxNy buffer layer also enhanced the electrical reliability of the Pr2O3/poly-Si TFT. All of these results suggest that a high-k Pr2O3 gate dielectric prepared the buffer layer is a good candidate for high-performance TFTs.

Effects of Oxynitride Buffer Layer on the Electrical Characteristics of Poly-Silicon TFTs Using $\hbox{Pr}_{2}\hbox{O}_{3}$ Gate Dielectric

In this paper, we have developed high-k Pr2O3 poly-Si thin-film transistors (TFTs) using different N2O plasma power treatments. High-k Pr2O3 poly-Si TFT devices using a 200-W plasma power exhibited better electrical characteristics in terms of high effective carrier mobility, high driving current, small subthreshold slope, and high ION/IOFF current ratio. This result is attributed to the smooth Pr2O3/poly-Si interface and low interface trap density. Pr2O3 poly-Si TFT with a 200-W N2O plasma power also enhanced electrical reliabilities such as hot carrier and positive bias temperature instability. All of these results suggest that a high-k Pr2O3 gate dielectric with the oxynitride buffer layer is a good candidate for high-performance low-temperature poly-Si TFTs.

Impacts of Fluorine Ion Implantation With Low-Temperature Solid-Phase Crystallized Activation on High- $\kappa$ LTPS-TFT

In this letter, fluorine ion implantation with low- temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> low-temperature poly-Si thin- film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> is achieved because 25% grain- boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric and fluorine preimplantation can simultaneously achieve low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ~ 1.32 V, excellent subthreshold swing ~0.141 V/dec, and high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> current ratio ~1.98 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> .

Characteristics of PBTI and Hot Carrier Stress for LTPS-TFT With High-$\kappa$ Gate Dielectric

In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with gate dielectric are well investigated for the first time. Under room temperature stress condition, the. PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for LTPS-TFT. In addition, an abnormal behavior of the degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the gate dielectric and the poly-Si grain boundaries.

Crystallinity Evaluation by Microwave Photoconductivity Decay in Double-Layered Polycrystalline Silicon Thin Films Crystallized by Solid Green Laser Annealing

The crystallinity of double-layered polycrystalline silicon thin films crystallized by solid green laser annealing (GLADLAX poly-Si) was evaluated in comparison with that of the conventional green-laser-annealed single-layer poly-Si (GLA SL poly-Si) by reflectance peak mapping measurement of microwave photoconductivity decay (µ-PCD), which measures the recombination lifetime of photoexcited carriers. As a result, the anisotropy of the poly-Si was observed as a difference in the reflectance-peak. Furthermore, the upper layer of the GLADLAX poly-Si had a larger microwave reflectance-peak compared with the GLA single-layer poly-Si, and correlation was confirmed between the reflectance-peak of the poly-Si and the electrical performance of thin film transistor (TFT). Thus, it can be said that crystallinty evaluation by µ-PCD measurement are promising for application to next-generation low-temperature poly-Si TFTs.

Fabrication and characterization of metal-oxide-nitride-oxynitride-polysilicon nonvolatile semiconductor memory device with silicon oxynitride (SiOxNy) as tunneling layer on glass

A nonvolatile semiconductor memory (NVSM) device with a metal-oxide-nitride-oxynitride-polysilicon (MONOS) structure on a rough polysilicon (poly-Si) surface was fabricated using a low-temperature process and poly-Si thin film transistor (TFT) technology on glass. For the fabrication of the NVSM device on glass, plasma-assisted oxynitridation was carried out using nitrous oxide (N2O) as a reactive gas, due to the very rough surface of the poly-Si on glass annealed using an excimer laser. The ultrathin SiOxNy films obtained using the N2O plasma have a very uniform distribution on poly-Si and similar contents of oxygen and nitrogen in the peaks and valleys of the grains. The NVSM devices having a MONOS structure with a tunneling layer of ultrathin SiOxNy on glass have suitable switching and charge retention characteristics for data storage. The results demonstrate that the NVSM device made using low-temperature poly-Si TFT technology on glass reported in this paper can be used in various types of display devices.

Reliability of Low Temperature Polycrystalline Silicon Thin-Film Transistors with Ultrathin Gate Oxide

We analyzed the reliability against the hot-carriers effect and Joule heating effects of low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with an ultrathin gate oxide film deposited by sputtering. For the hot-carrier effect, although the generation of hot-carriers was enhanced in TFT with a thin gate oxide film, no marked degradation due to direct constant voltage (DC) stress was observed in the electric characteristics even when the thickness of the gate oxide film was 9.5 nm. Regarding the effect of Joule heating on the reliability, the thickness of the oxide film markedly affected the TFT characteristics. A new degradation mode different from the conventional mode with a shift in threshold voltage owing to heat generation was observed when the oxide film was extremely thin in spite of small amount of heat generated during the application of DC stress. Regarding the reliability of the low-temperature poly-Si TFT with an ultrathin gate oxide film, the results revealed that a new degradation mode develops due to heat generation.

An Offset-Compensated LVDS Receiver with Low-Temperature Poly-Si Thin Film Transistor

The poly-Si thin film transistor (TFT) shows large variations in its characteristics due to the grain boundary of poly-crystalline silicon. This results in unacceptably large input offset of low-voltage differential signaling (LVDS) receivers. To cancel the large input offset of poly-Si TFT LVDS receivers, a full-digital offset compensation scheme has been developed and verified to be able to keep the input offset under 15 mV which is sufficiently small for LVDS signal receiving.

Enhanced Planar Poly-Si TFT EEPROM Cell for System on Panel Applications

In this work an enhanced electrically erasable programmable read-only memory (EEPROM) device comprised of twin low-temperature poly-Si thin-film transistors (TFTs) was fabricated for potential application to system-on-panel technology. Also, two kinds of memory devices with different overlap areas were developed to investigate the gate-coupling effect. The memory window of 4.8 and 4 V can be obtained at a programming voltage of 18 V, separately, for the fully overlapped EEPROM and the one with a 1 μm length overlap between the gate and source/drain. The excellent memory characteristics of the fully overlapped TFT EEPROM cell are attributed to the enhanced gate-coupling ratio by maximizing the overlap coverage between the gate electrode and the source/drain regions.

A Novel Selected Area Laser Assisted (SALA) System for Crystallization and Doping Processes in Low-Temperature Poly-Si Thin-Film Transistors

CMOS poly-Si thin-film transistors (TFTs) were fabricated through crystallization and GILD processes by a novel selected area laser assisted (SALA) system. The system enables a local area irradiation of small beams of a pulsed solid-state laser of frequency tripled Nd:YAG. The novel TFT process eliminated 3 doping mask steps of the conventional process. On-off current ratios for both types of poly-Si TFTs were improved by SALA. The field effect mobility of n- and p-channel TFTs is 84 cm 2 /Vs and 75 cm 2 /Vs, respectively.

Development of line-shaped optical system for green laser annealing used in the manufacture of low-temperature poly-Si thin-film transistors

We have developed a new optical system that transforms the circle profile beam generated with near-Gaussian intensity distribution by a pulse green laser (YAG2omega laser; second harmonics of a Q-switched Nd:YAG laser) into a line-profile beam. For homogenization in the longitudinal direction, we employed a waveguide plate-type homogenizer. We successfully reduced interference fringes. In the width direction, the laser beam was focused up to the limited M2 value. This transformed beam has a uniform distribution to within 5% in the longitudinal direction, and it is approximately 100 mm long and 40 microm wide.