Low Swing Research Articles

Estimation of bandwidth, voltage swing and DC coefficients for VLSI interconnects: current mode technique

ABSTRACT Necessity of bandwidth requires the effective use of it for high speed data transmission and faster read/write operation in memory cells. In this paper the transfer function expressions for RC interconnect line is presented for resistive load. The line delay, bandwidth and step response for current and voltage mode signalling is formulated. The current mode and voltage mode signalling provides the 3-dB bandwidth of 6.8 GHz and 3.1 GHz, respectively. An interconnect line modelled as either RLC or RC line depending upon input signal rise time, damping, and range of interconnect length with significant inductance effect is investigated for global interconnect lines. Low swing for column bit line in memory architectures is very important and estimated in terms of dc coefficients. For RC global interconnect of 10 mm, a swing of 0.382 V is obtained for current mode signalling, when a power supply of 1.8 V is applied to the network. DC coefficient and steady state value has been obtained which is significant for power computation on column bit line. It is also analytically validated by SPICE and MATLAB simulations.

A novel gain boost and slew rate enhanced CMOTA

Abstract The design of a novel current mirror operational transconductance amplifier is proposed to address the issues of low gain and limited swing rate under conditions of low voltage and power consumption. In order to improve the gain and swing rate of the amplifier, the increase and lift technology and swing rate increase technology are introduced to the traditional op-amp Simulation and verification based on 0.18 μm BCD process and candence. The results show that under 10 pF load capacitance, the gain is increased by 42 dB and the swing rate is increased by 130 times compared with the conventional transconductance op amp.

Thermodynamic analysis of electric field enhanced CO2 capture by moisture-sensitive quaternary ammonium-based sorbents

Climate change incurred by the increasing amount of CO2 released into the atmosphere has become a global priority, and triggers the development of carbon capture, utilization, and storage. Low energy requirement and cost by employing moisture swing process make quaternary ammonium-based materials applicable for CO2 capture. The moisture-sensitive sorbents suffer decreased CO2 affinity and cyclic capacities with moderate or high humidity, while water vapor ubiquitously exists in flue gas or ambient air. The effect of applying electric field on CO2 adsorption, especially the water-involved proton transfer step, by quaternary ammonium-based sorbents in the existence of water, is analyzed. The discrepancy in the hydrophilicity between reactant and product species is enhanced by the electric field, which indicates more favorable chemisorption. Thermodynamics of CO2 adsorption coupling interfacial water evaporation under the electric field are depicted with changes of enthalpy and free energy calculated. Therefore, the rationality of electric field enhanced CO2 capture of quaternary ammonium-based sorbents in moist circumstance is theoretically validated, providing the methodology of optimizing moisture swing adsorption from process intensification apart from material design.

Burnable Absorber Design Study for a Passively-Cooled Molten Salt Fast Reactor

The Passively-Cooled Molten Salt Fast Reactor (PMFR) is one of the advanced design concepts of the Molten Salt Fast Reactor (MSFR) which utilizes a natural circulation for the primary loop and aims to attain a long-life operation without any means of fuel reprocessing. For an extended operation period, it is necessary to have enough fissile material, i.e., high excess reactivity, at the onset of operation. Since the PMFR is based on a fast neutron spectrum, direct implementation of a burnable absorber concept for the control of excess reactivity would be ineffective. Therefore, a localized moderator concept that encircles the active core has been envisioned for the PMFR which enables the effective utilization of a burnable absorber to achieve low reactivity swing and long-life operation. The modified PMFR design that incorporates a moderator and burnable absorber is presented, where depletion calculation is performed to estimate the reactor lifetime and reactivity swing to assess the feasibility of the proposed design. All the presented neutronic analysis has been conducted based on the Monte Carlo Serpent2 code with ENDF/B-VII.1 library.

Comparison of side-cutting maneuvers versus low impact baseball swing on knee ligament loading in adolescent populations

BackgroundHigh impact sports are associated with an increased incidence rate for knee ligament injuries, specifically pertaining to the anterior cruciate ligament and medial collateral ligament. What is less clear is (i) the extent to which high impact activities preferentially load the anterior cruciate ligament versus the medial collateral ligament, and (ii) whether both ligaments experience similar stretch ratios during high loading scenarios. Therefore, the goal of this project was to assess how different loading conditions experienced through more at-risk sporting maneuvers influence the relative displacements of the anterior cruciate ligament and medial collateral ligament. The focus of the study was on adolescent patients – a group that has largely been overlooked when studying knee ligament biomechanics. MethodsThrough kinetic knee data obtained through motion capture experimentation, two different loading conditions (high vs low impact) were applied to 22 specimen-specific adolescent finite element knee models to investigate the biomechanical impact various sporting maneuvers place on the knee ligaments. FindingsThe high impact side cutting maneuver resulted in 102% and 47% increases in ligament displacement compared to the low impact baseball swing (p < 0.05) for both the anterior cruciate ligament and medial collateral ligament. InterpretationQuantifying biomechanical risks that sporting activities place on adolescent subjects provides physicians with insight into knee ligament vulnerability. More specifically, knowing the risks that various sports place on ligaments helps guide the selection of sports for at-risk patients (especially those who have undergone knee ligament surgery).

Research on the Dynamic Characteristics of a Low Recoil Swing Chamber Gun Based on the Cased Telescoped Ammunition and Rarefaction Wave Gun Technology

Based on the theory of a low-recoil rarefaction wave(RAVEN)gun firing cased telescoped ammunition(CTA), the equation system of interior ballistics and kinematics also dynamics were established. The dynamic characteristic curves were obtained by numerical simulation analysis, and the results were verified by firing tests. Compared with traditional closed-breech guns, the low recoil force swing chamber gun keeps the projectile’s muzzle velocity basically unchanged, while the maximum recoil is reduced by up to 74%. Based on these results, the parameters of the inertial breech buffer spring were optimized by numerical simulation optimization algorithms which efficiency is faster than using virtual prototyping technology, while the maximum recoil force of the breech reduced by 14.2% without affecting system performance and structural installation size, which effectively improved the overall performance of the weapon system.

Simulation Research of rigid chain failure in a modular gunpowder delivery machine

Based on the theory of a low-recoil rarefaction wave (RAVEN) gun firing cased telescoped ammunition (CTA), the models of interior ballistics and dynamics were established. The dynamic characteristic curves were obtained by numerical simulation analysis, and the results were verified by firing tests. Compared with traditional closed-breech guns, the low recoil force swing chamber gun keeps the projectile’s muzzle velocity basically unchanged, while the maximum recoil is reduced by up to 74%. Based on these results, the parameters of the inertial breech buffer spring were optimized while the maximum recoil force of the breech reduced by 14.2% without affecting system performance and structural installation size, which effectively improved the overall performance of the weapon system.

A monolithic gallium nitride‐based two‐phase synchronous buck converter with high operating frequency

AbstractThe need for a high‐frequency and high‐efficiency gallium nitride (GaN)‐based buck converter that can be controlled directly by a low swing pulse width‐modulated (PWM) signal, without the need for additional buffers or preamplifiers, poses a significant challenge in the field of power conversion and dynamically power supply applications. To solve this problem, this letter presents a monolithic two‐phase synchronous buck converter, fabricated using a 0.25‐um GaN‐on‐Si process, integrated both the drivers and power stage transistors, without requiring additional buffers or preamplifiers. So, the proposed converter can be directly controlled by a PWM signal with a swing of only 1 V (−0.5 to 0.5 V). At a 100‐MHz switching frequency, the converter achieves a maximum output power of 12 W with a power stage efficiency of 82%. The converter includes two identical half‐bridge Monolithic Microwave Integrated Circuit (MMICs), and with the frequency multiplication property of multi‐phase topology, the equivalent switching frequency can reach 200 MHz in the open‐loop operating mode. The experimental results show that the converter can track a 40‐MHz bandwidth envelope signal (256 QAM, 6 dB PAPR) with 80.1% efficiency.

Bias-Independent Inter-Modulation Method for Simultaneously Measuring Low-Frequency Modulation and Bias Half-Wave Voltages of Mach-Zehnder Modulators

A bias-independent inter-modulation method is proposed and demonstrated for measuring low-frequency modulation and bias half-wave voltages of Mach-Zehnder modulators (MZMs). The method consists of simultaneous sinusoidal modulation on the modulation and bias ports of the MZM under test. Sinusoidal-modulated sidebands heterodyne with each other and generate the desired inter-modulation products after photodetection, which allows extracting both the modulation depth and half-wave voltage for the modulation and bias ports of the MZM. Our method is independent of bias voltages of the MZM, which can be canceled out by carefully choosing the sinusoidal-modulation frequencies. Moreover, the proposed method enables the low swing voltage for measuring both the modulation depth and half-wave voltage of MZMs. Experiments indicate that the proposed method features the simple setup and high accuracy for low-frequency response measurement ranging from 1 Hz to 1 MHz.

Proposal and performance evaluation of delta doped negative capacitance tunneling field transistor: A simulation study

Here we proposes and optimizes a delta doped dual spacer negative capacitance TFET to improve ON current, steeper sub threshold slope, and ON to OFF current ratio. The inclusion of the delta layer and high K spacer on the source side improves the characteristics by increasing the electric field and lowering the surface potential at the source channel interface. The incorporation of the FE layer in the gate stack creates the negative capacitance effect and improves the performances due to voltage amplification process. Here, FE-HFO2 is taken as a ferroelectric material. A very high current ratio of the order 1.8 × 1012 with a substantially low average sub threshold swing of 18 mV/decade is achieved which make it suitable for low power applications. Finally, for optimized NCFETs, the influence of temperature (200 K–350 K) is examined at tfe = 5 nm for switching characteristics.

Thermal energy storage based on cold phase change materials: Charge phase assessment

• Experimental study of water–ice energy storage behavior at density inversion temperature . • Experimental analysis of a finned shell & tube latent heat thermal energy storage . • Effect of temperature, mass flow rate and charge direction on storage performance. • Presence of metastable phase is confirmed. Integration of thermal energy storage in energy systems provides flexibility in demand–supply management and in supporting novel operational schemes. In a combined heat and power cycle, it has been shown that integration of cold thermal energy storage is beneficial to fine-tune electric power and heating/cooling production profiles to better match the load demand. Latent heat storage systems have the advantage of compactness and low temperature swing, however storage performance analysis on large scale setup operating around the density inversion temperature is still limited. In this work, a shell & tube, latent heat based cold thermal energy storage was studied around the density inversion temperature of ice-water at 4 °C and the performance was characterized. Sensitivity analyses on heat transfer fluid flow rate, flow direction and inlet temperature were performed. The results show 27% power increase with doubled mass flow and 18% shorter charge time with 2 °C lower charge temperature. Contrary to general expectations during solidification, the cold thermal energy storage actually shows between 5% and 6% better thermal performance and reducing instant icing power jump of 36% due to supercooling with downwards cold heat transfer fluid flow in cooling charge cycle due to buoyancy change around density inversion temperature. This fact highlights the importance of accounting for the buoyancy effect due to density inversion when designing the operational schemes of large size cold thermal energy storage.

Technology scaling impact on VLSI interconnect and low swing signaling technique

Technology scaling impact on VLSI interconnect and low swing signaling technique

A wide swing charge sensitive amplifier for a prototype Si–W EM calorimeter

A wide swing charge sensitive amplifier (CSA) has been developed, as a part of a front-end electronics (FEE) readout ASIC, for a prototype silicon tungsten (Si–W) based electromagnetic (EM) calorimeter. The CSA, designed in 0.35μm N-well CMOS technology using 5V MOS transistors, has a wide linear operating range of 2.6 pC w.r.t the input charge with a power dissipation of 2.3 mW. A noise figure (ENC) of 820 e− at 0 pF of detector capacitance with a noise slope of 25 e−/pF has been achieved (when followed by a CR-RC2 filter of 1.2μs peaking time). This design of CSA provides a dynamic range (ratio of maximum detectable signal to noise floor) of 79 dB for the maximum input charge of 2.6 pC when connected to a silicon detector with a capacitance of 40 pF. Using folded cascode architecture-based input stage and low voltage high swing current mirrors as the load, the CSA provides an enlarged output swing by biasing the output node towards one supply rail and utilizing the voltage range towards the opposite rail. The design philosophy works for both polarities of a large input signal. This paper presents the design of CSA with a wide negative output swing for an anticipated input signal of positive polarity in the target application with a known detector biasing scheme.

Improvement in carrier mobility through band-gap engineering in atomic-layer-deposited In-Ga-Zn-O stacks

This paper reports the performance improvement of heterojunction channel field-effect transistor using an atomic-layer-deposited InGaZnO (IGZO) channel on basis of a band alignment. The heterojunction stack consisted of a 5 nm-thick In0.61Ga0.16Zn0.23O confinement layer (CL) and a 2 nm-thick In0.52Ga0.32Zn0.15O barrier layer (BL). Band-gap engineering through cation composition and thickness modulation of each layers allowed free electron diffusion from the In0.52Ga0.32Zn0.15O BL to the In0.61Ga0.16Zn0.23O CL and carriers confinement in CL, leading to the improvement in field-effect mobility. The control transistor with 5 nm-thick IGZO CL layer had a mobility of 33.4 cm2/Vs, whereas the heterojunction transistor with 2 nm-thick IGZO BL exhibited a higher mobility of 50.7 cm2/Vs as well as low gate swing of 89 mV/decade as a result of carrier transporting boosting. Moreover, the corresponding heterojunction channel transistors exhibited better gate bias stability due to the mitigation of gap states creation and passivating behavior by introducing the 2 nm-thick IGZO BL.

A High-Speed Fully Differential Telescopic Op-Amp for Active Filter Designs in V2X Applications

In this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascode current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04[Formula: see text]dB lower frequency gain, 1.81[Formula: see text]GHz gain-bandwidth product (GBW) and 51.9∘ phase margin under 5[Formula: see text]pF load capacitance. The design consumes a total current of 11.9[Formula: see text]mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120[Formula: see text][Formula: see text]m[Formula: see text]m layout area.

A Low Power SAR ADC with Digital Error Correction Technique for Wearable and Implantable ECG Devices

Aims: This study aims to propose an 8-bit differential input low-power Successi,e Approximation Register (SAR) ADC with digital error correction technique for sensing bio-potential signals in wearable and implantable devices. Background: As dynamic comparators have the advantages of full swing output, low power consumption, high speed, and high impedance at the input, they are preferably used in energy-efficient SAR ADC’s. However, since the dynamic comparator is the most frequently used block in SAR ADC, research is ongoing to reduce its μW power further. Also, as the offset voltage of the comparator affects the linearity of ADC, it must be minimized. Linearity can further be improved by calibrating the output of ADC, and extensive surveys on the calibration methods prove that the addition- only digital error correction method is efficient in terms of power. Objective: The objective of this study is to design a low-power and low-offset dynamic comparator intended for SAR ADC to achieve highly linear digital output. In addition to this, the objective is to implement a power-efficient digital error correction technique for the output of SAR ADC to overcome the non-idealities due to process variations. Method: As power consumption is proportional to the number of transistors, the proposed comparator is a design obtaining the same output as the existing dynamic comparators with reduced transistor count. The proposed comparator, along with low power full swing three-input XOR logic gate, is implemented in SAR ADC with digital error correction technique in cadence 45 nm technology files, and its performance parameters are simulated. Results: The layout of the proposed dynamic comparator occupies an area of 3 μm2. The simulation results of this comparator with a load of 1 pF show that it has a total offset of 11.2 mV, a delay of 0.9 ns, and power consumption of 24 nW. It also achieves a gain of 49.5, i.e., 33.86 dB. The 8-bit ADC, along with the digital error correction technique operating at 143-kS/s and under 0.6 V supply voltage simulated in 45nm technology, consumes only 0.12 μW of power. The DNL and INL errors obtained are +0.22/-0.2 LSB and -0.28 LSB, respectively. SNR limited by noise is 48.25 dB, SFDR is 48.64 dB, and ENOB achieved is 7.72. Conclusion: To satisfy the requirement of the wearable and implantable devices, a low-power SAR ADC with good linearity is designed using a low-power and low-offset dynamic comparator. A digital error correction technique using a low-power XOR logic gate is implemented at the SAR ADC output to minimize the non-idealities due to the process variations.

Restoration circuits for Low power Reduce Swing of 6T and 8T SRAM Cell With Improved Read and Write Margins

A paper that examines the factors thataffect the Static Noise Margin (SNM) of a StaticRandom Access memories. At an equivalent time,they specialise in optimizing Read and Writeoperation of 8T SRAM cell which is best than 6TSRAM cell Using Swing Restoration Dual NodeVoltage. The read and Write operation and improveStability analysis. This SRAM technique on thecircuit or architecture level is required to improveread and write operation. during this paperComparative Analysis of 6T and 8T SRAM Cellswith Improved Read and Write Margin is completedfor 180 nm Technology with Cadence Virtuososchematics Tool.This Paper is organized as follows: thecharacteristics of 6T SRAM cell are described arerepresented in section VIII. In section IX, proposed8T SRAM cell is described. In section X, Standard8T SRAM cell is described. Section XI includes thesimulation results which give comparison of variousparameters of 6T and 8T SRAM cells. In Section XIISimulation Results and DC analysis and sectionXIII conclusion the work.

Low Power Clock Generator Design With CMOS Signaling

The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more clock generators with increased performance (frequency and jitter) and lower power budgets. The traditional current mode low swing clock generators were used widely in industry about 10 years ago. Although it had the advantage of higher supply noise rejection due to the differential nature of the architectures, however, it had the disadvantages of high-power consumption, large layout area, and not friendly to process scaling. Contrary to current mode low swing design, clock generator architectures with CMOS large swing signaling, which have advantages of low power consumption, small area, and based on circuits friendly to process scaling, have been widely adopted for clocking generation in the industry since 2009. In this paper, phase locked loops, delay locked loops, phase interpolators, high resolution digital to time converter and clock distribution techniques with CMOS large swing signaling will be discussed and reviewed.

LMI based antiswing adaptive controller for uncertain overhead cranes

This paper proposes an adaptive anti-sway controller for uncertain overhead cranes. The state-space model of the 2D overhead crane with the system parameter uncertainties is shown firstly. Next, the adaptive controller which can adapt with the system uncertainties and input disturbances is established. The proposed controller has ability to move the trolley to the destination in short time and with small oscillation of the load despite the effect of the uncertainties and disturbances. Moreover, the controller has simple structure so it is easy to execute. Also, the stability of the closed-loop system is analytically proven. The proposed algorithm is verified by using Matlab/Simulink simulation tool. The simulation results show that the presented controller gives better performances (i.e., fast transient response, position tracking, and low swing angle) than the state feedback controller when there exist system parameter variations as well as input disturbances.

Power efficient error correction coding for on‐chip interconnection links

A configurable self-calibrated power efficient five-bit error correction code is proposed to correct both single bit random and burst errors up to five bits; providing 100% error correction probability with crosstalk avoidance. It can also correct higher-order error up to 9 bits with an error correction probability tolerance of 73% for on-chip interconnection links. Single error correction and double error detection with extended Hamming code (22,16) is utilised along with standard triplication error correction methods in the proposed code. Self-calibration algorithm and data stream rerouting block are integrated into the error correction code to achieve power efficiency. Reliability, link power consumption, and link swing voltage are estimated using an analytical model used in a network-on-chip. Area, power, and delay of the codec are obtained using Synopsys tools utilising UMC 90 nm technology. The proposed method provides 32–73% power saving and 22.3–60.6% delay reduction with negligible area overhead compared with the state-of-the-art works. Estimated results prove that it provides a 40.5–50% reduction in link swing voltage and link power consumption compared with the state-of-the-art works. The proposed code is more appropriate for on-chip interconnect links where it provides high reliability and low swing voltage with high error correction capability compared with existing codes.