Low Roundoff Noise Research Articles

Low Roundoff Noise of Two Sparse Second-Order Balanced Realization-Based Structures

Low Roundoff Noise of Two Sparse Second-Order Balanced Realization-Based Structures

Robust Digital Filter Structures: A Direct Approach

One of the many contributions of Prof. Fettweis was the invention of wave digital filters. These filters are obtained from classical RLC filters, in particular doubly terminated lossless two-ports, by using some transformations. Namely, the voltages and currents in the circuit elements are transformed into wave-variables and then a bilinear transformation is performed. If the wave transformation is performed appropriately it results in a realizable digital filter structure which furthermore enjoys a number of robustness properties such as low passband sensitivity, low roundoff noise, and freedom from limit cycle oscillations. Prof. Fettweis and his colleagues also showed that these properties are due to the inheritence of passivity properties from the continuous-time domain into the digital filter domain. Subsequent to this landmark work, a number of researchers worked on the problem of obtaining robust digital filter structures without starting from continuoustime circuits. One of these is the structurally bounded or structurally passive class of digital filters. These structures are based on inducing structural passivity directly into the implementation and are therefore simpler, both conceptually and from a practical viewpoint. They are also more general and lead to new structures which have no natural connection to electrical circuits. This paper gives an overview of some of these developments.

Low-Complexity Constant Multiplication Based on Trigonometric Identities with Applications to FFTs

In this work we consider optimized twiddle factor multipliers based on shift-and-add-multiplication. We propose a low-complexity structure for twiddle factors with a resolution of 32 points. Furthermore, we propose a slightly modified version of a previously reported multiplier for a resolution of 16 points with lower round-off noise. For completeness we also include results on optimal coefficients for eight-points resolution. We perform finite word length analysis for both coefficients and round-off errors and derive optimized coefficients with minimum complexity for varying requirements.

Low-noise zero-input, overflow, and constant-input limit cycle-free implementation of state space digital filters

This paper focuses on the selection of a suitable building block to implement cascade or parallel designs of narrowband high-order state-space digital filters that are guaranteed against any limit cycle. Two building blocks for which the absence of any limit cycle is guaranteed are gathered from the literature, and their relative output-roundoff-noise variances and computational complexities are checked. The result is the choice of a limit cycle-free building block fitting very well the requirements of low roundoff noise and low computational complexity. Although yet available in the literature, to the extent of the authors' knowledge the use such a building block has not been explored. Then, it is now revisited, and the result is the proposition of a new synthesis strategy that accomplishes minimum relative roundoff noise variance in its output, which is the main contribution of the paper.

A narrowband IIR digital filter with low sensitivity and roundoff noise

An efficient infinite-impulse response (IIR) structure is produced via spectral transformation of an appropriate finite-impulse response (FIR) prototype design. The filter specifications are prewarped to a halfband design by an allpass relationship to produce the efficient FIR prototype. The allpass coefficient is chosen to be exactly realizable with a small number of multiplier bits. Hence, the only coefficient quantization required is for the original FIR coefficients, which are relatively insensitive. The roundoff noise for fixed-point implementations is also quite low compared with conventional IIR designs. Scaling for overflow can be avoided completely, or, to save multipliers, a simple scale factor can be employed.

Design of very low-sensitivity and low-noise recursive filters using a cascade of low order lattice wave digital filters

Among the best structures for implementing recursive digital filters are lattice wave digital (LWD) filters (parallel connections of two all-pass filters). They are characterized by many attractive properties, such as a reasonably low coefficient sensitivity, a low roundoff noise level, and the absence of parasitic oscillations. The main drawback is that if the stopband attenuation is very high, then many bits are required for the coefficient representations. In order to get around this problem, a structure consisting of a cascade of LWD filters is introduced in this paper. The main advantage of the proposed structure, compared with the direct LWD filter, is that the poles of the new structure are further away from the unit circle. Consequently, the number of bits required for both the data and coefficient representations are significantly reduced. The price paid for these reductions is a slight increase in the overall filter order. By properly selecting the number of LWD filters and their orders and optimizing them, their coefficients are implementable by using a few powers of two. Filters of this kind are very attractive in very large-scale integration (VLSI) implementations, where a general multiplier is very costly.

GA-based design of multiplierless 2-D state-space digital filters with low roundoff noise

A new design method for multiplierless two-dimensional (2-D) state-space digital filters (SSDFs) with very low roundoff noise is presented. To eliminate multipliers in the hardware implementation, multiplierless 2-D SSDFs are designed under the constraint that all coefficients are expressed as one or two powers-of-two terms. They are attractive for low-cost implementation and high-speed operation. In addition, they can also perform highly accurate 2 D digital filtering because of very low roundoff noise. A combinatorial optimisation method based on a genetic algorithm (GA) is given to determine the coefficients. A stability test routine is also embedded in the GA-based design procedure to ensure the stability of the resultant multiplierless SSDFs. The proposed method can design multiplierless 2-D SSDFs not only with small approximation error but also with almost minimum roundoff noise. In addition they require fewer computational volume than 2-D SSDFs designed in a continuous coefficient space. For 16-bit words, the designed multiplierless 2-D SSDFs can be implemented with 24%, of the computational volume of 2-D SSDFs with real multipliers. The effectiveness of the proposed methods is demonstrated by two design examples.

Design and implementation of approximately linear phase two-dimensional IIR filters

A new method for designing separable denominator two-dimensional (2-D) infinite-response response (IIR) digital filters with approximately linear phase in the passband is proposed. This method is based on the model reduction of a linear phase finite-impulse response (FIR) filter using 2-D impulse response Gramians. The implementation of these filters using fixed-point arithmetic is also considered and an algorithm for obtaining a low roundoff noise structure with high computational efficiency is presented. Furthermore, a lower bound for the number of bits required for a 2-D IIR filter implementation with free of overflow oscillations is given. The resulting 2-D IIR digital filter has four advantages: (1) approximately linear phase in the passband; (2) low global roundoff noise; (3) high computational efficiency; and (4) no overflow oscillations under various overflow nonlinearities.

New Realization and Implementation of Fixed-Point IIR Digital Filters

A new low-roundoff noise realization for narrow-band IIR digital filters with residue feedback and a block triangular system matrix is presented. The block triangular form of the system matrix allows a reduction in the number of arithmetic operations required for the implementation and leads also to a realization which is suitable for high speed implementation. Numerical comparison between the proposed structure and three other low-noise structures shows that the proposed structure provides excellent performance in terms of output roundoff noise and coefficient sensitivity. The output roundoff noise is slightly higher than that of the optimal residue feedback realization proposed by Williamson9 but lower than the optimal realization without residue feedback proposed by Mullis, Roberts and Hwang.6,7 Further an efficient (in terms of speed) VLSI processor array implementation of the proposed IIR structure is also presented. The proposed implementation has been obtained by taking advantage of both the parallel feature of the residue feedback and the block triangular structure of the system matrix of the proposed realization. A hardware comparison between the proposed implementation and another implementation which is based on direct form shows that the proposed implementation provides a higher sampling rate for any narrow-band filter.

Minimization of fixed-point roundoff noise in extended state-space digital filters

A technique for determining a minimum roundoff noise extended state space (e-state) realization of fixed-point recursive digital filters is developed. Previous efforts have developed such minimum roundoff noise e-state structures for the second-order e-state equation only. This new algorithm determines a minimum roundoff e-state structure for the general order e-state equation. The technique obtains a linear transformation which, when applied to the original structure, produces a minimum noise e-state structure. A combination of a conjugate gradient algorithm and a variable metric algorithm is employed to determine the transformation coefficients. The e-state roundoff noise characteristics are illustrated by numerical examples. It is found that the minimum-noise e-state structure can have lower roundoff noise than the conventional minimum-noise structure, since fewer state variables are actually computed. In an e-state structure an Nth-order filter where N=LM can be implemented by M difference equations of order L resulting in a computational complexity of O[L(M+1)/sup 2/]. One advantage of e-state structures, compared to other realizations, is the use of fewer but longer inner products which pipelined digital signal processors are designed to handle efficiently.

Design and VLSI architecture and implementation of wave digital filters using short signed digit coefficients

The good dynamic range, low round-off noise characteristics and low coefficient sensitivity of wave digital filters make them suitable for realisations with short coefficient word-lengths. The authors discuss the design and implementation of a wave digital architecture using short signed digit coefficient ranges. The fundamental processing block employed in the implementation is the two port adaptor. Restricting the coefficients to this particular form reduces the number of levels of addition required in its implementation. Both the algorithmic and architectural aspects of this are considered. The resultant hardware increases the upper operating frequency, or sample rate, of the realisation, but at the expense of restrictions in the range of filter specifications that can be met. Hardware for a low latency, high clock rate adaptor is developed and cast into a form suited to VLSI implementation. A demonstrator for the concept has been designed and successfully fabricated in 1 /spl mu/m standard-cell CMOS technology. It is a programmable, cascadable device that may be applied to all standard filter types. The chip has a die area of 12.7 mm/sup 2/ and has been successfully tested to a clock rate of 30 MHz, which is twice the maximum filter sample rate.

Synthesis of fixed point limit‐cycle‐free digital filters with low roundoff noise

Synthesis of fixed point limit‐cycle‐free digital filters with low roundoff noise

New low roundoff noise realizations of second-order digital filter sections

New structures for second-order filter sections are proposed that yield lower output roundoff noise than many well known structures and are free of zero-input limit cycle oscillations. These new low-roundoff structures are based on these suggested by Bomar (1989) and are obtained by putting the constraint that some of the state-space coefficients be sum-of-two power-of-two terms. Numerical results are included to illustrate the performance of the proposed structures for narrow-band filters and to compare them with other structures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Scaled normalized lattice digital filter structures

The minimum-noise lattice digital filter with a systolizable structure, good scaling property and low output roundoff noise was recently proposed. In this paper, we show that the same structure can be designed by applying a new scaling method to the well known normalized lattice digital filter. Therefore, this structure can be referred to as the scaled normalized lattice digital filter. Different types of scaled normalized lattice digital filter structures are also derived. >

Lower finite word-length effect on state space digital filter by δ operator realization

A state-space digital filter realized using the δ operator has been presented to obtain a better numerical performance than the conventional forward-shift operator realization. When implemented with fixed-point arithmetic, it is shown that the δ operator realization has lower round-off noise, lower coefficient error and lower output error variance than the forward-shift operator realization.

Low roundoff noise augmented realizations of IIR filters

The scaling factor in a direct form II infinite impulse response (IIR) digital filter depends on only the system poles, not its zeros. Adding pole-zero cancellation pairs changes the scaling factor and the associated roundoff noise without affecting the transfer function. It is shown that with l/sub 2/ scaling, the upper bound of the noise reduction for direct form II IIR digital filters using K pole-zero cancellation pairs is about 6K dB. The authors consider parallel form 3P to be the basic structure, in which each subfilter is augmented with one or two pole-zero cancellation pairs and realized in direct form II. They seek an iterative optimization process for each subfilter to find the optimal pole-zero cancellation pairs that minimize the roundoff noise. Experimental results indicate the global optimal solution for these augmented subfilters can be obtained by using simple criteria to determine the starting points of the iterative processes. Alternative structures, illustrative examples, and overflow limit cycles are examined. >

Elimination of limit cycles in direct form digital filters using error feedback

AbstractThe elimination of zero‐input limit cycles in direct form filter sections using either a rounding or a magnitude truncation fixed‐point quantizer is considered. the well‐known criterion of Chang is reformulated for second‐order filter sections in a more practical form using the bilinear transformation. This enables graphical interpretation and quantitative analysis of the possible error feedback solutions for different pole locations.The synthesis of limit‐cycle‐free error feedback for second‐order filter sections is addressed in detail and several solutions are proposed. the error feedback coefficients are constrained to power‐of‐two values or to symmetric values so that the implementation is efficient, e.g. with signal processors. Different limit‐cycle‐free solutions are discussed with design examples and their round‐off noise properties are compared.The absence of limit cycles is related to the round‐off noise properties of the filter section. the main conclusion of the paper is that when the EF coefficients are appropriately chosen, low round‐off noise and the absence of limit cycles can always be accomplished at the same time. A particularly close correlation between limit cycles and roundoff noise is demonstrated with a rounding quantizer: a limit‐cycle‐free implementation always guarantees low roundoff noise. For most complex conjugate pole locations the converse relation also holds, i.e. low round‐off noise implies the absence of limit cycles.

Implementation of real coefficient two-dimensional denominator-separable digital filters based on decomposition techniques

In the paper, the implementation of two-dimensional digital filters is dealt with for the processing of real sequences. The approach is based on decomposition techniques to obtain separable one-dimensional polynomials from a two-dimensional polynomial, and then one-dimensional techniques are used to express the one-dimensional transfer functions as a sum of two reduced-order transfer functions with complex coefficients. Thus, new realisation structures are obtained for the equivalent reduced-order complex-coefficient transfer functions for the processing of real sequences. The authors concentrate more on two-dimensional denominator-separable digital filters and also confine themselves to the parallel-form structures as the emphasis is now on low data throughput delay and high parallelism due to recent advances in VLSI technology. All these structures consist only of one-dimensional first-order minimum-norm sections. Thus, these structures possess low round-off noise and freedom from overflow limit cycles. A comparison of different structures is made based on data throughput delay, efficiency in multiprocessor environment and round-off noise properties.

Finite word length effects on moment of impulse response of digital filter

The effect of finite word length on the moment of the impulse response of a digital filter is investigated. It is shown that the quantisation error in the moment values is almost linear with a slope of 3 dB/bit and is well related to the output roundoff noise. An algorithm is also proposed to order the cascade sections of an FIR filter with low output roundoff noise

Low roundoff noise augmented IIR filters based on normal realization

As second-order normal subfilters can be expressed as first-order complex subfilters, the authors decompose IIR digital filters into a parallel combination of first-order complex subfilters, in which each subfilter is augmented with one complex pole-zero cancellation pair and realized in complex direct form II. Under the l/sub 2/ dynamic range constraint, explicit expressions for the optimal complex pole-zero cancellation pair and the minimum roundoff noise of complex augmented subfilters are derived. Compared to normal realization, the noise reduction of this optimal complex augmented realization approaches its upper bound of about 6 dB as the desired filter bandwidth decreases. In addition, several suboptimal realizations are investigated and shown to achieve a greater performance-to-cost ratio.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>