Low-priority Cells Research Articles

Improving the Quality of Service Guarantee in an Asynchronous Transfer Mode (ATM) Network

This study presents a technique for improving the quality of service (QoS ) guarantee in an ATM network. In the proposed model, it was assumed that high priority traffic have been allocated a switch resource to guarantee a given QoS and low priority cells are allowed to enter the buffer, to improve the exploitation of reserved resources. The proposed technique was backed up with an exact analytical model for evaluating the cell loss probability of high and low priority cells. The performance of the proposed model was evaluated using C++ programming language. The results of the simulation shows that the loss probability of both high and low cells reduces as the buffer capacity increase and that the performance of high priority cell is better than that of low priority cell.

A performance analysis of the ATM multiplexer with selective discarding of the cells during congestion

In this paper, we present a discrete-time queuing analysis of the ATM multiplexer fed by independent binary Markov sources with two priority classes of cells. Each source alternates between On, Off periods and each On period consists of a random number of sub-periods. Each sub-period generates geometrically distributed number of cells, first cell of a sub-period is assigned high-priority while remaining cells are assigned low-priority. During normal operation the system delivers both high- and low-priority traffic while during congestion delivers only high-priority cells to their destinations and discard low-priority cells. We determine the performance of the system before and after discarding of the low-priority cells. We determine probability generating function of the queue length in both cases under infinite buffer assumption. Then, the mean delay for infinite buffer and approximate cell loss probabilities for the finite buffer cases are presented as a function of the percentage of the high-priority traffic load.

Incorporating priority scheme in IPv6 over ATM networks

An effective approach to support multiple QoS classes in IPv6 running over ATM networks is implemented by mapping the priority field of IPv6 into the ATM format. Such a scheme might not be necessary for simple congestion control in a network of equal capacity links, however, it might be important for multicasting to destinations reachable through a very diverse capacity network. When network congestion occurs, the cell loss requirements for different services can be satisfied by selectively discarding low priority cells. As the multi-priority scheme used in IPv6 is a “differentiated service” mechanism to enhance the QoS by best effort, its performance is certainly affected by the background traffic when these multi-priority traffic are multiplexed at the ATM level. This paper focuses on the performance with multi-priority scheme under different traffic conditions to determine the loss characteristics. The expected results are how QoS is affected and how priority can be given for more important traffic in the case of congested network.

Traffic policing in ATM networks with multimedia traffic: the super leaky bucket

Traffic policing and bandwidth management strategies at the User Network Interface (UNI) of an ATM network are investigated by simulation. The network is assumed to transport real time (RT) traffic like voice and video as well as non-real time (non-RT) data traffic. The proposed policing function, called the super leaky bucket (S-LB), is based on the leaky bucket (LB), but handles the three types of traffic differently according to their quality of service (QoS) requirements. Separate queues are maintained for RT and non-RT traffic. They are normally served alternately, but if the number of RT cells exceeds a threshold, it gets non-pre-emptive priority. Further increase of the RT queue causes low priority cells to be discarded. Non-RT cells are buffered and the sources are throttled back during periods of congestion. The simulations clearly demonstrate the advantages of the proposed strategy in providing improved levels of service (delay, jitter and loss) for all types of traffic.

An MPEG2-to-ATM converter to optimize performance of VBR video broadcast over ATM networks

This paper presents a novel MPEG2-to-ATM converter for VBR video broadcast over ATM networks. It functions as an external post-coding source rate controller between any MPEG2 source and an ATM network. Dynamic break points are employed to shape and partition the video data into high priority ATM cells which conform to the prevailing usage parameter control contract with the network, and nonconforming low priority cells which minimize the effects of cell loss due to network congestion on the subjective quality of the received video. Both high and low priority cells are transmitted over a common ATM virtual connection. Performance evaluations of actual VBR MPEG2 streams transmitted over a simulated converter and ATM network are presented to demonstrate the effectiveness of the proposed method.

GCRA-based architecture of multi-connection shaper and enforcer in multi-service ATM networks

Broadband networks are required to support multimedia applications that will have stringent requirements in terms of the quality of service. For instance, a video coding scheme has the ability to distinguish a given cell in the same connection as being a high- or low-priority cell by approprite packetization. Thus, the design of a multi-connection shaper and enforcer architecture which deals with different traffic parameters and cell priorities is important. In this paper, we propose algorithms and the architecture of a GCRA-based multiple-connection prioritized traffic shaper and enforcer. Simulation results reveal that the GCRA scheme is more suitable for shaping and UPC functions than conventional leaky-bucket schemes.

Loss periods in ATM output multiplexer

The authors present a new approach to evaluating the loss periods in the output multiplexer of ATM switch. First, they present a model for the output multiplexer using a discrete time finite capacity queueing system model with a threshold in the queue and priority in the bursty incoming cells. In modelling the loss period, they divide the queue space into a nonloss region, a half-loss region and a full-loss region, and define their corresponding time periods as the nonloss period, half-loss period and full-loss period, respectively. Next, they derive a general formula for the mean sojourn time for which a queue stays in a region. They derive formulae for the loss period, cell loss rate due to buffer overflow, discard rate for low priority cell and cell waiting time. Finally, they present the results of numerical experiments.

New implementation of multi-priority pushout for shared memory ATM switches

In a shared memory ATM switch with output queueing, the output queues share space flexibly in a common cell buffer. Selective Pushout is a technique for efficiently sharing this cell buffer memory among these multiple queues in an environment where cells also belong to various space priority classes. With Selective Pushout, whenever the buffer is full, arriving cells make space for themselves by pushing out low priority cells from the longest queue. In earlier work, we explored the performance of Selective Pushout. In this paper we consider its implementation. First we describe a queue controller implementation for a system without pushout. Then we outline a straightforward implementation of a queue controller with Selective Pushout. Next we propose a novel implementation that requires less control memory for the queue controller's data structures. Finally, we compare these implementations in terms of control memory requirements, processing speed, and design complexity. The control memory savings of the new implementation are significant for switches with large shared cell buffers. Moreover, for a system with only two space priority classes, the new implementation has a particularly simple design that should run nearly as fast as the straightforward implementation.

UPC/NPC algorithm for guaranteed QoS in ATM networks

In Broadband Integrated Services Digital Networks (B-ISDN) based on the Asynchrous Transfer Mode (ATM) technology, the required Quality of Service (QoS) must be guaranteed for connection. Cell loss ratio, which is one of the QoS parameters specified by the user in an ATM traffic contract of connection, may depend on the traffic enforcement mechanism known as the Usage Parameter Control/Network Parameter Control (UPC/NPC) or traffic policing. If two UPC/NPC algorithms are not equivalent with respect to cell discarding/tagging for a given traffic configuration, a common understanding about legality between the user and the network operator does not exist. To cope with this legality problem, the concept of cell conformance has been developed by the International Telecommunication Union-Telecommunication Standardization Sector (ITU-T). However, the Cell Loss Priority (CLP) bit, which ITU-T introduced in the ATM cell header to discriminate between a high priority cell (CLP = 0) and a low priority cell (CLP = 1), may cause the measurement phasing problem in cell conformance testing in ATM networks. This makes it difficult for a network provider to define and commit cell loss ratio as a QoS parameter. In this paper, we investigate measurement phasing problems and difficulties in commitment of the cell loss ratio in ATM networks. We propose a QoS guaranteed UPC/NPC algorithm to commit the cell loss ratio, and show an example of applications of the proposed UPC/NPC algorithm.

Analysis of controlled multiplexing systems via numerical stochastic control methods

The paper demonstrates the usefulness of numerical methods of stochastic control theory for the design, analysis and control of multiplexing type systems and networks, as well as ATM type systems. The sources are of the Markov-modulated type, although the final results hold for other types (e.g. low-order AR schemes). Control problems arise when we wish to control cell loss due to buffer overflows by regulating the sources. The basic control mechanism is the deletion of selected low-priority cells, according to an appropriate state dependent rule. But the same results hold for many other schemes (e.g. purchasing incremental bandwidth). By exploiting the large size of the system (large number of users), the systems can be efficiently approximated by diffusion type processes, whether there is a control term or not, and for many types of control mechanisms. The basic controls are of the "low-priority cell deletion" type, and various extensions. They might be state dependent, and we can obtain optimal controls for cost functions that weigh buffer overflow, controller cell deletion loss as well as queue length. The limit equations are an effective aggregation of the original system. It is shown that there are substantial savings in losses with the use of optimal control techniques. The numerical methods can be used to balance the losses at the control with those due to buffer overflow, to minimize losses at the controller subject to constraints on buffer overflow, and to explore various approximations, systems aggregations, the interaction of multiple source classes of different priorities.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modelling buffer admission mechanisms using stochastic automata networks

The stochastic automata networks formalism is an attractive technique to model complex systems with interacting components. Each component of the system is modelled by a single automaton; interactions between components are modelled by labels on the arcs which may represent synchronization and state-dependent transitions. Every automaton is associated with some matrices which allow to build the transition matrix of the underlying Markov chain, using tensor algebra. To illustrate this methodology, we introduce two buffer policies which could be used inAtm switching node. Every policy manages two priority levels which have distinct cell loss requirements. The first buffer policy is based on the push-out mechanism : a high priority cell replaces a low priority cell when the buffer is full. The second policy causes the discarding of all the low priority cells when the user transmits a request to send a burst of cells. In both studies, we compute the loss probabilities of each type of cells under various assumptions.

Priority shaping of source traffic in ATM B-ISDN

A source traffic shaper based on prediction of the behaviour of the ATM B-ISDN access policer is discussed. Using this approach, it is possible, within a policed virtual circuit, to reduce both loss and delay of the high-priority cells at the expense of delay of the low-priority cells. The priority-based traffic shaping is beneficial for sources generating cell streams with differing service requirements, e.g. multimedia sources.

Dimensioning of an ATM switch with shared buffer and threshold priority

A number of recent studies have addressed the use of priority mechanisms in Asynchronous Transfer Mode (ATM) switches. This investigation concerns the performance evaluation and dimensioning of a shared-buffer switching element with a threshold priority mechanism (partial buffer sharing). It assumes that incoming ATM ceils are distinguished by a space priority assignment, i.e., loss of a high priority cell should be less likely than loss of a low priority cell. The evaluation method is analytic, based on an approximate discrete-time, finite-state Markov model of a switch and its incoming traffic. The development focuses on the formulation of steady-state loss probabilities for each priority class. Evaluation of delay measures for each class is also supported by the model; results concerning the latter are illustrated without development. The analysis of loss probabilities is then used to dimension the buffer capacity and threshold level such that required maximum cell loss probabilities are just satisfied for each cell type. Moreover, when so dimensioned with respect to relatively stringent loss requirements, i.e., probabilities of 10 10 and 10 s for high and low priority cells, respectively, we find that both loss performance and resource utilization are appreciably improved over a comparable switch without such a mechanism.

A Queueing Model of a Bufferless Synchronous Clos ATM Switch with Head-of-Line Priority and Push-Out

We consider a synchronized bufferless Clos ATM switch with input cell processor queues. The arrival process to each input port of the switch is assumed to be bursty and it is modelled by an Interrupted Bernoulli Process. Two classes of cells are considered. Service in an input cell processor queue is head-of-line without preemption. In addition, push-out is used. That is, a high priority cell arriving to a full queue takes the space occupied by the low priority cell that arrived last, as long as the cell is not in service. Each cell processor queue is modeled as a priority IBP/Geo/1/ K + 1 queue with push-out. We first present an exact analysis of this priority queue. The results obtained are then used in an approximation algorithm for the analysis of the ATM switch. Validation tests using simulation data shows that the approximation algorithm has a good accuracy.

A VLSI sequencer chip for ATM traffic shaper and queue manager

The authors propose to control user traffic at two places in an asynchronous transfer model (ATM) network: at the user-network interface (UNI) by a traffic enforcer, and at the network-node interface (NNI) by a queue manager. The traffic enforcer adopted in this work contains a buffer to delay and reshape the violating cells that do not comply with some agreed-upon traffic parameters, and thus is also called a traffic shaper. The queue manager manages the queued cells in network nodes in such a way that higher priority cells are always served first, low-priority cells are discarded when the queue is full, and any interference between same-priority cells is prevented. Architectures for the traffic shaper and the queue manager are proposed. A key component, called the sequencer chip, has been implemented and tested to realize both architectures. The sequencer chip uses 1.2- mu m CMOS technology. It contains about 150 K transistors, has a die size of 7.5 mm*8.3 mm, and is packages in a 223-pin ceramic pin-grid-array (PGA) carrier.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>