Low-power Transceiver Research Articles

A Review of Agricultural IoT: Challenges, Applications & Future Research Direction

The field of wireless communication has had significant boom in wireless communication, mostly driven by increasing demand for connectivity and technological advancements in low power transceiver development. An Agriculture IoT (AIoT) refers to the technology to enhance agricultural sustainability, productivity, and efficiency. The agricultural IoT uses artificial intelligence to build a network of interconnected systems by fusing digital sensors, IoT devices, advanced analytics, and cloud computing. Agricultural products will be in high demand by 2030 because of the 40% raise in global population. IoT technology is currently utilized in various industries, including agricultural for automation processes. Therefore time is saved, total productivity is increased and decisions are made more effectively and resulting in higher crop yields. AIoT is also being utilized more to keep updated on the sustainability of agricultural supply chains, environment and water usage. Several IoT applications and problems have been covered in this paper. There is also an outline of potential future agricultural research directions.

Design and Simulation of VCO for RF Transceivers with Low Power, Low Phase Noise and Wider Tuning Range using Silterra 130nm CMOS Technology

The performance of low-power transceivers is required to meet stringent specifications for an advanced wireless radio frequency (RF) application. The design topology in this paper is simulated to meet the specifications and operation of VCO for low power, low phase noise and wide tuning range in complementary metal oxide semiconductor (CMOS) 130nm technology for RF transceivers. The relationship between the phase noise, power consumption and frequency turning range is fully analyzed to further improve the performance of the voltage-controlled oscillator (VCO). The architecture of the VCO employs two sets of symmetrical cross-couple split NMOS and PMOS with biased current sources operating in the triode region, and a resonator tank that achieves the desired low phase noise performance of about -110 dB/Hz at a tuning range of 4.1 to 4.5 GHz with a supply of 0.9 V. The control of the DC bias point reduces the conduction angle, which improves the current efficiency, power consumption and phase noise. The topology generates sufficient –gm for the oscillator incorporation to mitigate the start-up issue of the VCO. At the center frequency of 4.38 GHz, the VCO serves as a promising solution for improving low power and low phase for wireless communication systems and RF transceiver applications. The design consumes a very low power of 0.138 mW, achieves a phase noise of -110.53 dBc/Hz at 1 MHz offset, and a figure of merit (FoM) of -191.90 dBc/Hz.

CC2530-Based Wireless Data Long-Distance Communication Simulation Design and Application

With the rapid development of IoT, low-power wireless networks are becoming more and more important in engineering applications. For different IoT applications, a variety of corresponding low-power wireless technologies are studied and used. Among them, ZigBee technology is widely used for wireless data long-distance communication networks that require low-power consumption, low communication rate and large capacity self-organizing networks. However, the standard ZigBee module is limited by the large noise factor of the receiver and the small radiation power of the transmitter in the module, which cannot meet the requirements of long-distance communication. In this paper, we combine RF and communication technologies to design a long-range, low-power transceiver based on ZigBee technology for wireless data long-range communication simulation design and application. Experimental results show that the model in the urban area of 500[Formula: see text]m range, the system’s packet loss rate is kept at a low 0.03 or so, and the average Rssi is kept above and below [Formula: see text][Formula: see text]dBm, which can meet the general communication requirements and achieve the expected communication effect. Under the same packet rate, the model combines the improved AODVjr and Cluster_Tree algorithms, and the packet delivery rate can reach 98.5%, which greatly extends the wireless data long-distance communication life.

Analytical Approach to Improve the Performance of a Fully Integrated Class-F Power Amplifier with 0.13 µm BiCMOS Technology Using Drain–Bulk Capacitor Modulation

This article reports a novel technique based on drain–bulk capacitor modulation to improve the performance design of a class-F power amplifier (PA) used in low-power transceivers based on the I-Q amplitude modulation technique considering linearity–efficiency–miniaturization trade-offs. This idea is carried out by implementing a tuned capacitor in parallel with a cascode transistor on the output of the power stage to enhance the shape of the voltage–current amplitudes of the class-F PA by creating a new harmonic current component. Simulated results were obtained for the power back-off region of the proposed configuration, with an output power, power gain and power-added efficiency of 8 dBm (+ 5 dBm)B, 19 dB (+ 5 dB)B and 45% (+ 5% to 10%)B, respectively. In addition, post-layout simulations revealed a similar level of output power, a power gain of a 20 dB and a 28% power-added efficiency for an added capacitance equal to 1.3 pF. Class-F PA is implemented on a 732×605 μm2 chip’s surface. (B: indicates the improved values in the power back-off region).

A 40% PAE and 34dBm Peak OIP3 CMOS Power Amplifier with Integrated Zero Power Consumption Phase Linearizer

In this paper, an Integrated Phase Linearizer (IPL) technique is designed to improve the linearity performance of a CMOS power amplifier (PA). The IPL is integrated at the gate of the PA so that the effect of the parasitic gate-to-source ([Formula: see text]) capacitance of the main transistor is compensated by the linearizer. Thus, it improves the 3rd-order intermodulation point (OIP3) without trading-off the power added efficiency (PAE). The proposed solution is designed and fabricated in an 180[Formula: see text]nm CMOS technology process consuming the chip area of 2.25[Formula: see text]mm2. At the operating frequency of 2.45[Formula: see text]GHz, it exhibits a gain of 11.14[Formula: see text]dB with unconditional stability characteristics from 1[Formula: see text]GHz to 10[Formula: see text]GHz. Biased quiescent current of 19.35[Formula: see text]mA, the IPL-PA delivers a maximum output power of 15.20[Formula: see text]dBm with 40.86% peak PAE, 34.91[Formula: see text]dBm of peak OIP3 and maximum power consumption of 63.65[Formula: see text]mW at 2.45[Formula: see text]GHz with supply voltage headroom of 1.8[Formula: see text]V. The proposed linearization scheme proved to be an excellent solution for low-power transceivers integration.

A low-power WNoC transceiver with a novel energy consumption management scheme for dependable IoT systems

Wireless network-on-chip architectures (WNoCs), by combining wired and wireless modules and links, provide fast and efficient communication infrastructures for complex on-chip systems such as various IoT and intelligent systems. The most challenging step of designing high-performance and energy-efficient WNoCs is the structure of transceivers. In fact, transceivers and wired routers are the most power-hungry elements in WNoCs; therefore, any cut-down of power consumption in transceivers and routers significantly reduce the power consumption of WNoCs. In this paper, a low-power transceiver for WNoC is designed and then, a high-performance and configurable energy consumption management scheme for the transceiver is proposed. In the designed transceiver, various strategies are employed at both circuit-level and also at architectural-level for reducing static and dynamic power consumption. The proposed energy management scheme controls the activity and tunes the voltage level of the power supply of each module, in a distributed and dynamic manner. The evaluation results demonstrate that a WNoC utilizing the proposed scheme provides lower energy consumption, less latency, and higher reliability and higher network throughput compared to both of relevant single-chip and multi-chip WNoC architectures, at the cost of negligible impact on silicon area.

Orthogonal phase mixing for improved linearity phase interpolator

As the demand for high-speed low-power transceivers grows, it is critical to have precise clock timing circuits such as phase interpolators (PI) that allow maximizing link margin. A linearization technique which optimizes linearity without increasing power and area is presented. Implemented in a 7-nm complimentary metal oxide silicon (CMOS) technology, PI achieves less than 0.5 integral non-linearity (INL) while consuming only 184 μA from a 0.75-V supply at 4.3 GHz.

A LoRa-Cloud Based Water pH and Air Temperature Sensor Hub

Water pollution has become one of the important issues in Malaysia which occurs frequently especially in the rivers of Selangor. One of the indicators of pollution is the pH of the water. Thus, the main purpose of this study was to design a LoRa-Cloud-based water pollution sensor hub to monitor the real-time water quality. Sensor devices for pH (SEN0161-V2), and temperature and humidity (DHT11) were used to accurately detect water pH, and air temperature and humidity, respectively. REYAX RYLR896 Long Range Low Power (LoRa) transceiver module enabled the transmission of sensor data from the sensor node to the gateway node, while NodeMCU ESP8266 enabled transmission of sensor data to the Cloud. Ubidots IoT platform was used to monitor the real-time sensor data. A 3 W power supply was continuously supplied to the prototype and autonomy was guaranteed with the addition of monocrystalline solar cells. The performance of the prototype device was tested based on the monitoring function, and the overall pH level of Taman Metropolitan Batu Park Lake was slightly alkaline as the pH of the lake water ranged from 7.32 to 9.08 with data updating every 5 minutes on the Ubidots dashboards. The LoRa-Cloud-based water pollution sensor hub was successfully developed to monitor the real-time water quality through the Ubidots IoT platform.

Design of an Integrated Micro-Viscometer for Monitoring Engine Oil.

This paper proposes a novel integrated micro-viscometer for engine-oil monitoring. The final solution consists of a capacitive micromachined ultrasonic transducer (CMUT) and an application-specific integrated circuit (ASIC). The CMUT is used to generate and capture acoustic waves while immersed in engine oil. The low power transceiver ASIC is interfaced with the CMUT structure for actuation and reception. An integrated charge pump boosts the supply voltage from 3.3 to 22 V to generate the DC polarization voltage of the CMUT. The receiver has a power consumption of 72 µW with an input-referred noise current of 3.2 and a bandwidth of 7 MHz. The CMUT array occupies an area of 3.5 × 1 mm, whereas the ASIC has a chip area of 1 × 1 mm. The system was tested using engine oils of different types and ages at different temperatures. Measurement results show a significant frequency shift due to the dynamic viscosity change that occurs as oil ages. A shift of −1.9 kHz/cP was measured, which corresponds to a shift of 33 Hz/mile. This work paves the way for high accuracy-integrated solutions for oil condition monitoring and is expected to play a significant role in a more economic and environmentally friendly usage of oil.

Deep Conviction Systems for Biomedical Applications Using Intuiting Procedures With Cross Point Approach.

The production, testing, and processing of signals without any interpretation is a crucial task with time scale periods in today's biological applications. As a result, the proposed work attempts to use a deep learning model to handle difficulties that arise during the processing stage of biomedical information. Deep Conviction Systems (DCS) are employed at the integration step for this procedure, which uses classification processes with a large number of characteristics. In addition, a novel system model for analyzing the behavior of biomedical signals has been developed, complete with an output tracking mechanism that delivers transceiver results in a low-power implementation approach. Because low-power transceivers are integrated, the cost of implementation for designated output units will be decreased. To prove the effectiveness of DCS feasibility, convergence and robustness characteristics are observed by incorporating an interface system that is processed with a deep learning toolbox. They compared test results using DCS to prove that all experimental scenarios prove to be much more effective for about 79 percent for variations with time periods.

Relay based thermal aware and mobility support routing protocol for wireless body sensor networks

The evolvement of wireless technologies has enabled revolutionizing the health-care industry by monitor patient health condition requiring early diagnosis and interfering when a chronic situation is taking place. In this regard, miniaturized biosensors have been manufactured to cover various medical applications forming therefore a Wireless Body Sensor Network (WBSN). A WBSN is comprised of several small and low power devices capable of sensing vital signs such as heart rate, blood glucose, body temperature etc.. Although WBSN main purpose is to provide the most convenient wireless setting for the networking of human body sensors, there are still a great number of technical challenges to resolve such as: power source miniaturization, low power transceivers, biocompatibility, secure data transfer, minimum transmission delay and high quality of service. These challenges have to be taken into consideration when creating a new routing protocol for WBSNs. This paper proposes a new Relay based Thermal aware and Mobile Routing Protocol (RTM-RP) for Wireless Body Sensor Networks tackling the problem of high energy consumption and high temperature increase where the mobility is a crucial constraint to handle.

Indoor Positioning of Low-Cost Narrowband IoT Nodes: Evaluation of a TDoA Approach in a Retail Environment.

The localization of internet of things (IoT) nodes in indoor scenarios with strong multipath channel components is challenging. All methods using radio signals, such as received signal strength (RSS) or angle of arrival (AoA), are inherently prone to multipath fading. Especially for time of flight (ToF) measurements, the low available transmit bandwidth of the used transceiver hardware is problematic. In our previous work on this topic we showed that wideband signal generation on narrowband low-power transceiver chips is feasible without any changes to existing hardware. Together with a fixed wideband receiving anchor infrastructure, this facilitates time difference of arrival (TDoA) and AoA measurements and allows for localization of the fully asynchronously transmitting nodes. In this paper, we present a measurement campaign using a receiver infrastructure based on software-defined radio (SDR) platforms. This proves the actual usability of the proposed method within the limitations of the bandwidth available in the ISM band at . We use the results to analyze the effects of possible anchor placement schemes and scenario geometries. We further demonstrate how this node-to-infrastructure-based localization scheme can be supported by additional node-to-node RSS measurements using a simple clustering approach. In the considered scenario, an overall positioning root-mean-square error (RMSE) of is achieved.

Minimum Length Scheduling for Discrete-Rate Full-Duplex Wireless Powered Communication Networks

Wireless powered communication networks (WPCNs) will act as a major enabler of massive machine type communications (MTCs), which is a major service domain for 5G and beyond systems. The MTC networks will be deployed by using low-power transceivers with finite discrete configurations. This paper considers minimum length scheduling problem for full-duplex WPCNs, where users transmit information to a hybrid access point at a rate chosen from a finite set of discrete-rate levels. The optimization problem considers energy causality, data and maximum transmit power constraints, and is proven to be NP-hard. As a solution strategy, we define the minimum length scheduling (MLS) slot, which is slot of minimum transmission completion time while starting transmission at anytime after the decision time. We solve the problem optimally for a given transmission order based on the optimality analysis of MLS slot. For the general problem, we categorize the problem based on whether the MLS slots of users overlap over time. We propose optimal algorithm for non-overlapping scenario by allocating the MLS slots, and a polynomial-time heuristic algorithm for overlapping scenario by allocating the transmission slot to the user with earliest MLS slot. Through simulations, we demonstrate significant gains of scheduling and discrete rate allocation.

A Bimodal Low-Power Transceiver featuring a Ring Oscillator-based Transmitter and Magnetic Field-based Receiver for Insertable Smart Pills.

This paper presents a novel bimodal, low-power, mm-scale transceiver for insertable smart pills. The proposed PA-less, 915 MHz uplink transmitter (TX) incorporates an 1.21.2 mm2 on-chip, non-resonated antenna as part of a current-starved ring oscillator (RO) and directly transmits data by turning the RO on/off. This RO-based uplink TX is implemented in 180 nm CMOS along with a power management unit, which generates all internal reference voltages and supplies from a single battery. The uplink TX achieves a data rate of 33 Mb/s and consumes 210 μW, resulting in an energy efficiency of 6.4 pJ/bit. The orientation-insensitive magnetic field-based downlink receiver (RX) is implemented with an external 3-D magnetic sensor, achieves 0.02 kb/s of data rate limited by our measurement setup, and consumes 270 μW. Wireless measurements in saline over 150 cm and prototype of the 3.213.62.3 mm3 insertable pill are presented.

Minimum Length Scheduling for Multi-Cell Full Duplex Wireless Powered Communication Networks.

Wireless powered communication networks (WPCNs) will be a major enabler of massive machine type communications (MTCs), which is a major service domain for 5G and beyond systems. These MTC networks will be deployed by using low-power transceivers and a very limited set of transmission configurations. We investigate a novel minimum length scheduling problem for multi-cell full-duplex wireless powered communication networks to determine the optimal power control and scheduling for constant rate transmission model. The formulated optimization problem is combinatorial in nature and, thus, difficult to solve for the global optimum. As a solution strategy, first, we decompose the problem into the power control problem (PCP) and scheduling problem. For the PCP, we propose the optimal polynomial time algorithm based on the evaluation of Perron–Frobenius conditions. For the scheduling problem, we propose a heuristic algorithm that aims to maximize the number of concurrently transmitting users by maximizing the allowable interference on each user without violating the signal-to-noise-ratio (SNR) requirements. Through extensive simulations, we demonstrate a 50% reduction in the schedule length by using the proposed algorithm in comparison to unscheduled concurrent transmissions.

A Digitally Controlled Multichannel Spectrally Efficient Low-Power Transceiver for Ultra-Wideband Cognitive Radio Applications

A multichannel transceiver design with low hardware complexity, flexibility and efficient spectrum use intended for Impulse Radio (IR) Ultra-Wideband (UWB) apertures, is proposed in this paper. The transceiver supports 14 channels and is implemented in TSMC CMOS process. The transmitter adopts a symmetrical triangular narrow pulse generator, a multiband LC-VCO, a mixer and a Variable-Gain Amplifier. A digital control of transmitter output power and carrier frequency is achieved by a current-steering Digital-to-Analog Converter (CS-DAC). The receiver follows the noncoherent Energy Detection (ED) scheme including Low-Noise Amplifier (LNA) which takes the benefits of the body biasing technique to further reduce power consumption, squarer and comparator. The LNA achieves high gain of up to 30[Formula: see text]dB allowing to enhance the receiver sensitivity which is [Formula: see text]83.7[Formula: see text]dBm at 25[Formula: see text]Mbps. The transmitter provides output pulses with a width of 3[Formula: see text]ns, a pulse repetition rate of 20[Formula: see text]ns and a maximum Power Spectral Density (PSD) of [Formula: see text]42[Formula: see text]dBm/MHz. The power consumptions of transmitter and receiver are 35.6[Formula: see text]pJ/bit and 0.207[Formula: see text]nJ/bit at 25[Formula: see text]Mbps, respectively. Maximizing utilization of the scarce wireless spectrum, enhancing spectral flexibility and efficiency and reducing power consumption are the main contributions brought by this work, enabling this transceiver to be able to deal with the current debate on producing single multifunctional Cognitive Radio (CR) UWB systems.

A Time-based Transceiver Front-end Circuit with 1-tap IIR DFE and Relaxed Termination for Short-reach PCB Interconnect

A time-based low-power transceiver is proposed for short-reach PCB interconnect which connects two chips closely placed on a printed circuit board (PCB). This was achieved by reducing the I/O signaling power of transmitter (TX) with the increase of on-die termination (ODT) resistance. The short-reach PCB interconnect is approximated as a single-time-constant RC channel due to the large ODT resistance. The increase of inter-symbol interference (ISI) by the increased R-C time constant of channel was compensated by using a 1-tap infinite-impulse-response (IIR) decision-feedback equalizer (DFE) at receiver (RX). The RX circuit is composed of a cascaded connection of a voltage-to-time converter, an IIR DFE, a FIR DFE and a time comparator. The transceiver chip was implemented in 65 nm CMOS technology; in tests with a 1.6-mm micro-strip line channel the transceiver achieved maximum data-rate of 12 Gb/s at 0.8 V supply and minimum energy efficiency of 0.37 pJ/b at 8 Gb/s and 0.75 V supply.

Design Considerations for a Sub-mW Receiver Front-End for Internet-of-Things

Internet-of-Things (IoT) and Wireless sensor networks (WSNs) require very low power transceivers. This paper presents techniques for minimizing power consumption of receiver (RX) frontends for short range wireless links. Two key approaches, i.e., current reuse and supply voltage reduction are compared. Different RX architectures such as direct-conversion, low-IF, sliding IF as well as phase-tracking RX, are compared, emphasizing their potential and limitations when targeting sub-mW RX power dissipation. Low-power design techniques for LNA, frequency generation blocks and baseband amplifiers are presented. As a case study, an efficient low-IF RX front-end for IoT is described in detail. In 28 nm CMOS, such a receiver occupies an active area of 0.1 mm2 and consumes only $350~{\mu }\text{W}$ from a 0.9 V supply while showing a minimum in band NF of 6.2 dB. The achieved performance is very competitive with state-of-the-art ultra-low-power receivers, while consuming the lowest power.

A Novel AEB-AODV Based AADITHYA Cross Layer Design Hibernation Algorithm for Energy Optimization in WSN

Wireless Sensor Networks (WSN) has gained significant importance in current scenario because of its ability to monitor as well as understand the physical environment in terms of different parameters like temperature, humidity, pressure etc. There is a plethora of applications in WSN is finding importance ranking from military tracking, surveillance to environmental exploration and wildlife monitoring. The main challenge in WSN is energy efficiency especially when the capacity of battery and availability of energy source is a constraint. To address some of key WSN challenges, a novel routing protocol, a hibernation algorithm (cross layer design) along with the low power hardware design for achieving energy efficiency are proposed here.Because of the fact that WSN has requirement to adapt itself according to the needs of the dynamically changing environment, the quantity of sensor nodes which are part of routing tree cannot be the same and need to adapt itself so that it can precisely observe and forecast the physical surroundings. Initially the routing protocols being used popularly for WSN network layer i.e. AODV, AOMDV, and DSR are compared. The next stage is a proposal for adaptive model for AODV routing protocol for sensor node selection based on residual energy (AEB-AODV) towards improving the efficiency of energy and Quality of Service depending on the mentioned targets of performance. Here, the scheme utilizes fewer sensor nodes at a time along the route to the destination from the source of the event, and place remaining sensor nodes’ transceivers in the sleep mode but microcontroller, sensors and low power transceivers of the nodes are ON. The last module is a combined model capable of achieving improvements in efficiency of energy–adaptive routing model (AEB-AODV) and Hibernation of the sensor nodesi.e. AADITHYA algorithm, which reduces energy consumption, duty cycle to great extent and improved the latency, implemented with low power ARM CORTEX microcontroller and two sets of transceivers, one active power (AP) for data transmission and another very low power (LP) for sending wake up signals and control signals to the hibernating neighbors. Simulation results of AEB-AODV routing protocol and actual test readings of the developed hardware have shown that this method is effective in optimizing the energy usage in the nodes and hence improves the life expectancy of the WSN used for any general application.

A switching frequency modulated DC-to-DC converter with reduced spurious noise for a RF power amplifier in microwatts transmitters

Varying a supply voltage using a DC-to-DC converter can significantly improve the efficiency of RF power amplifiers (PAs) for low-power RF transceivers. However, intrinsic switching noise from a conventional DC-to-DC converter operating in fixed Pulse-Width Modulation (PWM) can affect the system performance since the spectral components in the switching noise are confined in the fundamental switching frequency and its harmonics. This harmonic noise will have detrimental effects on the performance of the microwatt’s transmitter due to its low output power. Especially for microwatts systems, the minimized size of the inductor will increase the spurious noise due to increased peak-to-peak inductor current. By relocating the spurious noise and reducing peak noise from a switching converter, this paper proposes the technique to prevent high noise spurs in a microwatt transmitter, combining both pseudo-random frequency stepping and monotonic frequency stepping. Both modulation circuits are implemented in CMOS 0.18 µm process and incorporated to achieve the proposed DC-to-DC converter system. The measurement results indicate that the proposed PWM ramp signal modulator with random frequency modulation in a DC-to-DC converter can reduce the peak of the spurious noise-power by 22 dB. Monotonic frequency modulation with various frequency steps reduces the peak of the spurious noise-power by 18 dB.