Low-power Successive Approximation ADC Research Articles

Design and Implementation of a Low Power Successive Approximation ADC

This paper designed a low-power successive approximation ADC based on BCD 0.35um standard CMOS technology. The overall static power consumption of the circuit and the use of passive components has been reduced by using switch dynamic comparator and the comparator of the state transition controlled by the clock signal as well as the DAC circuit uses charge redistribution structure. The sample and hold circuit is built into the ADC which further reduce the size of the chip area. The parameters of DNL, INL, SINR and SINAD were verified by MATLAB software. At the same time HSPICE tools were used to simulate the successive approximation ADC. Under the condition of VCC = 3.3V, T = 25 ℃, the overall power consumption of the circuit is 1.518mW, and the SNR of the circuit is 50.93dB.

A low-power 12-bit SAR ADC for remote pressure measurement

A 12-bit low power successive approximation ADC has been designed and fabricated in 0.35 µm, poly---poly capacitor AMS technology. The SAR ADC is targeted for bridge type pressure sensor in wireless sensor node applications. An improved cascaded inverter based comparator is used for its lower power consumption at reduced supply voltage of 1.3 V. A modified SAR digital circuit has been incorporated to accommodate a higher input range of 1.8 V for the ADC . For a given noise floor, the higher input range of ADC ensures enhanced SNR performance relaxing the constraint on sensor interface circuit preceding to the ADC. Also a novel switching scheme is used in the feedback of comparator to reduce the charge injection induced offset without sacrificing the useful bandwidth of ADC. The inverter based comparator consumes 2 µW of power while operating at a speed of 1.6 MHz. The comparator does not make use of any offset cancellation techniques. By suitably choosing the capacitor array of inherent DAC, the calibration techniques have been avoided for the ADC. The ADC achieves an effective number of bits of 10.01 while consuming 6.69 µW at a conversion speed of 100 KHz. The FOM of the whole ADC is found to be 64.8 fJ/conversion-step. The active area occupied by the ADC is 0.170625 mm2 (375 µm × 455 µm).

Low-Power Successive Approximation ADC with 0.5 V Supply for Medical Implantable Devices

Low-Power Successive Approximation ADC with 0.5 V Supply for Medical Implantable Devices

A low-power Successive Approximation ADC for biomedical applications

A new switching algorithm is proposed in Successive Approximation Analog-to-Digital Converters (SA-ADCs) to reduce the power consumption in both DAC and comparator. This technique is more efficient in applications where the input signal has low-varying characteristics. For slow-varying samples, only the least significant bits of the new analog sample are extracted leading to power saving in both the capacitor-based DAC and the comparator. For an Electrocardiogram (ECG) signal and with the proposed structure, the simulated power consumption of the DAC, the comparator and the entire ADC for an 8-bit 10-kS/s converter are 74%, 38% and 52% less than those of a conventional architecture, respectively.