Low Power Self Research Articles

Low Power Self disabling Comparator for Asynchronous ADC

A low power single channel ADC with high sampling rate is designed in this work. The low power is accomplished by utilizing a self-disabling continuous time comparator those outcomes in less delay cells. The proposed ADC executed and simulated in 180nm CMOS technology. The possibility of 1.8 V supply in this technology provides improvement in step size and the improved delay cells yields increased sampling rate. The decision of asynchronous ADC is because of the way that it eliminates complicated correction methods to acquire better execution, as in flash, pipelined and SAR ADC. Asynchronous digital slope ADC, accomplishes power lower than the synchronous ADC. It does not need the complex alignment and can accomplish low power utilization.. So to improve speed of sampling, improvisation of delay cell and shortening of delay time is done. In this paper an improvised design of the StrongARM comparator having faster performance, smaller area, and higher power efficiency is designed.

An Ultra Low Voltage Low Power Self Biased Latched Comparator with Wide Input Common Mode Range for Biomedical Applications

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0 V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141 nW to 188 nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 μV with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3–2.4 mV (with input common mode range from 0 V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1 MHz in most process corners and temperature range of 0–100°C which is suitable for most of the biomedical sensing applications.

Optimizing Energy-Efficient Reconstruction of Mobile Point Source in Sensor Networks

To obtain accurate information about the interested physical phenomenon, many nodes should be deployed and collaborated to extract data about the event source. This article proposes a Low Power Self Scheduling protocol for mobile point source reconstruction. The motivation is clear, to provide high level QoS (reconstruction distortion) and reduce energy consumption. This article first obtains a distance to the event source, in which all sensing reports are collected to minimize the reconstruction distortion. This distance is relatively constant under different network densities. Then the mobility of the event source is considered. Sensor nodes are self-scheduled to join or leave the representative nodes group, which guarantee that those appropriate nodes will always be the group member. Simulation validates the effectiveness of the presented scheme.