Low-power IoT Applications Research Articles

Piezoelectric Sensors as Energy Harvesters for Ultra Low-Power IoT Applications.

The aim of this paper is to discuss the usability of vibrations as energy sources, for the implementation of energy self-sufficient wireless sensing platforms within the Industrial Internet of Things (IIoT) framework. In this context, this paper proposes to equip vibrating assets like machinery with piezoelectric sensors, used to set up energy self-sufficient sensing platforms for hard-to-reach positions. Preliminary measurements as well as extended laboratory tests are proposed to understand the behavior of commercial piezoelectric sensors when employed as energy harvesters. First, a general architecture for a vibration-powered LoRaWAN-based sensor node is proposed. Final tests are then performed to identify an ideal trade-off between sensor sampling rates and energy availability. The target is to ensure continuous operation of the device while guaranteeing a charging trend of the storage component connected to the system. In this context, an Ultra-Low-Power Energy-Harvesting Integrated Circuit plays a crucial role by ensuring the correct regulation of the output with very high efficiency.

Automatic Modulation Classification for low-power IoT applications

Automatic Modulation Classification for low-power IoT applications

BLE Transmitter with Multiple Feedback Filter for Low-Power IoT Applications

BLE Transmitter with Multiple Feedback Filter for Low-Power IoT Applications

LoRaWAN Physical Layer-Based Attacks and Countermeasures, A Review.

As LoRaWAN is one of the most popular long-range wireless protocols among low-power IoT applications, more and more focus is shifting towards security. In particular, physical layer topics become relevant to improve the security of LoRaWAN nodes, which are often limited in terms of computational power and communication resources. To this end, e.g., detection methods for wireless attacks improve the integrity and robustness of LoRaWAN access. Further, wireless physical layer techniques have potential to enhance key refreshment and device authentication. In this work, we aim to provide a comprehensive review of various vulnerabilities, countermeasures and security enhancing features concerning the LoRaWAN physical layer. Afterwards, we discuss the impact of the reviewed topics on LoRaWAN security and, subsequently, we identify research gaps as well as promising future research directions.

Enhancement of the TSCH-Sim Simulator to Support Manual Scheduling and Routing

Time Slotted Channel Hopping (TSCH) has become prominent for low-power industrial IoT applications where primary requirements are high throughput and low delay. This paper presents enhancements to the TSCH-Sim simulator that support the manual specification of a TSCH schedule and static routing for a wireless sensor network. This feature is extremely valuable for researchers that are investigating optimized scheduling for TSCH and our is not currently supported in any of the open-source TSCH simulators. TSCH-Sim is one of a few open and free simulators available that researchers can leverage to design and test any novel TSCH scheduling and routing algorithms. The additional modules have been tested and validated on the simple network where the TSCH schedule can be easily specified as well as on a more complex network with an optimized TSCH schedule. The results show that the manual TSCH schedules deliver 100% of the generated packets under ideal conditions where there is no loss of data caused by path signal degradation. These results validate that these new modules are operating properly.

Neuromorphic In-Memory RRAM NAND/NOR Circuit Performance Analysis in a CNN Training Framework on the Edge for Low Power IoT

Training a CNN involves computationally intense optimization algorithms to fit the network using a training dataset, to update the network weight for inferencing and then pattern classification. Hence, the application of in-memory computation would enable a highly power-efficient low latency on-the-edge CNN training technique by avoiding the memory wall created during the external memory read/write operation (for off chip instruction and data transfer). A memory write-verify, and re-program technique can control the RRAM variability. Still, memory verification and re-program is a complex process with additional resources needed for practical implementation of verification circuit. In this study, we have demonstrated a practical (First-in Max-Out) FIMO-based cache memory called Maximum Count Binary Comparator Layer (MCBC), using 1T3R, 1T5R, and 1T7R RRAM structures by using a probability-based accuracy improvement architecture, without the conventional verification process. We constructed 10 layered modified MobileNET with filter size ranging from 32 - 512 and trained with Traffic Sign Recognition Database (TSRD) using a three-tier abstraction simulation learning framework - (1) High level, 10 layered CNN implementation with Python+TensorFlow; (2) Verilog HDL based FP32MUL and FP32ADD (32-bits Floating Point adder and multiplier) circuits constructed with RRAM NAND gates using 1T2R structures; and (3) Digital Look-Up-Table (LUT) model for RRAM variability. An edge learning framework (for the forward pass) is demonstrated using digital RRAM-NAND/NOR universal gates integrated with the Maximum Count Binary Comparator Layer (MCBC) to partially circumvent the impact of RRAM variability and to quantify the RRAM variability on the CNN training prediction accuracy for 65nm CMOS OxRAM (TiN/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Hf/TiN) with varying device current compliance of 5, 10, and 50μA for low power IoT applications. The MCBC layer was simulated using a SPICE model, for which the estimated chip layout is 1150 × 1230 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per logical gate input, which resulted in an overall prediction accuracy improvement from 10% to 60% by repeating the logical operations of the NOR gate for {1, 3, 5, and 7} cycles respectively.

Computation-transferable authenticated key agreement protocol for smart healthcare

Smart healthcare plays an important role in contemporary society while its security and privacy issues remain inevitable challenges. Authenticated key agreement (AKA) mechanism, as the foundation of secure communication, has been recognized as an important measure for solving this problem. Most existing AKA protocols utilize cloud-based centralized architecture, data privacy and security can be exposed easily once the centralized authority is attacked. In addition, most past solutions require the online registration center to assist mutual authentication and consume considerable amounts of resources. To address these drawbacks, a computation-transferable authenticated key agreement protocol without an online registration center for smart healthcare is designed. Specifically, the proposed protocol can realize mutual authentication and key agreement without the need for an online registration center, as well as being able to satisfy security and privacy protection requirements. By transferring partial computation tasks to the server, the proposed scheme incurs lower computation and communication overhead on the user side. Moreover, the proposed scheme adopts certificateless public key cryptography, which can solve the problems of certificate management and key escrow. Performance analysis indicates that the proposal reduces 9.9% of the computation overhead on the resource-limited terminal, which is suitable for low-power IoT applications, including smart healthcare.

Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

Design of Self-Differential Down-Conversion I/Q Mixer for 2.4 GHz IoT Application

A 2.4 GHz self-differential down-conversion Gilbert cell mixer with current-reuse topology is presented in this paper. This design is targeted for low-power IoT applications. Here, by using a novel self-differential RF input stage with current-reuse topology, the single-ended RF signal can be transferred into differential signals without using a balun. With an applied local oscillator (LO) power of 10 dBm and RF signal of -30 dBm, this mixer demonstrates 9.886 dB of conversion gain, 10.4 dB of noise figure at 5 MHz and an IIP3 of 1.1767dBm in both I/Q branch. The design consumes 1.57 mA from a 1.8 V voltage supply.

Highly Integrable Paper-Based Harmonic Transponder for Low-Power and Long-Range IoT Applications

In this letter, the design and performance analysis of a harmonic planar transponder on paper, which conjugates compactness and scalability, are presented. The tag, targeted for a fundamental frequency of 1.2 GHz, is based on a frequency doubler with a single lumped component (a low-barrier Schottky diode) and a system of nested tapered annular slot antennas. Both antennas, orthogonally placed, feature a maximum gain around 3 dBi. The frequency doubler is optimized for power levels in the order of −13 dBm, where it achieves a conversion loss of 15.7 dB. A complete prototype has been tested in a wireless indoor experiment, demonstrating a coverage of at least 4 m, insensitive to tag-to-reader rotations (transmitter effective isotropic radiated power 16 dBm).