Low-power Implementation Research Articles

High Speed and Low Power Implementation of AES for Wireless Sensor Networks

In the recent years, data security has become the biggest concern due to the increasing number of connected devices. Hence, cryptography has become vital for enhancing data security. Cryptography is a technique which converts the data into an unintelligible form. In applications such as the wireless sensor networks, it plays a major role since most of the data is transmitted over an insecure channel. Symmetric key cryptosystems play a major role in such applications, since they are lightweight and faster in operation. Power dissipation of the system is another major concern for such applications as they are battery-operated devices. In this paper, the power dissipation of the circuit is enhanced by trading off area and throughput. The power is minimized by the method of parallel processing the hardware along with reduced amount of redundant hardware. The power dissipation of the circuit for the proposed structure is presented to be 2.04 times less than that of existing parallel processing structures. The proposed architecture was implemented using the industry standard Cadence® Encounter SoC tools using TSMC180 technology library.

Low-power transcutaneous current stimulator for wearable applications

BackgroundPeripheral neuropathic desensitization associated with aging, diabetes, alcoholism and HIV/AIDS, affects tens of millions of people worldwide, and there is little or no treatment available to improve sensory function. Recent studies that apply imperceptible continuous vibration or electrical stimulation have shown promise in improving sensitivity in both diseased and healthy participants. This class of interventions only has an effect during application, necessitating the design of a wearable device for everyday use. We present a circuit that allows for a low-power, low-cost and small form factor implementation of a current stimulator for the continuous application of subthreshold currents.ResultsThis circuit acts as a voltage-to-current converter and has been tested to drive + 1 to − 1 mA into a 60 kOmega load from DC to 1 kHz. Driving a 60 kOmega load with a 2 mA peak-to-peak 1 kHz sinusoid, the circuit draws less than 21 mA from a 9 V source. The minimum operating current of the circuit is less than 12 mA. Voltage compliance is ± 60 V with just 1.02 mA drawn by the high voltage current drive circuitry. The circuit was implemented as a compact 46 mm × 21 mm two-layer PCB highlighting its potential for use in a body-worn device.ConclusionsNo design to the best of our knowledge presents comparably low quiescent power with such high voltage compliance. This makes the design uniquely appropriate for low-power transcutaneous current stimulation in wearable applications. Further development of driving and instrumentation circuitry is recommended.

Low-Power Wideband Analog Channelization Filter Bank Using Passive Polyphase-FFT Techniques

Polyphase-FFT (P-FFT) techniques allow for low power implementations of high performance multi-channel filter banks by utilizing computation sharing like a standard fast Fourier transform (FFT). Additionally, it enables a longer “effective window length” than is possible in a standard FFT. This characteristic breaks the trade-off between the main-lobe width and the side-lobe amplitudes in normal finite impulse response filters. Thus, P-FFT techniques have been employed for the channelization of wideband input signals in high speed digital communication receivers. In this paper, we present a prototype analog P-FFT based filter bank in discrete time that is used to channelize wideband input signals so as to reduce the speed and dynamic range requirement of the ADCs. The four-channel I/Q prototype is implemented using TSMC’s 65 nm GP technology. Based on passive switches, the design operates at high speed, consumes low power, and offers high linearity performance. The measured transfer function shows >38 dB side-lobe suppression at 1 GS/s operation. The average measured IIP3 is +25 dBm differential power and the total integrated output noise is 208 $\mu V_{\mathrm{ rms}}$ . The total power consumption for the P-FFT filter bank (eight-channels total) is 34.6 mW (34.6 pJ/conv).

A New Method for Neural Spike Alignment: The Centroid Filter

Recordings made directly from the nervous system are a key tool in experimental electrophysiology and the development of bioelectronic medicines. Analysis of these recordings involves the identification of signals from individual neurons, a process known as spike sorting. A critical and limiting feature of spike sorting is the need to align individual spikes in time. However, electrophysiological recordings are made in extremely noisy environments that seriously limit the performance of the spike-alignment process. We present a new centroid-based method and demonstrate its effectiveness using deterministic models of nerve signals. We show that spike alignment in the presence of noise is possible with a 30 dB reduction in minimum SNR compared with the conventional methods. We present a mathematical analysis of the centroid method, characterizing its fundamental operation and performance. Furthermore, we show that the centroid method lends itself particularly well to hardware realization, and we present results from a low-power implementation that operates on an FPGA, consuming ten times less power than conventional techniques - an important property for implanted devices. Our centroid method enables the accurate alignment of spikes in sub-0 dB SNR recordings and has the potential to enable the analysis of spikes in a wider range of environments than has been previously possible. Our method thus has the potential to influence significantly the design of electrophysiological recording systems in the future.

Key alternating ciphers based on involutions

In this work, we study the security of Even–Mansour type ciphers whose encryption and decryption are based on a common primitive, namely an involution. Such ciphers possibly allow efficient hardware implementation as the same circuit is shared for encryption and decryption, and thus expected to be more suitable for lightweight environment in which low power consumption and implementation costs are desirable. With this motivation, we consider a single-round Even–Mansour cipher using an involution as its underlying primitive. The decryption of such a cipher is the same as encryption only with the order of the round keys reversed. It is known that such a cipher permits a birthday-bound attack using only construction queries, but whether it provides provable security in the range below the birthday bound has remained. We prove that the Even–Mansour cipher based on a random involution is as secure as the permutation-based one when the number of construction queries is limited by the birthday bound. In order to achieve security beyond the birthday bound, we propose a two-round Even–Mansour-like construction, dubbed $$\mathsf {EMSI}$$ , based on a single involution I using a fixed permutation $$\sigma $$ in the middle layer. Specifically, $$\mathsf {EMSI}$$ encrypts a plaintext u by computing $$\begin{aligned} v=I\left( \sigma \left( I(u\oplus k_0)\right) \oplus k_1\right) \oplus k_2 \end{aligned}$$ with the key schedule $$\gamma =(\gamma _0,\gamma _1,\gamma _2)$$ generating three round keys $$k_0=\gamma _0(k)$$ , $$k_1=\gamma _1(k)$$ and $$k_2=\gamma _2(k)$$ from an n-bit master key k. We prove that if the key schedule $$\gamma =(\gamma _0,\gamma _1,\gamma _2)$$ satisfies a certain condition, and $$\sigma $$ is a linear orthomorphism, then this construction is secure up to $$2^{\frac{2n}{3}}$$ construction and permutation queries. $$\mathsf {EMSI}$$ is the first construction that uses a single involution—a primitive weaker than a truly random permutation—and that provides security beyond the birthday bound at the same time. Encryption and decryption of $$\mathsf {EMSI}$$ are the same except for the key schedule and the middle layer. Since encryption and decryption are both based on a common primitive, $$\mathsf {EMSI}$$ is expected to be particularly suitable for modes of operation that use both encryption and decryption of the underlying block cipher such as OCB3.

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging.

Ultrasound imaging is a reference medical diagnostic technique, thanks to its blend of versatility, effectiveness, and moderate cost. The core computation of all ultrasound imaging methods is based on simple formulae, except for those required to calculate acoustic propagation delays with high precision and throughput. Unfortunately, advanced three-dimensional (3-D) systems require the calculation or storage of billions of such delay values per frame, which is a challenge. In 2-D systems, this requirement can be four orders of magnitude lower, but efficient computation is still crucial in view of low-power implementations that can be battery-operated, enabling usage in numerous additional scenarios. In this paper, we explore two smart designs of the delay generation function. To quantify their hardware cost, we implement them on FPGA and study their footprint and performance. We evaluate how these architectures scale to different ultrasound applications, from a low-power 2-D system to a next-generation 3-D machine. When using numerical approximations, we demonstrate the ability to generate delay values with sufficient throughput to support 10000-channel 3-D imaging at up to 30fps while using 63% of a Virtex 7 FPGA, requiring 24MB of external memory accessed at about 32GB/s bandwidth. Alternatively, with similar FPGA occupation, we show an exact calculation method that reaches 24fps on 1225-channel 3-D imaging and does not require external memory at all. Both designs can be scaled to use a negligible amount of resources for 2-D imaging in low-power applications and for ultrafast 2-D imaging at hundreds of frames per second.

Design and Implementation of Low Power 32 Bit Arithmetic Logic Unit

Design and Implementation of Low Power 32 Bit Arithmetic Logic Unit

Design and Implementation of Efficient Low Power Digitally Controlled Delay Line Using 45 nm CMOS Technology

Design and Implementation of Efficient Low Power Digitally Controlled Delay Line Using 45 nm CMOS Technology

VLSI Implementation of Low Power and High Speed Architecture of DWT-IDWT using Lifting based Algorithm

Objective: The purpose of this study is to optimize DWT1-IDWT2 architecture for different Image Compression techniques using lifting based algorithms. Statistical Analysis: The data in form of image and video are transmitted as signal. Because of limited channel bandwidth the data has to be compressed and this reduces the quality of the image. An algorithmic concept of encoding information is given by wavelets in a manner that is layered according to level of detail. The analysis of this implementation includes speed optimization, accuracy, and power reduction. This study uses pipelined architecture of 1D-DWT architecture and is combined with another 1D-DWT module in parallel to obtain 2D-DWT architecture to analyze the speed. Findings: The study was done using VLSI cad tools and coding was done using Verilog, by implementing the proposed algorithm with pipelined-parallel architecture for image compression using DWT, we analyzed the timing wrt* clock speed and we analyzed PSNR and SNR for different video and image compression techniques. Improvements: Our study shows higher speed can be achieved by using DWT for image compression and by using VLSI architecture, the study can be optimized to any further extent.

Pruning-Based Sparse Recovery for Electrocardiogram Reconstruction from Compressed Measurements.

Due to the necessity of the low-power implementation of newly-developed electrocardiogram (ECG) sensors, exact ECG data reconstruction from the compressed measurements has received much attention in recent years. Our interest lies in improving the compression ratio (CR), as well as the ECG reconstruction performance of the sparse signal recovery. To this end, we propose a sparse signal reconstruction method by pruning-based tree search, which attempts to choose the globally-optimal solution by minimizing the cost function. In order to achieve low complexity for the real-time implementation, we employ a novel pruning strategy to avoid exhaustive tree search. Through the restricted isometry property (RIP)-based analysis, we show that the exact recovery condition of our approach is more relaxed than any of the existing methods. Through the simulations, we demonstrate that the proposed approach outperforms the existing sparse recovery methods for ECG reconstruction.

Bio-WiTel: A Low-Power Integrated Wireless Telemetry System for Healthcare Applications in 401-406 MHz Band of MedRadio Spectrum.

This paper presents a low-power integrated wireless telemetry system (Bio-WiTel) for healthcare applications in 401-406MHz frequency band of medical device radiocommunication (MedRadio) spectrum. In this paper, necessary design considerations for telemetry system for short-range (upto 3 m) communication of biosignals are presented. These considerations help greatly in making important design decisions, which eventually lead to a simple, low power, robust, and reliable wireless system implementation. Transmitter (TX) and receiver (RX) of Bio-WiTel system have been fabricated in 180nm mixed mode CMOS technology. While radiating -18dBm output power to a 50 antenna, the packaged TX IC consumes 250μW power in 100% on state from 1 V supply, whereas the RX IC consumes 990μW power from 1.8 V supply with a sensitivity of -75dBm. Measurement results show that TX fulfils the spectral mask requirement at a maximum data rate of 72kb/s. The measured bit error rate (BER) of RX is less than for a data rate of 200kb/s. The proposed Bio-WiTel system is tested successfully in home and hospital environments for the communication of electrocardiogram and photoplethysmogram signals at a data rate of 57.6kb/s with a measured BER of <10 for a maximum distance of 3 m.

Low Power S-Box Architecture for AES Algorithm using Programmable Second Order Reversible Cellular Automata: An Application to WBAN

In this paper, we presented a novel approach of low energy consumption architecture of S-Box used in Advanced Encryption Standard (AES) algorithm using programmable second order reversible cellular automata (RCA 2). The architecture entails a low power implementation with minimal delay overhead and the performance of proposed RCA 2 based S-Box in terms of security is evaluated using the cryptographic properties such as nonlinearity, correlation immunity bias, strict avalanche criteria, entropy and also found that the proposed architecture is secure enough for cryptographic applications. Moreover, the proposed AES algorithm architecture simulation studies show that energy consumption of 68.726 nJ, power dissipation of 3.856 mW for 0.18- μm at 13.69 MHz and energy consumption of 29.408 nJ, power dissipation of 1.65 mW for 0.13- μm at 13.69 MHz. The proposed AES algorithm with RCA 2 based S-Box shows a reduction power consumption by 50 % and energy consumption by 5 % compared to best classical S-Box and composite field arithmetic based AES algorithm. Apart from that, it is also shown that RCA 2 based S-Boxes are dynamic in nature, invertible, low power dissipation compared to that of LUT based S-Box and hence suitable for Wireless Body Area Network (WBAN) applications.

Vacuum Packaged Low-Power Resonant MEMS Strain Sensor

This paper describes a technical approach toward the realization of a low-power temperature-compensated micromachined resonant strain sensor. The sensor design is based on two identical and orthogonally-oriented resonators where the differential frequency is utilized to provide an output proportional to the applied strain with temperature compensation achieved to first order. Interface circuits comprising of two front-end oscillators, a mixer, and low-pass filter are designed and fabricated in a standard 0.35- $\mu \text{m}$ CMOS process. The characterized devices demonstrate a scale factor of 2.8 Hz/ $\mu \varepsilon $ over a strain range of 1000 $\mu \varepsilon $ with excellent linearity over the measurement range. The compensated frequency drift due to temperature is reduced to 4% of the uncompensated value through this scheme. The total continuous power consumption of the strain sensor is 3 $\mu \text{W}$ from a 1.2 V supply. This low power implementation is essential to enable battery-powered or energy harvesting enabled monitoring applications. [2015-0328]

Receiver Architecture for Frequency Offset Correction and I/Q Imbalance Compensation in Equal Bandwidth Contiguous Carrier Aggregation

A highly efficient receiver architecture for intraband contiguous carrier aggregation (CA) is described. The downconversion architecture is done in two stages; the first stage is done in the analog domain using a direct-conversion receiver, whereas the second stage is done in the digital domain using offset frequency digital mixing to separate the carriers. The novelty in the architecture stems from its ability to compensate for the different carrier frequency offsets (CFOs) between the two transmitted carriers, and unlike traditional approaches, the receiver uses a single complex digital mixer for baseband carrier separation. The receiver architecture also compensates for in-phase and quadrature gain and phase imbalance (IQI) inherent in direct-conversion receivers. It is shown that, in our new architecture, IQI compensation can be done post the digital mixer, thus enabling a low-power implementation to this impairment.

Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD

Background/Objective: Now a day’s electronics industry people are concentrating on low power designs. The growing market of portable electronic systems demands microelectronic circuit with ultra low power dissipation. Method: The accomplished operations in this design are logical operations, the arithmetic operations, and branch operations. The outcome values of these operations stored in the registers and they can retrieve from the same when needed. The low power RISC processor with unbiased double precision FPU is designed without any complication, because the power reduction can do in front end technique. Findings: On MAX V CPLD a low power pipelined 64-bit RISC processor is implemented. Arithmetic operations, logical and branch functions of RISC processor are successfully verified with this design. In order to avoid any misbehavior in the jump instructions, the data will flush in the pipeline automatically by the processor architecture. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. Modelsim software is used to verify the simulation results of the design. The ALU operations and double precision floating point arithmetic operation results will be displayed on 7-Segments.

Comparative analysis of adiabatic full adder cells in CNFET technology

The advent and widespread use of portable devices and their large market share have turned the spotlight on low-power design of such battery-operated systems. Arithmetic unit is the heart of a media processor embedded in portable electronic devices. Therefore, a low-power implementation of full adder cell, which is the basic building block of arithmetic structures, may significantly reduce the whole power of the mentioned systems. One of the well-known methods for reducing power dissipation in systems with high switching activity is the adiabatic logic. Due to the problems of the MOS scaling, carbon nanotube field effect transistor (CNFET) has been introduced as the most promising replacement for today’s FET devices. In this paper, various hybrid topologies of full adder cell are reviewed and implement based on the adiabatic logic with reduced transistor count. The simulations are conducted under various conditions such as different operating frequencies, load capacitors and supply voltages that may occur in realistic conditions. Moreover, ripple carry adder is realized in both adiabatic and non-adiabatic families in order to carry out more comprehensive analyses. Finally, regarding the fact that integrated circuits in Nano regime are much more sensitive to process variations, the robustness of such circuits against these variations is surveyed and analyzed.

Design of Low Power and Secure Implementation of SBox and Inverse-SBox for AES

Design of Low Power and Secure Implementation of SBox and Inverse-SBox for AES

Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD

This article represents the implementation of low power pipelined 64-bit RISC processor on Altera MAXV CPLD device. The design is verified for arithmetic operations of both fixed and floating point numbers, branch and logical function of RISC processor. For all the jump instruction, the processor architecture will automatically flush the data in the pipeline, so as to avoid any misbehavior. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. The simulation results have been verified by using ModelSim software. The ALU operations and double precision floating point arithmetic operation results are displayed on 7-Segments. The necessary code is written in Verilog HDL.

A new neuron and synapse model suitable for low power VLSI implementation

A new dynamical neuron model for low power and compact VLSI implementation is presented. The model is capable of generating the most common type of spiking patterns. Judicious use of subthreshold CMOS design techniques leads to a very effective low-power CMOS Neuron and synapse circuits. The circuit consists of a single first-order log domain filter and a few hyperbolic function generators. We have also developed a circuit which realizes the synaptic interconnections of the neurons. Based on this complete neuron and synapse model, we studied synchronization behavior of two reciprocally interconnected neurons with excitatory and inhibitory couplings. Owing to the use of log-domain design and current-mode design, the circuits occupying low chip area and having very low power consumption are obtained even at real biological time-scale operation. These features make these circuits especially suitable for hybrid interface applications and large scale VLSI neuromorphic networks.

A CU-Level Rate and Distortion Estimation Scheme for RDO of Hardware-Friendly HEVC Encoders Using Low-Complexity Integer DCTs.

In this paper, a low complexity coding unit (CU)-level rate and distortion estimation scheme is proposed for High Efficiency Video Coding (HEVC) hardware-friendly implementation where a Walsh-Hadamard transform (WHT)-based low-complexity integer discrete cosine transform (DCT) is employed for distortion estimation. Since HEVC adopts quadtree structures of coding blocks with hierarchical coding depths, it becomes more difficult to estimate accurate rate and distortion values without actually performing transform, quantization, inverse transform, de-quantization, and entropy coding. Furthermore, DCT for rate-distortion optimization (RDO) is computationally high, because it requires a number of multiplication and addition operations for various transform block sizes of 4-, 8-, 16-, and 32-orders and requires recursive computations to decide the optimal depths of CU or transform unit. Therefore, full RDO-based encoding is highly complex, especially for low-power implementation of HEVC encoders. In this paper, a rate and distortion estimation scheme is proposed in CU levels based on a low-complexity integer DCT that can be computed in terms of WHT whose coefficients are produced in prediction stages. For rate and distortion estimation in CU levels, two orthogonal matrices of 4×4 and 8×8 , which are applied to WHT that are newly designed in a butterfly structure only with addition and shift operations. By applying the integer DCT based on the WHT and newly designed transforms in each CU block, the texture rate can precisely be estimated after quantization using the number of non-zero quantized coefficients and the distortion can also be precisely estimated in transform domain without de-quantization and inverse transform required. In addition, a non-texture rate estimation is proposed by using a pseudoentropy code to obtain accurate total rate estimates. The proposed rate and the distortion estimation scheme can effectively be used for HW-friendly implementation of HEVC encoders with 9.8% loss over HEVC full RDO, which much less than 20.3% and 30.2% loss of a conventional approach and Hadamard-only scheme, respectively.