Low-power Circuit Design Research Articles

Design of Area-Optimized Low-power Voltage Reference Circuits using a Modified Particle Swarm Optimization

Design of Area-Optimized Low-power Voltage Reference Circuits using a Modified Particle Swarm Optimization

Low-power and cost-effective readout circuit design for compact semiconductor gas sensor systems

This study introduces a novel readout circuit architecture that enhances semiconductor gas sensor systems by reducing power consumption, enabling miniaturization, and improving economic viability. Validated at the PCB level, the design shows strong commercial potential by addressing power efficiency and signal accuracy challenges. The technology is adaptable for applications in environmental monitoring, industrial safety, and medical diagnostics, where efficient and reliable gas sensing is essential.

Design and test of a sub-45 nm non-aligned double gate inverter in TCAD environment: static and dynamic analysis

ABSTRACT This work presents a sub-45 nm application-specific nanoscale single-device non-aligned double gate inverter (NADGI) with minimised gate and drain contacts. NADGI uses two devices of 25 nm channel length, i.e. NADGPFET and NADGNFET, giving maximum ON-current of 1.16 mA and 1.36 mA, respectively. The dynamic performance of the proposed structure was evaluated by applying ultra-high frequency, super-high frequency, and varying supply voltage/load capacitor. This work uses graphical method to determine the optimal supply voltage of the NADGI, the estimated values at 1 GHz and 10 GHz input frequency were 0.6 V and 0.7 V, respectively. When compared with the past works, the proposed inverter shows 82.4% improvement in propagation delay and 40% reduction in the supply voltage. Therefore, with improved design structure and response, the proposed inverter can be suitably used for high-frequency and low-power circuit design.

Analysis of the Methods for Realization of Low-Power Piezoelectric Energy Harvesting Circuits for Wearable Battery-Free Power Supply Devices

This paper presents a comprehensive review of the design and implementation methods of low-power piezoelectric energy harvesting circuits, which in the last few years have gained an extremely large range of applications like the power sources of wearable electronic devices, such as biometrical sensors. Before examining the electronic circuitries of the self-supplied power devices, an overview of the structure, equivalent electrical circuits, and basic parameters of the piezoelectric generators and MEMSs as energy harvesting elements is presented. The structure of energy storage elements (parallel-plate capacitors and thin-film supercapacitors), suitable for this type of application, is also presented. The description of these components from an electrical point of view allows them to be easily workable when connected to the various power conversion electronic circuits. Based on an overview of the structure and the principles of operation, as well as some analytical expressions for energy efficiency evaluation, a comprehensive comparative analysis is presented. Depending on the advantages and disadvantages of the known circuit configurations, the basic electrical and design parameters are systematized in tabular form. Practical realizations of piezoelectric power conversion circuits are also presented in graphic form, ensuring the optimal value of energy efficiency and compactness in the construction of the devices.

Design and application of germanium based complementary TFET devices with step tunneling paths

Expanding tunneling has consistently been one of the approaches to enhance the on-state current (Ion) and performance of Tunnel Field-Effect Transistor (TFET). This paper proposes a novel structure for TFET called Step Tunneling Path TFET (STP TFET). The stepped tunneling path is achieved by preparing majority carrier channel and introducing pocket doping layers and lightly doped channel extension regions in the channel. Taking Germanium TFET as an example, the complementary structures, electrical parameters, DC and analog characteristics of STP TFET are investigated. Simulation results demonstrate that, compared to normal TFET, STP TFET exhibits significant improvements in Ion (n-TFET∼18/p-TFET∼45 times), cut-off frequency (n-TFET∼6/p-TFET∼16 times), Gain Bandwidth Product enhancement (n-TFET∼22/p-TFET∼16 times), and Transconductance Frequency Product enhancement (n-TFET∼3/p-TFET∼15 times). Furthermore, in the C-TFET inverter, the transient rise and fall times have decreased by 149 and 199 ns, respectively, while the voltage gain has increased by 6.7 times. The proposed device shows promising potential for applications in high-speed and low-power circuit designs.

On-board drone classification with Deep Learning and System-on-Chip implementation

In recent years the increasing use of drones has raised significant concerns on safety and make them dramatic threats to security. To address these worries Counter-UAS Systems (CUS) are capturing the interest of research and of industry. Consequently, the development of effective drone detection technologies has become a critical research focus. The proposed work explores the application of edge computing to drone classification. It tunes a Deep Learning model, You Only Look Once (YOLO), and implements it on a Field Programmable Gate Array (FPGA) technology. FPGAs are considered advantageous over conventional processors since they enable parallelism and can be used to create high-speed, low-power, and low-latency circuit designs and so to satisfy the stringent Size, weight and Power (SWaP) requirements of a drone-based implementation. In details, two different YOLO neural networks YOLO v3 and v8 are trained and evaluated on a large data set constructed with drones’ images at various distances. The two models are then implemented on a System-on-Chip (SoC). In order to demonstrate the feasibility of a drone on board image Artificial Intelligence processing, the evaluation assesses the accuracy of classification and the computational performances such as latency.

A low power circuit design of BLE baseband transmission data processing module

With the quickly development of the Internet of Things technology, Bluetooth (BLE) protocol has been increasingly adopted in consumer communication applications, industry communication utilization, and even positioning requirement, due to its advantages such as low power consumption, low cost, and low complexity. Especially the outstanding low power capability compared with other short-range communication protocol, many power limited AIoT (Artificial Intelligence IoT) devices select BLE as basic component. So, the low power, high performance, and small area BLE module become the key point of successful of whole AIoT system. In BLE system, the baseband data processing is the foundation. A good hardware circuit design of BLE baseband can improve BLE module performance and decrease power simultaneously. This paper analyzes the baseband data processing function of BLE in detail, and designs the baseband transmission data processing RTL circuit IP using Verilog HDL Hardware description language based on BLE protocol. The IP includes CRC verification module, whitening module and coding mapping function module. The RTL design is simulated and evaluated in workstation server with Synopsys VCS tool. The simulation results show that this design can achieve the Low-power BLE Bluetooth baseband function.

Design of low-noise low-power ECG amplifier circuit with high integration level

Electrocardiogram (ECG) is a common tool in medicine and is an important indicator for diagnosing many diseases. Nowadays, aspects such as low noise, low power, and high integration have become important indicators for ECG circuit design. Also, due to the low amplitude of ECG signals, ECG circuits need to have high gain to ensure accurate signal detection and analysis. Second, ECG signals are usually subject to interference from other parts of the body, so a high common mode rejection ratio (CMRR) is required to suppress these interfering signals. In this paper, we propose an ECG circuit composed of an amplifier with a drive right leg circuit (DRL) using pseudo-resistors as well as capacitors to improve the common instrumentation amplifier. The simulation using industrial-grade simulation software LTspice shows that the circuit has a voltage of 1.8 V, a bandwidth of 17 mHz-1 KHz, a gain of 55 dB, and an INR of 3.4 μVrms, and because the signal amplifier part of this circuit design consists of only pseudo-pseudo-resistors, capacitors, and mos tubes. Therefore, it has a smaller size and a higher degree of integration. In addition, the circuit has less power loss for the same amplification design. Overall, this design has excellent characteristics such as low noise, low power, and small size.

Wide-range and area-selective threshold voltage tunability in ultrathin indium oxide transistors

The scaling of transistors with thinner channel thicknesses has led to a surge in research on two-dimensional (2D) and quasi-2D semiconductors. However, modulating the threshold voltage (VT) in ultrathin transistors is challenging, as traditional doping methods are not readily applicable. In this work, we introduce a optical-thermal method, combining ultraviolet (UV) illumination and oxygen annealing, to achieve broad-range VT tunability in ultrathin In2O3. This method can achieve both positive and negative VT tuning and is reversible. The modulation of sheet carrier density, which corresponds to VT shift, is comparable to that obtained using other doping and capacitive charging techniques in other ultrathin transistors, including 2D semiconductors. With the controllability of VT, we successfully demonstrate the realization of depletion-load inverter and multi-state logic devices, as well as wafer-scale VT modulation via an automated laser system, showcasing its potential for low-power circuit design and non-von Neumann computing applications.

Trends in volumetric-energy efficiency of implantable neurostimulators: a review from a circuits and systems perspective.

This paper presents a comprehensive review of state-of-the-art, commercially available neurostimulators. We analyse key design parameters and performance metrics of 45 implantable medical devices across six neural target categories: deep brain, vagus nerve, spinal cord, phrenic nerve, sacral nerve and hypoglossal nerve. We then benchmark these alongside modern cardiac pacemaker devices that represent a more established market. This work studies trends in device size, electrode number, battery technology (i.e., primary and secondary use and chemistry), power consumption and longevity. This information is analysed to show the course of design decisions adopted by industry and identifying opportunity for further innovation. We identify fundamental limits in power consumption, longevity and size as well as the interdependencies and trade-offs. We propose a figureof merit to quantify volumetric efficiency within specific therapeutic targets, battery technologies/capacities, charging capabilities and electrode count. Finally, we compare commercially available implantable medical devices with recently developed systems in the research community. We envisage this analysis to aid circuit and system designers in system optimisation and identifying innovation opportunities, particularly those related to low power circuit design techniques.

DESIGN OF LOW POWER HIGH SPEED CNTFET ADDER SUBTRACTOR

Multi-valued logic design itself is not sufficient to achieve the performance improvement in digital system design in nanotechnology. The need to replace silicon devices with some more efficient new devices are required so as to meet the power improvements in the nanoscale region. Among various devices explored, CNTFET is the most promising alternative to replace conventional MOS transistors. These nano devices have the benefits of low power consumption due to reduced leakage component, ballistic transport operation even at low supply voltages makes them suitable for high frequency and low voltage applications. MVL circuitry has soared in popularity because the threshold voltage of the CNFET device is somewhat adjustable by the diameter of carbon nanotubes. CNFET is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Carbon Nanotube Filed-Effect Transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry- dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed design. In this paper, we present a novel high speed Adder-subtractor cell using CNFETs based on XOR gates and multiplexer. Proposed design uses fourteen transistors, ten for full adder and four to modify the cell for subtraction. Simulation results show significant improvement in terms of delay and area saving with respectively compared to the latest design. Simulations were carried out using HSPICE based on CNFET model with optimized design parameters. All designs are simulated at 32nm CNFET with HSPICE. The simulation results show that on average, speed enhancement and area saving of 48% and 11% can be achieved with optimized parameters design over default values of these parameters. The cumulative benefits of the novel adder-subtractor design based CNFET result in an PDP reduction by a factor of 41%.

Low Power ALU using Wave Shaping Diode Adiabatic Logic

The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.

A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process

To maintain performance increase and reliability, power supply and threshold voltages will have to continually scale, in CMOS technology. With threshold voltage scaling and thinner gate-oxide thickness, sub-threshold and gate tunneling leakage powers are expected to become a significant portion of the total power in CMOS VLSI systems. A self-control leakage-suppression block (SCLSB) for leakage power reduction of static CMOS gates is proposed in this paper. The proposed SCLSB consists of two PMOS and two NMOS transistors that are located between pull-down network (PDN) and pull-up network (PUN). In any combination of input signals, one PMOS and one NMOS transistor of SCLSB turn on and the rest turn off, hence the resistance between the power supply voltage rail to the ground rail increased and leakage currents greatly reduced. The basic static CMOS gates such as inverter, NAND, NOR, and XOR circuits are designed based on SCLSB and their performance is evaluated using SPICE simulations in 22 nm CMOS BSIM4 process. Evaluation outcomes with VDD = 0.9 V depict that power-delay product (PDP) is diminished by 9%, 12.8%, 6%, and 15.25% for inverter, NAND, NOR, and XOR compared to the best counterpart (LECTOR) and by 9%, 35%, 21.5% and 33.8% compared to the conventional CMOS gates. The mentioned features of the proposed static-CMOS circuits are achieved while sustaining the full-swing behavior. To ensure the stability and robustness of the circuits in the presence of the process, voltage, and temperature (PVT) variations, Monte Carlo analysis is also performed.

Synapse and Tunable Leaky-Integrate Neuron Functions Enabled by Oxide Trapping Dynamics in a Single Logic Transistor

We show that a high-k gated n-MOSFET can embody both the memory plasticity of a synapse and leaky-integration of a neuron, by virtue of the rich temporal dynamics of charge capture/emission by gate-oxide defects. In addition, a tunable leaky-integrate function is demonstrated. The lower limit of energy per input spike is on the order of fJ, which provides room for low-power trigger circuit design and scalability. This work points to the prospect of a gate-engineered logic transistor serving as the universal building block of hardware spiking neural networks, thereby accelerating the realization of compact, energy efficient neuromorphic computers given the relative maturity of the transistor technology.

Low power architecture of logic gates using adiabatic techniques

The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.

Through the Looking Glass—The 2022 Edition: Trends in solid-state circuits from ISSCC

The International Solid-State Circuits Conference (ISSCC) is the flagship conference of the IEEE Solid-State Circuits Society. The theme for ISSCC 2022 is “Intelligent Silicon for a Sustainable World.” This theme further highlights the fact that to cope with strong environmental changes, the circuit design community is evolving more than ever to support a more sustainable world. Given their widespread use in our everyday lives, without change, ICs will become the dominant energy consumer and source of carbon emissions in the (near) future. Despite phenomenal advances in solid-state circuits and systems, low-power circuit design is becoming increasingly more sophisticated in all application areas, from digital computation and machine learning to analog design. In the context of data communications, advances in wireless and wireline circuits will help optimize local and global communications energy. Various sensors can be deployed to measure environmental data and optimize energy consumption. Power management techniques continue to be an essential aspect of a majority of circuits and systems to extend their lifetime and battery longevity. Furthermore, new technologies are providing opportunities to develop innovative circuits, reduce fabrication impacts, and improve recyclability.

Modeling of the Gate Tunneling Current in MFIS NCFETs

In this article, we present a model for the gate tunneling current (GTC) in metal-ferroelectric-insulator-semiconductor (MFIS) negative capacitance FETs (NCFETs), which, to the best of our knowledge, is the first such report. The model is numerical in nature, and is developed using the Tsu–Esaki formulation, employing the Wentzel–Kramer–Brillouin (WKB) approximation, in order to estimate the transmission coefficients of the carriers through the barriers. The ferroelectric (FE) material considered is HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and is modeled using the Landau phase transition theory. Simulation results reveal a remarkable nonmonotonic dependence of the GTC on the FE layer thickness, an effect that we explain through the Landau model. Furthermore, it is shown how this GTC can be reduced by orders of magnitude without changing the overall dielectric capacitance—a feature that may prove to be beneficial in low-power circuit designs. Additionally, it is seen that the GTC is a weak function of the remanent polarization and coercive field of the FE. All the model predictions are validated through a comparison with the results obtained from Sentaurus 2-D TCAD simulations. The novel results presented in this work should serve as a guide for detailed experimental studies on the gate current characteristics of MFIS NCFETs.

Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms

This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed and verified using the proposed design tool. It is also shown in this paper that, the design results obtained from the proposed algorithm in MATLAB, have a very good agreement with the obtained circuit simulation results in HSPICE.

Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms

Design of low-power CMOS VLSI circuits using multi-objective optimization in genetic algorithms

Trends in Design of Low Power Circuits Using Level Shifting Buffers for Multi Supply Systems

Power and performance efficiencies are the most important design parameters in system – on - chip design. Numbers of methods were developed for reducing the power and delay by reducing supply voltage and multi supply voltages. Multiple supply voltage designs need voltage level conversions between multiple voltage domains. This is achieved by the application of voltage level shifter (LS) circuits. LSs are an interfacing circuit which interconnects low core voltage to high core voltage and vice versa. LS ease communication among diverse modules. However literature reported that the conventional LSs suffer from delay variation due to dissimilar current driving transistors along with high power dissipation. This paper presents the identification of limitations and design aspects of existing LSs through an extensive literature survey and to project the current state of LSs. This study concentrates on multiple supply voltages, power consumption, and speed of processing in ICs. The detailed literature review is expected to pave way for addressing the issues and challenges related to LSs and helps in design and development of efficient low-power multivoltage LSs in the design aspects of VLSI circuits.