Low-power Application-specific Integrated Circuit Research Articles

A Wirelessly Powered Scattered Neural Recording Wearable System.

This paper introduces a wirelessly powered scattered neural recording wearable system that can facilitate continuous, untethered, and long-term electroencephalogram (EEG) recording. The proposed system, including 32 standalone EEG recording devices and a central controller, is incorporated in a wearable form factor. The standalone devices are sparsely distributed on the scalp, allowing for flexible placement and varying quantities to provide extensive spatial coverage and scalability. Each standalone device featuring a low-power EEG recording application-specific integrated circuit (ASIC) wirelessly receives power through a 60 MHz inductive link. The low-power ASIC design (84.6 μW) ensures sufficient wireless power reception through a small receiver (Rx) coil. The 60 MHz inductive link also serves as the data carrier for wireless communication between standalone devices and the central controller, eliminating the need for additional data antennas. All these efforts contribute to the miniaturization of standalone devices with dimensions of 12×12×5 mm3, enhancing device wearability. The central controller applies the pulse width modulation (PWM) scheme on the 60 MHz carrier, transmitting user commands at 4 Mbps to EEG recording ASICs. The ASIC employs a novel synchronized PWM demodulator to extract user commands, operating signal digitization and data transmission. The analog frontend (AFE) amplifies the EEG signal with a gain of 45 dB and applies band-pass filtering from 0.03 Hz to 400 Hz, with an input-referred noise (IRN) of 3.62 μVRMS. The amplified EEG signal is then digitized by a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with a peak signal-to-noise and distortion ratio (SNDR) of 55.4 dB. The resulting EEG data is transmitted to an external software-defined radio (SDR) Rx through load-shift-keying (LSK) backscatter at 3.75 Mbps. The system's functionality is fully evaluated in human experiments.

An 8-channel low power ASIC for Helium-3 tube position sensitive neutron detectors

The majority of neutron spectrometers designated for use in the China Spallation Neutron Source (CSNS) rely on position-sensitive detectors that utilize Helium-3 tube detector technology. To minimize the impact of air on neutron scattering experiments, detectors must be located inside a vacuum chamber. For these types of spectrometers, it is also advisable to house the readout electronics within the vacuum chamber to limit the number of feed-through cables required and enhance the signal-to-noise ratio. This paper proposes an application-specific integrated circuit (ASIC) dedicated to position-sensitive Helium-3 tube detectors, including front-end amplification, shaping module and readout driving buffer. The 8-channel chip, named HEROCV1 (HElium-3 ReadOut Circuits), achieves an input dynamic range from 10 fC to 1 pC, with a counting rate of up to 100 kHz. The equivalent noise charge (ENC) measurement is 1297e-@15pF, and the power consumption is less than 9.9 mW per channel. The ASIC has replaced the traditional front-end circuit based on discrete components, fundamentally addressing the issue of front-end power consumption and enabling the entire detector system to operate in a vacuum environment.

A new deterministic PSO algorithm for real-time systems implemented on low-power devices

The paper presents a novel, deterministic particle swarm optimization (PSO) algorithm, facilitating its implementation in low-power application specific integrated circuits (ASIC) realized in CMOS technology. The PSO algorithms are commonly used in a variety of optimization problems. They allow to search for a global extreme in a selected fitness function, which is used for numerical modeling of specific optimized problems. The conventional version of the algorithm is relatively difficult to implement directly in hardware, especially when each particle is represented by a separate circuit working in parallel with other particles. In such a situation, each particle has to be equipped with its own copy of each function. One of the problems is, for example, an efficient realization of the random function block that provides for each particle some factors used in computing a cognitive and a social velocity components. In this paper we shows a novel way to work around this problem. In the proposed approach the random function does not need to be used. It has been replaced by a simple computationally deterministic mechanism, which at the level of the overall swarm allows for effective emulation of the former random mechanism. We proposed such simplifications that reduce the formulas describing the algorithm to only basic arithmetic and logic operations. Comprehensive investigations have shown that performance of the proposed approach is comparable with its original version or in may situations even better. The proposed algorithm was tested with numerous test functions (50 runs for each tested function), to verify its flexibility and adaptation abilities to different problems.

Highly Miniaturized, Low-Power CMOS ASIC Chip for Long-Term Continuous Glucose Monitoring.

The objective of this work is to develop a highly miniaturized, low-power, biosensing platform for continuous glucose monitoring (CGM). This platform is based on an application-specific integrated circuit (ASIC) chip that interfaces with an amperometric glucose-sensing element. To reduce both size and power requirements, this custom ASIC chip was implemented using 65-nm complementary metal oxide semiconductor (CMOS) technology node. Interfacing this chip to a frequency-counting microprocessor with storage capabilities, a miniaturized transcutaneous CGM system can be constructed for small laboratory animals, with long battery life. A 0.45 mm × 1.12 mm custom ASIC chip was first designed and implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology node. This ASIC chip was then interfaced with a multi-layer amperometric glucose-sensing element and a frequency-counting microprocessor with storage capabilities. Variation in glucose levels generates a linear increase in frequency response of this ASIC chip. In vivo experiments were conducted in healthy Sprague Dawley rats. This highly miniaturized, 65-nm custom ASIC chip has an overall power consumption of circa 36 µW. In vitro testing shows that this ASIC chip produces a linear (R2 = 99.5) frequency response to varying glucose levels (from 2 to 25 mM), with a sensitivity of 1278 Hz/mM. In vivo testing in unrestrained healthy rats demonstrated long-term CGM (six days/per charge) with rapid glucose response to glycemic variations induced by isoflurane anesthesia and tail vein injection. The miniature footprint of the biosensor platform, together with its low-power consumption, renders this CMOS ASIC chip a versatile platform for a variety of highly miniaturized devices, intended to improve the quality of life of patients with type 1 and type 2 diabetes.

A wireless battery-less and moisture-resistant packaged glucose sensing system employing hydrogel-based inductive sensing technique and low-power ASIC for long-term glucose monitoring

A wireless and battery-less glucose sensing system has been demonstrated for future long-term implantable glucose monitoring. The proposed glucose sensing system employs an oscillator-based inductive sensor that detects a volumetric change of a glucose-sensitive hydrogel. A robust 3D-printed moisture-resistant package is used to encapsulate the sensing system for in-vitro characterization. An application-specific integrated circuit (ASIC) is designed to enable in-situ temperature characterization as well as system miniaturization. The overall system dissipates 600 μW and exhibits a dimension of 6 mm × 6 mm x 25 mm. A rotation-insensitive wireless powering scheme has been demonstrated to reliably deliver power to a tube-shaped implantable system. The prototype sensor operated at 190 MHz can be wirelessly powered by a 6.78 MHz RF power source over a distance of 2 cm. The sensor achieves a glucose sensing resolution of 0.025–0.055 mM within a typical physiological glucose concentration between 4 mM and 10 mM at a typical human body temperature of 37 ºC. The prototype sensor has demonstrated a reliable in-vitro operation for 60 days without noticeable performance degradation.

In Vivo Evaluation of a Subcutaneously Injectable Implant with a Low-Power Photoplethysmography ASIC for Animal Monitoring.

Photoplethysmography is an extensively-used, portable, and noninvasive technique for measuring vital parameters such as heart rate, respiration rate, and blood pressure. The deployment of this technology in veterinary medicine has been hindered by the challenges in effective transmission of light presented by the thick layer of skin and fur of the animal. We propose an injectable capsule system to circumvent these limitations by accessing the subcutaneous tissue to enable reliable signal acquisition even with lower light brightness. In addition to the reduction of power usage, the injection of the capsule offers a less invasive alternative to surgical implantation. Our current prototype combines two application-specific integrated circuits (ASICs) with a microcontroller and interfaces with a commercial light emitting diode (LED) and photodetector pair. These ASICs implement a signal-conditioning analog front end circuit and a frequency-shift keying (FSK) transmitter respectively. The small footprint of the ASICs is the key in the integration of the complete system inside a 40-mm long glass tube with an inner diameter of 4 mm, which enables its injection using a custom syringe similar to the ones used with microchip implants for animal identification. The recorded data is transferred wirelessly to a computer for post-processing by means of the integrated FSK transmitter and a software-defined radio. Our optimized LED duty cycle of 0.4% at a sampling rate of 200 Hz minimizes the contribution of the LED driver (only 0.8 mW including the front-end circuitry) to the total power consumption of the system. This will allow longer recording periods between the charging cycles of the batteries, which is critical given the very limited space inside the capsule. In this work, we demonstrate the wireless operation of the injectable system with a human subject holding the sensor between the fingers and the in vivo functionality of the subcutaneous sensing on a pilot study performed on anesthetized rat subjects.

ALTAIR: A Low-Noise, Low-Power, High-Speed and Wide Dynamic Range ASIC for X- and γ-Ray Spectroscopy With CdTe/CdZnTe Pixel Detectors

ALTAIR is an application-specific integrated circuit (ASIC) developed for the readout of CdTe/CdZnTe detectors for X-γ-ray spectroscopic imaging. ALTAIR is composed of 16 channels with analog and mixed-signal sections specifically designed for high energy resolution and high-rate applications with the constraints of a low power consumption and operation at room temperature. The ASIC has three selectable ranges for input charge signals covering photon energies up to 90, 160, or 300 keV, which allow to optimize the signal-to-noise ratio under different experimental conditions. Eight peaking times of the pulse shaper are selectable from 200 up to 2.3 μs. ALTAIR includes a 180 bits register and an integrated serial peripheral interface (SPI) interface to configure the signal-processing parameters globally or independently for each channel. The power consumption is 950 μW/channel or 1.35 mW/channel for single-ended or differential output versions, respectively. A minimum equivalent noise charge (ENC) of 37 electrons rms [386 eV full-width at half-maximum (FWHM) in CdTe] has been measured at 500 ns peaking time and 90-keV energy range. With a CdTe pixel detector connected to ALTAIR and operated at +24 °C, a pulser FWHM of 1.7 keV (160 el. rms) and 1.9-keV FWHM on 59.54 keV line of <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">241</sup> Am have been achieved at a peaking time of 500 ns.

A high time resolution and low-power ASIC for MRPC applications

The structure of readout circuits needs to be improved to meet the requirements of the endcap time of flight upgrade with multi-gap resistive plate chamber (MRPC) in Beijing Spectrometer III experiments, posing a demand for the high time resolution and low-power electronics. Considering MRPC features, an application-specific integrated circuit (ASIC) called FEEWAVE, which integrates the front-end circuit and digitization function, is proposed to meet the above requirements. The front-end circuit implements I/V conversion and signal amplification. To reduce power consumption and further improve the time resolution, the waveform sampling technique based on switch capacitor array is adopted. A 30 fC to 1.2 pC input signal dynamic range is obtained, and the jitter is less than 21 ps rms. At the same time, the chip realizes 5 GSPS (gigabit samples per second) sampling rate, trigger rate capability of 50 kHz and 25 mW/channel power consumption. The 6-channel ASIC has been designed and taped out with 0.18 $$\upmu $$m complementary metal oxide semiconductor technology. The preliminary test results of FEEWAVE have been achieved.

Low-power ASIC suitable for miniaturized wireless EMG systems

Abstract Nowadays, the technology advancements of signal processing, low-voltage low-power circuits and miniaturized circuits have enabled the design of compact, battery-powered, high performance solutions for a wide range of, particularly, biomedical applications. Novel sensors for human biomedical signals are creating new opportunities for low weight wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents the design and implementation of a novel miniaturized low-power sensor in integrated circuit (IC) form suitable for wireless electromyogram (EMG) systems. Signal inputs (electrodes) are connected to this application-specific integrated circuit (ASIC). The ASIC consists of several consecutive parts. Signals from electrodes are fed to an instrumentation amplifier (INA) with fixed gain of 50 and filtered by two filters (a low-pass and high-pass filter), which remove useless signals and noise with frequencies below 20 Hz and above 500 Hz. Then signal is amplified by a variable gain amplifier. The INA together with the reconfigurable amplifier provide overall gain of 50, 200, 500 or 1250. The amplified signal is then converted to pulse density modulated (PDM) signal using a 12-bit delta-sigma modulator. The ASIC is fabricated in TSMC0.18 mixed-signal CMOS technology.

CMOS stimulating chips capable of wirelessly driving 473 electrodes for a cortical vision prosthesis

Objective. Implantable neural stimulating and recording devices have the potential to restore capabilities such as vision or motor control to disabled patients, improving quality of life. Implants with a large number of stimulating electrodes typically utilize implanted batteries and/or subcutaneous wiring to deal with their high-power consumption and high data throughput needed to address all electrodes with low latency. The use of batteries places severe limitations on the implant’s size, usable duty cycle, device longevity while subcutaneous wiring increases the risk of infection and mechanical damage due to device movement. Approach. To overcome these limitations, we have designed and implemented a system that supports up to 473 implanted stimulating microelectrodes, all wirelessly powered and individually controlled by micropower application specific integrated circuits (ASICs). Main results. Each ASIC controls 43 electrodes and draws 3.18 mW of power when stimulating through 24 channels. We measured the linearity of the digital-to-analog convertors (DACs) to be 0.21 LSB (integrated non-linearity) and the variability in timing of stimulation pulses across ASICs to be 172 ns. Significance. This work demonstrates the feasibility of a new low power ASIC designed to be implanted in the visual cortex of humans. The fully implantable device will greatly reduce the risks of infection and damage due to mechanical issues.

Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0–30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space.

Design of a video capsule endoscopy system with low-power ASIC for monitoring gastrointestinal tract.

In recent years, wireless capsule endoscopy (WCE) has been a state-of-the-art tool to examine disorders of the human gastrointestinal tract painlessly. However, system miniaturization, enhancement of the image-data transfer rate and power consumption reduction for the capsule are still key challenges. In this paper, a video capsule endoscopy system with a low-power controlling and processing application-specific integrated circuit (ASIC) is designed and fabricated. In the design, these challenges are resolved by employing a microimage sensor, a novel radio frequency transmitter with an on-off keying modulation rate of 20Mbps, and an ASIC structure that includes a clock management module, a power-efficient image compression module and a power management unit. An ASIC-based prototype capsule, which measures Φ11mm×25mm, has been developed here. Test results show that the designed ASIC consumes much less power than most of the other WCE systems and that its total power consumption per frame is the least. The image compression module can realize high near-lossless compression rate (3.69) and high image quality (46.2dB). The proposed system supports multi-spectral imaging, including white light imaging and autofluorescence imaging, at a maximum frame rate of 24fps and with a resolution of 400×400. Tests and in vivo trials in pigs have proved the feasibility of the entire system, but further improvements in capsule control and compression performance inside the ASIC are needed in the future.

Design of the Readout Electronics for the BGO Calorimeter of DAMPE Mission

The DAMPE (DArk Matter Particle Explorer) is a scientific satellite being developed in China, aimed at cosmic ray study, gamma ray astronomy, and searching for the clue of dark matter particles in the near future. The BGO (Bismuth Germanate Oxide) Calorimeter, which consists of 616 PMTs (photomultiplier tubes) and 1848 dynode signals, is a crucial part of the DAMPE payload for measuring the energy of cosmic ray particles, distinguishing interesting particles from background, and providing trigger information. An electronics system, which consists of 16 FEE (Front End Electronics) modules with a total power consumption of about 26 W, has been developed. Its main functions are based on the low power, 32-channel VA160 and VATA160 ASICs (Application Specific Integrated Circuits) for precisely measuring the charge of PMT signals and providing“hit”signals as well. To assure the long-term reliability in harsh space environment, a series of critical issues such as the radiation hardness, thermal design, components and board level quality control, etc., are taken into consideration. Test result showed that the system level ENC (equivalent noise charge) for each channel is about 10 fC in RMS (root mean square), and the timing uncertainty of the hit signals is about 300 ns, both of which satisfy the physics requirements of the detector. Experiments with $^{60}{\hbox {Co}}$ radioactive source proved that 20 krad(Si) TID (Total Ionizing Dose) level is achieved, while the heavy ion beam and laser beam tests indicated that its SEL (Single Event Latch-up) and SEU (Single Event Upset) performance in orbit will be acceptable by taking some hardness measures. All the readout modules successfully passed the board-level screening, the sub-system level and finally the satellite system level environmental tests, and behave well in the beam test at CERN (European Organisation for Nuclear Research).

Test of a 32-channel Prototype ASIC for Photon Counting Application.

A new low-power application-specific integrated circuit (ASIC) for Cadmium Zinc Telluride (CZT) detectors for single-photon emission computed tomography (SPECT) application is being developed at BNL. As the first step, a 32-channel prototype ASIC was designed and tested recently. Each channel has a preamplifier followed by CR-RC3 shaping circuits and three independent energy bins with comparators and 16-bit counters. The ASIC was fabricated with TSMC 0.35-μm complementary metal-oxide-semiconductor (CMOS) process and tested in laboratories. The power consumption is around 1 mW/ch with a 2.5-V supply. With a gain of 400 mV/fC and the peaking time of 500 ns, the equivalent noise charge (ENC) of 360 e- has been measured in room temperature while the crosstalk rate is less than 0.3%. The 10-bit DACs for global thresholds have an integral nonlinearity (INL) less than 0.56% and differential nonlinearity (DNL) less than 0.33%. In the presentation, we will report the detailed test results with this ASIC.

An Implantable Telemetry Platform System With ASIC for &lt;italic&gt;in Vivo&lt;/italic&gt; Monitoring of Gastrointestinal Physiological Information

This paper presents a multiple channel, implantable biotelemetry platform, suitable for in vivo monitoring of gastrointestinal (GI) physiological information. This system consists of a wireless capsule, a portable data recorder, and a workstation; it can digitalize and transmit up to four analog signals coming from different sensors. Several design challenges involving system miniaturization, sensor-precision improvement, and power-dissipation reduction were resolved by employing optimized architecture, microsensors, and a low-power application-specific integrated circuit (ASIC) that applied a very large scale integration architecture of three-stage clock management, power management, and an 18-bits full-differential input sigma–delta analog-to-digital converter. pH, temperature, and pressure sensors were manufactured and assembled with the ASIC and the transmission circuit into an elliptical capsule. The capsule measured 25 mm in length and 11 mm in diameter to ensure that it would be easy for patients to swallow yet able to transmit GI physiological information wirelessly. Because of the implementation of the low-power ASIC, the capsule can work normally for 136 h with three 1.5 V 22-mA button batteries. The system performances were assessed through several vivid tests. In addition, results from 22 cases of application in humans are reported in this paper.

VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD’s). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500eV and 50keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6µs to 6.6µs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35µm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200µm×500µm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6µs peaking time and room temperature is measured and the linearity error is between −0.9% and +0.6% in the whole input energy range. The total power consumption is 481µW and 420µW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD’s shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

A low-power CMOS ASIC for X-ray Silicon Drift Detectors low-noise pulse processing

We present an Application Specific Integrated Circuit (ASIC), named VEGA-1, designed and manufactured for low-power analog pulse processing of signals from Silicon Drift Detectors (SDDs). The VEGA-1 ASIC consists of an analog and a digital/mixed-signal section to achieve all the functionalities and specifications required for high-resolution X-ray spectroscopy in the energy range from 500 eV to 60 keV with low power consumption. The VEGA-1 ASIC has been designed and manufactured in 0.35-μm CMOS mixed-signal technology in single and 32-channel version with dimensions of 200 μm × 500 μm per channel. A minimum intrinsic ENC of 12 electrons r.m.s. at 3.6 μs shaping time and room temperature is measured for the ASIC without detector. The VEGA-1 has been tested with Q10-SDD designed in Trieste and fabricated at FBK, with an active area of 10 mm2 and a thickness of 450 μm. The aforementioned detector has an anode current of about 180 pA at +22°C. A minimum Equivalent Noise Charge (ENC) of 16 electrons r.m.s. at 3.0 μs shaping time and −30°C has been demonstrated with a total measured power consumption of 482 μW.

CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 μm CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke− (1.2 fC) with an input capacitance of 3.3 pF. With this value of input capacitance a timing resolution down to 10 ps RMS was measured for pulser signals of a few million electrons, corresponding to the single photon response for these detectors.

Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC

Modified discrete cosine transform (MDCT) is used in many audio coding standards for time-to-frequency transformation of digital signals. It is one of the most computationally intensive operations in audio compression and decompression processes. In this study, optimised dedicated hardware architectures utilised in a highly scalable MDCT IP core are proposed to accelerate the forward/backward MDCT computation in MP3 audio coding standard. The MDCT IP core is pipelined, capable to compute both the forward and backward MDCT on the same hardware and it is optimised with field-programmable gate arrays (FPGA) and application-specific integrated circuit (ASIC) technologies. The MDCT IP core is implemented to FPGA and ASIC, whereby the FPGA implementation used Xilinx Virtex-4 FPGA, while the ASIC implementation used AMS 350 nm CMOS standard cell library. The MDCT IP core is further optimised and implemented utilising UMC 90 nm CMOS low-power digital libraries and clock gating technique. As a result, power consumption and the area are reduced significantly. The proposed hardware architectures are optimised to achieve high computational speed with high precision, and therefore they are suitable for a lossless audio compression. In particular, high computational speed permits multichannel real-time acceleration of the forward and backward MDCT computation.

Large area high temperature hard X-ray spectroscopy detectors for space experiments

High quantum efficiency, good energy resolution and room temperature operation make Cadmium Zinc Telluride (CZT) pixel detector an unique advantage for space experiments. We present here the results of two large area CZT detector systems; one with external ADC (Analog-to-Digital Converter) and high power Application-Specific Integrated Circuits (ASICs)(Ideas) having faster parallel readout system and the other with on-pixel ADC and low power ASICs (OrboTech) having slower serial readout system. We have studied background, energy resolution and detection efficiency of these detectors between 20 and 100keV. For Ideas detectors, large power dissipation in ASICs increases the detector temperature (upto 70°C) and the thermal background. This rise in temperature increases thermal noise sharply which drastically affects both the energy resolution as well as the detection efficiency. The low energy dissipation in OrboTech ASICs keeps the detector temperature low & constant, making thermal background stable. We find that OrboTech resolution & efficiency are far better than that of Ideas detector in spite of slower readout system. We further discuss the use of these detectors in space experiments.