Low Oxide Field Research Articles

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET) structure with side-wall p-type pillar (p-pillar) and wrap n-type pillar (n-pillar) in the n-drain was investigated by utilizing Silvaco TCAD simulations. The optimized structure mainly includes a p+ buried region, a light n-type current spreading layer (CSL), a p-type pillar region, and a wrapping n-type pillar region at the right and bottom of the p-pillar. The improved structure is named as SNPPT-MOS. The side-wall p-pillar region could better relieve the high electric field around the p+ shielding region and the gate oxide in the off-state mode. The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance (R on,sp). As a result, the SNPPT-MOS structure exhibits that the figure of merit (FoM) related to the breakdown voltage (V BR) and R on,sp () of the SNPPT-MOS is improved by 44.5%, in comparison to that of the conventional trench gate SJ MOSFET (full-SJ-MOS). In addition, the SNPPT-MOS structure achieves a much faster-witching speed than the full-SJ-MOS, and the result indicates an appreciable reduction in the switching energy loss.

A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance

A split gate MOSFET (SG-MOSFET) is widely known for reducing the reverse transfer capacitance (C RSS). In a 3.3 kV class, the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field. In addition to the poor static performance, the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering (DIBL) caused by the high gate oxide electric field. As such, a 3.3 kV 4H-SiC split gate MOSFET with a grounded central implant region (SG-CIMOSFET) is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance. The SG-CIMOSFET has a significantly low on-resistance (R ON) and maximum gate oxide field (E OX) due to the central implant region. A grounded central implant region significantly reduces the C RSS and gate drain charge (Q GD) by partially screening the gate-to-drain capacitive coupling. Compared to a planar MOSFET, the SG MOSFET, central implant MOSFET (CIMOSFET), the SG-CIMOSFET improve the R ON×Q GD by 83.7%, 72.4% and 44.5%, respectively. The results show that the device features not only the smallest switching energy loss but also the fastest switching time.

Time-Dependent Dielectric Breakdown of Commercial 1.2 kV 4H-SiC Power MOSFETs

Constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on recently manufactured commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs) from three vendors. Abrupt changes of the electric field acceleration parameters ( γ) are observed at oxide electric fields ( E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> ) around 8.5 MV/cm to 9 MV/cm for all commercial MOSFETs. Gate leakage currents and threshold voltage shifts are also monitored under different oxide fields ( E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> = 8 MV/cm and 10 MV/cm). The results suggest the failure mode under high oxide electric field is modified by impact ionization or Anode Hole Injection (AHI) induced hole trapping. This observation agrees with previously published oxide reliability studies on SiC MOSFETs and suggests that constant-voltage TDDB measurements need to be carefully performed under low oxide fields to avoid lifetime overestimation caused by hole trapping. The extrapolated t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">63%</sub> lifetimes (times to 63% failures) from TDDB measurements performed at E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> <; 8.5 MV/cm are longer than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> hours at 150°C for all vendors. The predicted lifetimes at E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> = 4 MV/cm demonstrate more than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> times increases than the oxide lifetimes reported a decade ago, showing promising progress in SiC technology.

A New SiC Planar-Gate IGBT for Injection Enhancement Effect and Low Oxide Field

A new silicon carbide (SiC) planar-gate insulated-gate bipolar transistor (IGBT) is proposed and comprehensively investigated in this paper. Compared to the traditional SiC planar-gate IGBT, the new IGBT boasts a much stronger injection enhancement effect, which leads to a low on-state voltage (VON) approaching the SiC trench-gate IGBT. The strong injection enhancement effect is obtained by a heavily doped carrier storage layer (CSL), which creates a hole barrier under the p-body to hinder minority carriers from being extracted away through the p-body. A p-shield is located at the bottom of the CSL and coupled to the p-body of the IGBT by an embedded p-MOSFET (metal-oxide-semiconductor field effect transistors). In off-state, the heavily doped CSL is shielded by the p-MOSFET clamped p-shield. Thus, a high breakdown voltage is maintained. At the same time, owing to the planar-gate structure, the proposed IGBT does not suffer the high oxide field that threatens the long-term reliability of the trench-gate IGBT. The turn-off characteristics of the new IGBT are also studied, and the turn-off energy loss (EOFF) is similar to the conventional planar-gate IGBT. Therefore, the new IGBT achieves the benefits of both the conventional planar-gate IGBT and the trench-gate IGBT, i.e., a superior VON-EOFF trade-off and a low oxide field.

Exploring SiC Planar IGBTs towards Enhanced Conductivity Modulation Comparable to SiC Trench IGBTs

The state-of-the-art silicon insulated-gate bipolar transistor (IGBT) features a trench gate, since it enhances the conductivity modulation. The SiC trench IGBT, however, faces the critical challenge of a high electric field in the gate oxide, which is a crucial threat to the device’s reliability. In this work, we explore the possibility of using a SiC planar IGBT structure to approach high performance to the level of a SiC trench IGBT, without suffering the high gate oxide field. The proposed SiC planar IGBT features buried p-layers directly under the p-bodies, and thus can be formed using the same mask set. The region between the buried p-layer and the p-body is heavily doped with n-type dopants so that the conductivity modulation is improved. Comprehensive TCAD simulations have been carried out to verify this concept, and the simulation results show the new SiC planar IGBT exhibits a high performance comparable to the trench IGBT, and also exhibits a low gate oxide field.

SiC trench MOSFET with self‐biased p‐shield for low R ON‐SP and low OFF‐state oxide field

A SiC trench metal-oxide-semiconductor field-effect transistor (MOSFET) with a self-biased p-shield (SBS-MOS) is proposed and comprehensively studied. The p-shield region is used to reduce the high oxide field at the OFF-state, which would otherwise be detrimental to the device long-term reliability. A self-biasing network is designed to raise the potential of the p-shield in the SBS-MOS, so that the parasitic junction field effect transistor (JFET) is driven synchronously with the MOS-gate. Mixed-mode numerical simulations are carried out to study the performance of the proposed device. The SBS-MOS boasts a reduced specific ON-resistance ( R ON-SP ) compared with the trench MOSFET with a grounded p-shield (GS-MOS), by the reduction of the JFET resistance and/or further down-scaling of the cell size. To synchronously drive the JFET region, only a slightly larger gate charge is required for the SBS-MOS. Therefore, a low OFF-state oxide field, a low R ON-SP and a low Q GD are simultaneously achieved in the proposed SBS-MOS.

A New SiC Trench MOSFET Structure With Protruded p-Base for Low Oxide Field and Enhanced Switching Performance

The high OFF-state oxide field in the SiC trench MOSFET is a threat for its long term reliability, and thus hinders the wide acceptance of the SiC trench MOSFETs. In this paper, an SiC trench MOSFET with protruded p-bases (PB-MOS) is proposed, which features protruded p-bases to shield the gate oxide at the trench bottom against the high OFF-state drain voltage. Numerical device simulations based on Sentaurus TCAD verify the benefits of the structure. The OFF-state oxide field ( ${ {E}}_{\text {ox-m}}$ ) in the PB-MOS is 1.7 MV/cm, which is dramatically lower compared to the high ${ {E}}_{\text {ox-m}}$ of 8.6 MV/cm in the conventional trench MOSFET (C-MOS). The above benefit is achieved without sacrificing device performances. The reverse transfer capacitance ( ${ {C}}_{\text{rss}}$ ) of the PB-MOS is around ten times lower than that in the C-MOS. Both the gate charge ( ${ {Q}}_{\text{G}}$ ) and the gate-to-drain charge ( ${ {Q}}_{\text{GD}}$ ) of the PB-MOS are significantly improved compared to the C-MOS. A low specific ON-resistance ( ${ {R}}_{\text{ON}}$ ) is maintained in the PB-MOS by using additional JFET doping to compensate the JFET effect. As a result, the PB-MOS presents much better figures of merit ${ {Q}}_{\text{G}} \cdot { {R}}_{\text{ON}}$ and ${ {Q}}_{\text{GD}} \cdot { {R}}_{\text{ON}}$ than those of the C-MOS. The PB-MOS achieves a much faster switching speed than the C-MOS, and consequently exhibits an appreciable reduction in the switching energy loss.

1200 V SiC IE-UMOSFET with Low On-Resistance and High Threshold Voltage

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.

On the Evolution of Switching Oxide Traps in the HfO2/TiN Gate Stack Subjected to Positive- and Negative-Bias Temperature Stressing

In this paper, evolution of switching oxide traps (SOTs) in the HfO2/TiN gate stack is examined under positive- and negative-bias temperature (PBT and NBT, respectively) stress. Charging and discharging of SOTs were sensed by repetitive stress/ relaxation cycling and the discharging of SOTs was quantified based on the extent of the threshold voltage shift recovery after a fixed relaxation interval. For both the PBT and NBT stress at a low oxide field (~5.5 MV/cm), the quantity of SOTs discharged is observed to be approximately constant, independent of the number of stress/relaxation cycles. At a higher oxide stress field (~7 MV/cm), however, the quantity of SOTs discharged is seen to decrease progressively with the number of stress/relaxation cycles. This observation implies that a part of the SOTs which can be discharged in earlier relaxation phases is no longer able to do so as the stress progresses. The reduction in recovery points to an increase of the emission times of the trapped charge arising probably from structural changes at the oxide defect sites. Although the evolution of SOTs under both stresses is broadly similar, differences are observed from the opposite gate-polarity relaxation study and stress-induced leakage current measurement. First-principles simulation shows that a defect model based on the oxygen vacancy alone could not explain the differences observed. An extended model involving both the oxygen vacancy and vacancy-interstitial defects is shown to be able to explain the similarities as well as differences observed under PBT and NBT stresses.

POCl3 Annealing as a New Method for Improving 4H-SiC MOS Device Performance

Effects of POCl3 annealing on the electrical properties of metal-oxide-semiconductor (MOS) devices on 4H-SiC were investigated. Comparative results of non-annealed, NO-annealed, and POCl3-annealed MOS devices are shown. POCl3 annealing is more effective to reduce interface state density and improve channel mobility than conventional NO annealing. Breakdown characteristics and reliability of annealed oxides were also investigated. POCl3 annealing did not deteriorate oxide breakdown field very much. Time-dependent dielectric breakdown characteristics indicated different behavior due to enhanced electron trapping in the oxide. It is related with uniformly distributed phosphorus in the oxide. Flat-band voltage shift due to interface traps and near-interface traps in the oxide was very small at low oxide fields (< 3 MV/cm), whereas injected electrons were easily trapped in the POCl3 annealed oxide at high oxide fields (> 5 MV/cm). By combination of NO and POCl3 annealing, relatively high channel mobility and stabilized characteristics against electron injection were achieved.

High Performance Metal-Insulator-Metal Capacitors with Er2O3 on ALD SiO2 for RF Applications

MIM capacitors for RF applications with sputtered Er2O3 on ALD SiO2 stacked dielectrics with excellent capacitance performance were demonstrated for the first time. An MIM capacitor with 8.8 nm Er2O3 on 3 nm SiO2 stacked dielectrics displayed a high capacitance density of 7 fF/μm2, a low quadratic VCC of less than 100 ppm/V2, a low leakage current at 3.3 V bias of 1 × 10−8 A/cm2, and a high dielectric field strength of 8.7 MV/cm. Having leakage currents of 1 × 10−7 and 4 × 10−8 A/cm2 at 3.3 and 2 V, respectively, the MIM capacitor with 7 nm Er2O3 on 3 nm SiO2 stacked dielectrics demonstrated a capacitance density of 7.4 fF/μm2 and quadratic VCCs of −91 and −255 ppm/V2 at 10 and 100 kHz, respectively. The low quadratic VCC α was obtained by compensating the positive α of Er2O3 with the negative α of SiO2, while the low leakage current and high oxide field strength demonstrated were due to the high quality SiO2 deposited by the ALD method.

Study of the Effects of the Antisite Related Defects in Silicon Dioxide of Metal-Oxide-Semiconductor Structure on the Gate Leakage Current

The effects of the antisite related defects on the electronic structure of silica and the gate leakage current have been investigated using first-principles calculations. Energy levels related to the antisite defects in silicon dioxide have been introduced into the bandgap, which are nearly 2.0 eV from the top of the valence band. Combining with the electronic structures calculated from first-principles simulations, tunneling currents through the silica layer with antisite defects have been calculated. The tunneling current calculations show that the hole tunneling currents assisted by the antisite defects will be dominant at low oxide field whereas the electron direct tunneling current will be dominant at high oxide field. With increased thickness of the defect layer, the threshold point where the hole tunneling current assisted by antisite defects in silica is equal to the electron direct tunneling current extends to higher oxide field.

Comparative study of NBTI as a function of Si film orientation and thickness in SOI pMOSFETs

Negative bias temperature instability of SOI pMOSFET is investigated as a function of Si film orientation and film thickness. It is observed that NBTI induced threshold voltage shift is bigger for (1 1 0) MOSFETs in comparison to (1 0 0) MOSFETs and it decreases with the decrease of Si film thickness. The possible reason for less degradation of thinner Si film devices is explained by the small gate current due to low oxide field. The activation energy is independent on Si film orientation. The dependence of recovery behavior on the Si film orientation is studied by comparing of a conventional stress-measurement-stress technique with un-interrupted stress technique. It is also observed that the NBTI effect is underestimated and the recovery phenomenon is more profound in (1 1 0) MOSFETs.

First-principles study of the effects of oxygen vacancy on hole tunneling current

The effects of oxygen vacancies on the electronic structure of silicon dioxide and the hole tunneling current were investigated using first-principles calculations. A level related to oxygen vacancy was obtained to be nearly 2.0 eV from the top of valence band within the bandgap of the α-quartz supercell with one oxygen vacancy. And therefore the defect assisted hole (electron) tunneling currents were calculated. The results shows that the hole tunneling current will be dominant for a thinner oxide thickness at low oxide field and the contribution of trap assisted hole tunneling to the total tunneling current decreases with oxide thickness and oxide field increasing. It is concluded that the effects of the oxygen vacancies on the hole tunneling current become smaller with larger oxide thickness and higher electric field.

Tunneling currents through lightly nitride silicon dioxide/oxide stacks

AbstractOxynitride has been used to decrease leakage current of thin film SiO2. Combining with the band structures obtained from first‐principles simulations, tunneling currents through SiO2/silicon oxynitride stacks were calculated. SiO2/silicon oxynitride stacks can reduce leakage current at low oxide field but will fail at higher field. The threshold oxide field, which means that SiO2/silicon oxynitride stacks can not reduce the tunneling current when oxide field is higher than it, decreases with increased nitrogen concentration while the effective oxide thickness remains constant. Direct tunneling and defect‐assisted tunneling will be dominant for lower and higher nitrogen atom concentrations, respectively. (© 2007 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Analysis of variation in leakage currents of Lanthana thin films

Lanthana (La 2O 3) films were deposited by E-beam evaporation on n-Si(1 0 0). Conduction mechanisms for the as-deposited film have been investigated. In order to study the annealing effect of the as-deposited films on the conduction mechanisms, some films were annealed in an ex situ way at different temperatures with nitrogen or oxygen gas flow for 5 min. From current–voltage measurement of the as-deposited films, extremely low gate oxide leakage currents were observed while some films showed variation in the scale of the currents. It is shown that all the currents of as-deposited films obey the same conduction mechanisms irrelevant of the magnitude of the leakage currents. From the electric field and temperature dependences of the currents of the gate oxide, it is shown that the main conduction mechanisms are the space-charge limited current (SCLC) at low oxide field region and Fowler–Nordheim (F–N) conduction at high oxide field region. It is also shown that conduction mechanisms of the nitrogen annealed films were basically the same as those of the as-deposited films although the magnitude of the conduction current and flat-band voltage ( V FB) are different.

Characterization of hot-hole injection induced SILC and related disturbs in flash memories

In this paper, we have proposed a new method for the study of disturb failure mechanisms caused by stress induced leakage current (SILC) in source-side erased flash memories. This method is able to directly separate the individual components of SILC due to either carrier charging/discharging in the oxide or the positive charge/trap assisted electron tunneling into the floating gate. In addition, the present method is very sensitive with capability of measuring ultralow current (<10/sup -19/ A). Results show that, at low oxide field, the disturb is mainly contributed by the so-called charging/discharging of carriers into/from the oxide due to the capacitance coupling effect. While at high oxide field, the positive charge/trap assisted electron tunneling induced floating-gate charge variation is the major cause of disturb failure.

Modeling of SILC based on electron and hole tunneling. II. Steady-state

For pt. I see ibid., vol. 47, no. 6 (June 2000). A numerical model for the stationary stress-induced leakage current (SILC) is presented, accounting for both electron and hole tunneling. Detailed comparisons against experimental results on both n- and p-channel devices highlight that the steady-state SILC is due to positively charged centers, with an energy level located in correspondence of the silicon bandgap. Electron-hole recombination at these sites dominates normal trap-assisted tunneling at low oxide fields, and successfully accounts for recently observed hole steady-state leakage. The contribution from neutral traps seems instead marginal. Based on this new picture, the impact of the recombination process on the leakage properties of ultrathin gate is also discussed.

Origin of positive charge generated in thin SiO/sub 2/ films during high-field electrical stress

The characteristics of electron capture in a 131-/spl Aring/ silicon dioxide after hot-hole injection have been studied, which have been compared with those after high-field Fowler-Nordheim (FN) electron injection. After hole injection from the silicon substrate into the oxide, positive charges accumulated in the oxide and electrons could be captured even at low oxide fields only under the positive gate polarity. The charge centroid of the captured electrons was near the substrate-SiO/sub 2/ interface. The low-field electron capture can be explained based on the electron tunneling from the substrate into the positive charge and neutral trap centers created near the substrate-SiO/sub 2/ interface. In order to investigate the initial stage of the oxide degradation due to high-field FN stress, electrons were injected from the gate and the charge fluence was selected to be -1.0 C/cm/sup 2/. After the high-field stress, positive charges appeared in the oxide and electrons were captured only under the positive gate polarity by the positive charge and neutral trap centers, which were distributed near the interface. These facts are explained on the basis of the model describing that hole injection and trapping are the dominant causes for the generation of the positive charge centers during high-field FN stress.

Study of MOS gate dielectric breakdown due to drain avalanche breakdown

This work reports the effects of drain impact ionization injection on the gate dielectric breakdown. Results show that due to the high energy hot carrier injection, the gate oxide can break down twice at a low oxide electric field (<1.2 MV/cm). The first breakdown occurs simultaneously with the drain avalanche breakdown whereas the second breakdown occurs beyond the drain breakdown. It is further identified that the first gate oxide breakdown is governed by the thermionic emission of hot electrons at low oxide fields (<1.0 MV/cm) and by the scattering processes at higher oxide fields. The second breakdown is attributed to the Fowler–Nordheim (F–N) tunneling.