Low Off-currents Research Articles

Germanium FETs and capacitors with rare earth CeO 2/HfO 2 gates

Long channel Ge FETs and capacitors with CeO 2/HfO 2/TiN gates were fabricated by photolithography and gate wet etch. Rare earth CeO 2 in direct contact with Ge was used as a passivating layer producing lowest D it values in the mid 10 11 eV −1 cm −2 range. HfO 2 cap reduces leakage and improves equivalent oxide thickness scaling of the whole gate stack. The p-FETs show exceptionally high I ON/ I OFF ratio ∼10 6, mainly due to low OFF current, and peak channel mobility around 80 cm 2/V s. The n-FETs, although functional, show inferior performance producing ON currents an order of magnitude lower compared to p-FETs.

Improvements in the Device Characteristics of Polycrystalline Silicon Thin-Film Transistors on Stainless Steel by UV Treatment

A significant improvement in device performance was observed for polycrystalline Si thin-film transistors (poly-Si TFTs) on stainless steel foil subjected to UV treatment prior to the deposition of the buffer layer and gate dielectric film of . This is presumably due to the reduction of the trap-state density in the poly-Si film and at the gate dielectric/poly-Si interface caused by the removal of the organic contamination, which might be induced during the planarization of the rough stainless steel. An excellent subthreshold gate swing of , low threshold voltage of , and very low off-current of , as well as a high field-effect mobility of , were achieved for the p-channel poly-Si TFTs on stainless steel. Thus, it is concluded that poly-Si TFTs on stainless steel can be comparable to those on a conventional glass substrate in terms of their overall device performance, including , , and the off-current.

Room temperature pulsed laser deposited indium gallium zinc oxide channel based transparent thin film transistors

Indium gallium zinc oxide deposited by pulsed laser deposition at room temperature was used as a channel layer to fabricate transparent thin film transistors with good electrical characteristics: field effect mobility of 11cm2V−1s−1 and subthreshold voltage swing of 0.20V∕decade. By varying the oxygen partial pressure during deposition the conductivity of the channel was controlled to give a low off-current of ∼10pA and a drain current on/off ratio of ∼5×107. Changing the channel layer thickness was a viable way to vary the threshold voltage. The effect of the gate dielectric on the electrical behavior was also explored.

Silicon p-FETs from Ultrahigh Density Nanowire Arrays

Statistical numbers of field-effect transistors (FETs) were fabricated from a circuit of 17-nm-wide, 34-nm-pitch Si nanowires boron doped at a level of 10(18) cm-3. Top-gated 4-microm-wide Si nanowire p-FETs yielded low off-currents (approximately 10(-12) A), high on/off ratios (10(5)-10(6)), good on current values (30 microA/microm), high mobilities (approximately 100 cm2/V-s), and low subthreshold swing values (approximately 80 mV/decade between 10(-12) and 10(-10) A increasing to 200 mV/decade between 10(-10)-10(-8) A).

Pushing CMOS beyond the roadmap

Today, the 90 nm generation is in production and in spite of many roadblocks, the latest ITRS 04 expects that CMOS can be scaled down to the 22 nm node and beyond. However, for conventional bulk CMOS serious challenges are evident and new transistors with better electrostatic channel control, lower off-currents and higher on-currents will be needed. Among them, multi-gate devices with very thin silicon channels are most promising. Several architectures like FinFET, Wafer Bonded Double Gate and SON Gate All Around have been demonstrated with good electrical characteristics at gate lengths of 25–10 nm. Under certain assumptions for the SD regions, quantum mechanical simulations predict that silicon MOSFETs can be functional down to 2 nm gate length. Multi-gate transistors have also been implemented in high density Flash memory cells down to 20 nm. Large V t shifts suitable for multi-level storage were achieved. Therefore, it seems very realistic that the device roadmap will not end at the 22 nm node. Assuming that manufacturing and cost issues can be fulfilled, CMOS will continue to dominate in the nanoelectronics era.

Scaling the Vertical Tunnel FET With Tunnel Bandgap Modulation and Gate Workfunction Engineering

In this paper, we look into the scaling issues of a vertical tunnel field-effect transistor (FET). The device, a gated p-i-n diode based on silicon, showed gate-controlled band-to-band tunneling from the heavily doped source to the intrinsic channel. An exponentially increasing input characteristics, perfect saturation in the output characteristics, and off-currents of the order of 1 fA//spl mu/m for sub-100-nm channel lengths were observed. Further, with a /spl delta/p/sup +/ SiGe layer at the p-source end, improvements in the device performance in terms of on-current, threshold voltage and subthreshold swing were shown, albeit trading off the off-currents which increase with Ge content x. We show here that the tunnel FET performance is nearly independent of channel length scaling L and with /spl delta/p/sup +/ SiGe layer, scaling t/sub ox/ is not critical to tunnel FET scaling. Further, with gate workfunction engineering, the tunnel FET can be tuned to achieve a high on-current as well as very low off-currents. Due to the perfect saturation in the output characteristics, the device looks good for sub-100-nm low-power analog devices.

High ON/OFF ratio and stability of amorphous organic field-effect transistors based on spiro-linked compounds

We report high ON/OFF ratios for organic field-effect transistors (OFETs) based on amorphous thin films of spiro-linked compounds. Bottom-contact OFET structures are fabricated, using 2,2′,7,7′-tetra-( m-tolyl-phenylamino)-9,9′-spirobifluorene (Spiro-TPD) and 2,2′,7,7′-tetrakis-(diphenylamino)-9,9′-spirobifluorene (Spiro-TAD) as active materials. The field-effect mobility of holes in Spiro-TPD and Spiro-TAD thin films is 7 × 10 −5 cm 2/Vs. We obtained ON/OFF ratios up to 3.6 × 10 6 with low OFF currents in the pA range. Time-dependent measurements show that the transistor characteristics do not change significantly over 9 months.

Carbon Nanotube Field-Effect Transistors with Integrated Ohmic Contacts and High-κ Gate Dielectrics

High-performance enhancement-mode semiconducting carbon nanotube field-effect transistors (CNTFETs) are obtained by combining ohmic metal−tube contacts, high-dielectric-constant HfO2 films as gate insulators, and electrostatically doped nanotube segments as source/drain electrodes. The combination of these elements affords high ON currents and subthreshold swings of ∼70−80 mV/decade and allows for low OFF currents and suppressed ambipolar conduction. The doped source and drain approach resembles that of MOSFETs and can impart excellent OFF states to nanotube FETs under aggressive vertical scaling. This presents an important advantage over devices with a metal source/drain, or devices commonly referred to as Schottky barrier FETs.

Performance Improvement of Excimer Laser Annealed Poly-Si TFTs Using Fluorine Ion Implantation

Significant improvement of device performance was observed for the excimer laser annealed (ELA) poly-Si thin film transistors (TFTs) by the incorporation of fluorine atoms using the ion implantation technique. This is presumably due to the relaxation of mechanical stress at the poly-Si/buffer-oxide interface and the passivation of trap-states in the poly-Si channel region and at the gate-oxide/poly-Si interface. We achieved high performance ELA poly-Si TFTs with a very low off-current of ∼0.26 pA/μm and a very high On/Off current ratio of about 10 8 . Moreover, the fluorine ion implantation also greatly improved the reliability of the ELA poly-Si TFTs with respect to the hot-carrier stress, presumably due to the formation of strong Si-F bonds.

A read-disturb-free ferroelectric gate fet memory

The enhancement-type ferroelectric gate field-effect transistor (FeFET) requires a read biasing voltage to the gate to secure a sufficient on/off current ratio. However, disturb (depolarization) of the ferroelectric by repetitive applications of read biasing voltage to the gate is a potential reliability concern. This paper deals with the disturb issue for an experimentally fabricated FeFET with a stacked gate comprised of metal/SrBi2Ta2O9/CeO2. A significant difference between a high ON current and a low OFF current is brought about and sustained after a large number of read operations by choosing a proper gate voltage, which is not only enough to make a positively programmed FeFET turn on, but also effective to prevent the disturb effect.

A Novel Four Terminal Poly-Si Tft Suppressing Kink and Improving Reliability

ABSTRACTWe fabricated a new device, which employs counter-doped lateral body terminal (CLBT) in order to suppress kink effects and improve the device stability. Proposed device also employs a buried channel (BC), which increases ON-current and operating frequency. Although LDD structure is not employed in the proposed device, low OFF-current is successfully obtained due to elimination of minority carrier through CLBT. We have measured the dynamic properties of poly-Si TFT device and circuit. The reliability of TFT and circuits after AC stress is also discussed in our paper.The proposed poly-Si TFT has high ON-current and low OFF-current compared with conventional 3-terminal poly-Si TFT. The 4-terminal device characteristics were measured with source and CLBT shorted. The proposed device exhibits superior performance to conventional device in ON-current because BC prevents carrier scattering to gate oxide. We have performed bias and high temperature stress test of ring oscillator in order to investigate dynamic reliability between conventional poly-Si TFT and proposed 4-terminal poly-Si TFT. Our experimental results show that BC enables the device to have high mobility and switching frequency (33MHz at VDD=15V). The minority carrier elimination of CLBT suppresses kink effects and makes superb dynamic reliability of CMOS circuit.