Low-overhead Design Research Articles

CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency

Conventional security systems incur considerable computational resources, which become a significant hindrance for resource constraints internet of things (IoT) and wireless sensor network applications. Downsizing the existing security processes necessitates demand for lightweight cryptography for a secure system. The Physically Unclonable Function (PUF) extracts the uncontrollable randomness in the physical variation of integrated circuits (ICs). It is now proven to be promising security primitive for many hardware security applications, including authentication and anti-counterfeiting. The Arbiter PUF (APUF) provides a viable solution with minimal design overhead. This work proposes a new PUF variant, the Configurable Circular Arbiter PUF (CAPUF), for hardware security applications. In the CAPUF, the position of switches in an APUF are selectively altered to amalgam non-linearity and Strict Avalanche Criterion (SAC) properties, which enhances its security at low design overhead. An important feature of the CAPUF is that it is configurable, and this flexibility gives it a considerable advantage over many existing PUF variants. Simulation results and statistical analyses establish that the CAPUF outperforms the existing APUF variants through a combination of cost-effective architecture, SAC property, adequate modeling robustness, and the trade-off between security and hardware overhead.

A low-overhead PUF for anti-clone attack of RFID tags

Physically Unclonable Function (PUF) is one of the important research techniques for anti-cloning attacks in Radio Frequency Identification (RFID) tags security. But in RFID tags, there are not quite a few resources left for PUF. Therefore, this paper designs a new lightweight reconfigurable XOR RO PUF, which can simultaneously switch the internal delay of each inverter and the number of ring oscillator stages, increase the delay complexity with less hardware overhead, and generate more multiple authentication keys. In this paper, the proposed PUF circuit design is verified and good performance indicators are obtained. By comparison with the existing PUF low-overhead design, this design has more challenge/response pairs (CRPs) and less hardware overhead without reducing the uniformity, randomness, uniqueness and reliability of the PUF.

Analysis and Optimization for Large-Scale LoRa Networks: Throughput Fairness and Scalability

LoRa networks are pivotally enabling Long Range connectivity to low-cost and power-constrained user equipments (UEs) in a wide area, whereas a critical issue is to effectively allocate wireless resources to support potentially massive UEs while resolving the prominent near–far fairness issue, which is challenging due to the lack of tractable analytical model and the practical requirement for low-complexity and low-overhead design. Leveraging on stochastic geometry, especially the Poisson rain model, we derive (semi-) closed-form formulas for the aggregate interference distribution, packet success probability, and hence, system throughput in both single-cell and multicell setups with frequency reuse, by accounting for channel fading, random UE distribution, partial packet overlapping, and/or multi-gateway (GW) packet reception. The analytical formulas require only average channel statistics and spatial UE distribution, which enable tractable network performance evaluation and incubate our proposed iterative balancing (IB) method that quickly yields high-level policies of joint spreading factor (SF) allocation, power control, and duty-cycle adjustment for gauging the average max–min UE throughput or supported UE density with rate requirements. Numerical results validate the analytical formulas and the effectiveness of our proposed optimization scheme, which greatly alleviate the near–far fairness issue and reduces the spatial power consumption, while significantly improving the cell-edge throughput as well as the spatial (sum) throughput for the majority of UEs, by adapting to the UE/GW densities.

CONCEALING-Gate: Optical Contactless Probing Resilient Design

Optical probing, though developed as silicon debugging tools from the chip backside, has shown its capability of extracting secret data, such as cryptographic keys and user identifications, from modern system-on-chip devices. Existing optical probing countermeasures are based on detecting any device modification attempt or abrupt change in operating conditions during asset extraction. These countermeasures usually require additional fabrication steps and cause area and power overheads. In this article, we propose a novel low-overhead design methodology to prevent optical probing. It leverages additional operational logic gates, termed as “CONCEALING-Gates,” inserted as neighbor gates of the logic gates connected to the nets carrying asset signals. The switching activity of the asset carrying logic is camouflaged with the switching activity of the concealing-gate. The input signal and placement in the layout of the concealing-gates must be selected in such a way that they remain equally effective in preventing different variants of optical probing, i.e., electro-optical frequency mapping and Electro-optical probing. The methodology is suitable for the existing ASIC/FPGA design flow and fabrication process, since designing new standard logic cells is not required. We have performed a comprehensive security evaluation of the concealing-gates using a security metric developed based on the parameters that are crucial for optical probing. The attack resiliency of the logic cells, protected by concealing-gates, is evaluated using an empirical study-based simulation methodology and experimental validation. Our analysis has shown that in the presence of concealing-gates, logic cells achieve high resiliency against optical contactless probing techniques.

Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems

This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps.

An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Droplet Barcoding in Single-Cell Analysis

Single-cell analysis is used to gain insights into diseases, such as cancer. Advances in microfluidic solutions have enabled the efficient classification and analysis of a heterogeneous population of cells. Recently, a hybrid microfluidic platform was proposed for concurrent single-cell analysis on thousands of heterogeneous cells. In this design, barcoding droplets are routed using a valve-based routing fabric to label the input cells. However, prior work overlooked defects that are likely to occur during chip fabrication and system integration and the fault tolerance of this routing fabric remains a major concern. We address the above limitation and introduce a low-overhead design technique for guaranteeing the tolerance of single faults, while maintaining the efficiency of the cell-analysis platform. We show that the proposed method is optimal in that it minimizes the overhead in terms of fabric size.

End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs

Solutions to the integration challenges of a new thermal sensor technology into 3-D integrated circuits (ICs) will be discussed in this paper. Our proposed architecture uses bimetallic thin-film thermocouples, which are thermally linked to points of measurement throughout the 3-D stack with dedicated vias. These vias will be similar to thermal through-silicon vias (TSVs) in structure, yet different in functionality. We propose a low-overhead design methodology by linking the sensor placement task with the existing thermal TSV planning phase for 3-D ICs. A fraction of thermal TSV resources is decoupled from their original use and repurposed for the temperature sensing infrastructure. Tradeoffs concerning the reduction of the thermal TSV resources are investigated. Furthermore, we present an end-to-end system, including the physical realization of the sensor network as well as its analog interface circuitry with the sensor data sampling unit. We demonstrate the operation and correctness of this interface with transistor-level simulations. Next, through thermal modeling and simulation using a state-of-the-art tool (FloTHERM), we demonstrate that we can achieve high accuracy (1 °C error) in temperature tracking while still maintaining the effectiveness of the thermal TSVs in heat management (conforming to a peak temperature constraint of 95 °C).

Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis

Intellectual Property (IP) core used in computing system-on-chip provides a unique blend of yielding enhanced design productivity with reduced design cycle time. However, leveraging benefits of IP core require protection against threats from both seller’s and buyer’s perspective. This paper proposes a novel symmetrical IP core protection methodology that embeds a buyer fingerprint and seller watermark simultaneously during high level synthesis (HLS). The proposed work leverages major HLS steps to concurrently embed buyer fingerprint signature and seller watermark signature into a reusable IP core design. The proposed signature encoding for fingerprint and watermark is multi-variable in nature offering strong robustness, low embedding cost and low design overhead. Results on standard benchmarks indicated that the proposed symmetrical approach satisfies all the major protection features of a watermark and fingerprint such as strong robustness to both seller & buyer, low overhead, low runtime and low embedding cost. Further on comparison with baseline design (no protection), the proposed approach offers symmetrical protection (both buyer and seller) at less than 1% area overhead and less than 1.1% latency overhead. Additionally on comparison with a recent unsymmetrical approach, the proposed approach offers symmetrical protection (both buyer and seller) at 0% area overhead and less than 1.1% latency overhead.

OFDM Multitone Signal Generation Technique for Analog Circuitry Test Characterization

Multitone test is an effective technique in many wideband circuit test applications. However, the traditional multitone test signal generation methods are complex and/or time consuming. In this brief, a new approach utilizing orthogonal frequency-division multiplexing technique is developed, which can effectively produce multiple frequency tones concurrently with fine resolution and low design overhead. For validation, filter test characterizations are performed and demonstrated.

Compressive Sampling Coupled OFDM Technique for Testing Continuous Wave Radar

Testing continuous wave (CW) radar circuitry is a challenging and time consuming process that requires characterizing system response over a wide range of frequencies. Step frequency continuous wave (SFCW) functional test is widely adopted for CW radar through a large number of frequency tones generation and characterization. For an ultra-wideband radar system, SFCW testing can be very time consuming. In this paper, we propose a new approach to increase test speed at low cost and low design overhead by combining OFDM (Orthogonal Frequency Division Multiplexing) in conjunction with compressive sampling (CS) algorithm. In the test, OFDM is applied for multi-tone signal generation while compressive sampling is for frequency tone reduction. To show equivalent test performance, SFCW test and OFDM-CS test are both performed to characterize a sample ground penetrating radar (GPR). Simulation results are presented for validations.

One-Hop Neighbor Based Broadcast Scheduling in Wireless Sensor Networks

SUMMARY For wireless sensor networks in which resources are limited and network topology dynamically changes, we propose the one-hop neighbor based broadcast scheduling (ONBS) algorithm to provide reliable delivery service of broadcast packets. The proposed algorithm reduces the scheduling overhead by allowing each joining node to decide its broadcast schedule based on only its one-hop neighbor information in an on-line and distributed manner. Also, once the broadcast schedule is decided, it is not changed to accommodate a newly joining node in order to prevent the consecutive changes of existing schedules. The network simulation results show that the proposed algorithm provides low latency and high reachability despite low overhead and on-line algorithm design.

Low-overhead F max calibration at multiple operating points using delay-sensitivity-based path selection

Maximum operating frequency ( F max ) of a system often needs to be determined at multiple operating points, defined by voltage and temperatures. Such calibration is important for the speed binning process, where the voltage-frequency (V- F max ) relation needs to be accurately determined to sort chips into different bins that can be used for different applications. Moreover, adaptive systems typically require F max calibration at multiple operating points in order to dynamically change operating condition such as supply voltage or body bias for power, temperature, or throughput management. For example, a Dynamic Voltage and Frequency Scaling (DVFS) system requires accurate delay calibration at multiple operating voltages in order to apply the correct operating frequency corresponding to a scaled supply. In this article, we propose a low-overhead design technique that allows efficient characterization of F max at different operating voltages and temperatures. The proposed method selects a set of representative timing paths in a circuit based on their temperature and voltage sensitivities and dynamically configures them into a ring oscillator to compute the critical path delay. Compared to existing F max calibration approaches, the proposed approach provides the following two main advantages: (1) it introduces a delay sensitivity metric to isolate few representative timing paths; (2) it considers actual timing paths instead of critical path replicas, thereby accounting for local within-die delay variations. The all-digital calibration method is robust under process variations and achieves high delay estimation accuracy (> 4% error) at the cost of negligible design overhead (1.7% in delay, 0.3% in power, and 3.5% in die-area).

Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput

Within-die parameter variations can cause wide delay distribution among similar functional units in superscalar processors. Conventionally, the frequency of operation is reduced to accommodate the slowest unit, which in turn degrades throughput. We present a low-overhead design technique that sets the operating frequency in a superscalar processor based on the faster units and allows more cycles for the slower units. We propose an associated priority scheduling strategy to schedule instructions in the functional units to maximize throughput. Simulation results on a set of benchmarks show that, by assigning a higher scheduling priority to faster units, we can achieve 18 percent improvement in performance on average with negligible design overhead.

Publicly detectable watermarking for intellectual property authentication in VLSI design

Highlighted with the newly released intellectual property (IP) protection white paper by VSI Alliance, the protection of virtual components or IPs in very large scale integration (VLSI) design has received a great deal of attention recently. Digital signature/watermark is one of the most promising solutions among the known protection mechanisms. It provides desirable proof of authorship without rendering the IP useless. However, it makes the watermark detection, which is as important as watermarking, an NP-hard problem. In fact, the tradeoff between hard-to-attack and easy-to-detect and the lack of efficient detection schemes are the major obstacles for digital signatures to thrive. In this paper, the authors propose a new watermarking method which allows the watermark to be publicly detected without losing its strength and security. The basic idea is to create a cryptographically strong pseudo-random watermark, embed it into the original problem as a special (which the authors call mutual exclusive) constraint, and make it public. The authors combine data-integrity technique and the unique characteristics in the design of VLSI IPs such that adversaries will not gain any advantage from the public watermarking for forgery. This new technique is compatible with the existing constraint-based watermarking/fingerprinting techniques. The resulting public-private watermark maintains the strength of a watermark and provides easy detectability with little design overhead. The authors build the mathematical framework for this approach based on the concept of mutual exclusive constraints. They use popular VLSI CAD problems, namely technology mapping, partitioning, graph coloring, FPGA design, and Boolean satisfiability, to demonstrate the public watermark's easy detectability, high credibility, low design overhead, and robustness.

A low overhead design for testability and test generation technique for core-based systems-on-a-chip

In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult, mainly due to the problem of justifying test sequences at the inputs of a core embedded deep in the circuit and propagating test responses from the core outputs. In this paper, we first present a design for testability technique for testing such core-based systems. In this scheme, untestable cores are first made testable using hierarchical testability analysis techniques. If necessary, additional testability hardware is added to the cores to make them transparent so that they can propagate test data without information loss. This testability and transparency technique is currently applicable to cores of the following types: application-specific integrated circuits, application-specific programmable processors, and application-specific instruction processors. Other core types can be made testable and transparent using traditional techniques. The testable and transparent cores can then he integrated together with some system-level testability hardware to ensure justification of precomputed test sequences of each core from system primary inputs to the core inputs and propagation of test responses from core outputs to system primary outputs. Justification and propagation of test sequences are done at the system level by extending and suitably modifying the symbolic hierarchical testability analysis method that has been successfully applied to register-transfer level circuits. Since the testability analysis method is symbolic, the system test generation method is independent of the bit-width of the cores. The system-level test set is obtained as a byproduct of the testability analysis and insertion method without further search. The test methodology was applied to six example systems. Besides the proposed test method, the two methods that are currently used in the industry were also evaluated: (1) FScan-BScan, where each core is full-scanned, and system test is performed using boundary scan and (2) FScan-TBus, where each core is full-scanned, and system test is performed using a test bus. The experiments show that the proposed scheme has significantly lower area overhead, delay overhead, and test application time compared to FScan-BScan and FScan-TBus, without any compromise in the system fault coverage.

Cost-free scan: a low-overhead scan path design

Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design. However, the functionality of the functional logic has not been utilized for the test purposes. We propose a low-overhead scan design methodology, called cost-free scan, which exploits the controllability of primary inputs to establish scan paths through the functional logic. We show how to analyze the circuit to determine all the free-scan flip-flops and select the best input vector to establish the maximum number of free-scan flip-flops for the scan chain design. Significant reduction in the scan overhead is achieved on ISCAS89 benchmarks. In full-scan designs, as many as 89% of the flip-flops are found free-scannable. In the partial-scan designs, we assume that selecting flip-flops for scan to break sequential cycles is used to increase circuit testability. Reduction can be as high as 97% in scan flip-flops needed to break sequential cycles.

Test-point insertion: scan paths through functional logic

Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design. We propose a low-overhead scan design methodology that employs a new test-point insertion technique. Unlike the conventional test-point insertion, where test points are used directly to increase the controllability and observability of the selected signals, the test points are used here to establish scan paths through the functional logic. The proposed technique reuses the functional logic for scan operations; as a result, the design-for-testability overhead on area or timing can be minimized. We show an algorithm that uses the new test-point insertion technique to reduce the area overhead for the full-scan design. We also discuss its application to the timing-driven partial-scan design.

Low overhead design for programmable logic array with testability

Abstract A new design to reduce the overhead required for a fully testable PLA is proposed. This design rearranges and groups the product lines into partitions. Then, one extra output line per partition is added to make the whole PLA testable. The silicon area overhead required by this design is significantly less than those of previous methods.