Low Coefficient Sensitivity Research Articles

Design of state digital filters

In this correspondence, we develop a very simple algorithm for the design of a second-order state-space digital filter. The design equations presented here were derived on the rendition that the sensitivity of the coefficients in the state-space digital filter (SDF) are spread uniformly to all coefficients of the SDF. The design algorithm has been shown to provide SDF realizations having a minimum output round-off noise while preserving low coefficient sensitivity and freedom from limit cycles.

ARMA direct form filter designing method to reconstruct FIR digital filters based upon genetic algorithm and simulated annealing.

In this paper, the method for reconstructing FIR digital filter into ARMA direct form digital filter based upon adaptive ARMA Four Line Lattice filter with the phase estimation is proposed. The phase estimation is performed by the combination of GA (Genetic Algorithm) and SA (Simulated Annealing) in addition to the spectrum estimation. In order to reduce the calculation cost that will be significant issue for the system implementation of digital filters into the products, it will be necessary to design ARMA digital filter.Introducing the phase estimation method, it contributes the possibility to provide optimum ARMA digital filters that is not only relatively lower coefficient sensitivity and better robustness, but also it will maintain all its desired characteristics that include the phase performance. Maintaining the phase characteristics is the unforgettable factor for the fields of the inverse filtering problem for any opportunities. We conduct the original cost function that will cooperate with GA and SA searching in order to realize the phase estimation. In this paper, experimental results are also discussed to confirm the performance of proposed method.

Design and VLSI architecture and implementation of wave digital filters using short signed digit coefficients

The good dynamic range, low round-off noise characteristics and low coefficient sensitivity of wave digital filters make them suitable for realisations with short coefficient word-lengths. The authors discuss the design and implementation of a wave digital architecture using short signed digit coefficient ranges. The fundamental processing block employed in the implementation is the two port adaptor. Restricting the coefficients to this particular form reduces the number of levels of addition required in its implementation. Both the algorithmic and architectural aspects of this are considered. The resultant hardware increases the upper operating frequency, or sample rate, of the realisation, but at the expense of restrictions in the range of filter specifications that can be met. Hardware for a low latency, high clock rate adaptor is developed and cast into a form suited to VLSI implementation. A demonstrator for the concept has been designed and successfully fabricated in 1 /spl mu/m standard-cell CMOS technology. It is a programmable, cascadable device that may be applied to all standard filter types. The chip has a die area of 12.7 mm/sup 2/ and has been successfully tested to a clock rate of 30 MHz, which is twice the maximum filter sample rate.

Design of fixed point state space digital filters with low round‐off noise

AbstractA simple method is described for the design of fixed‐point recursive digital filters with low round‐off noise. the method is based on reducing to zero as many as possible of the coefficients of the filter state matrices. an optimization procedure is used to get the optimum value of linear transformation that minimizes the total output round‐off noise power. Compared with the existing approaches, this method is characterized by its computational simplicity, very low output round‐off noise (if not the lowest possible) and low coefficient sensitivity. the structure of the proposed technique is modular, which makes it suitable for VLSI implementation. the technique is then employed to obtain a reduced‐order low‐round‐off‐noise filter with characteristics equivalent to some desired FIR specifications. Illustrative examples are given to verify these advantages.

High-speed digital filtering: Structures and finite wordlength effects

This paper is a study of high-throughput filter structures such as block structures and their behavior in finite precision environments. Block structures achieve high throughput rates by using a large number of processors working in parallel. It has been believed that block structures which are relatively robust to round-off noise must also be robust to coefficient quantization errors. However, our research has shown that block structures, in fact, have high coefficient sensitivity. A potential problem that arises as a result of coefficient quantization is a periodically time-varying behavior exhibited by the realized filter. We will demonstrate how finite wordlength errors can change a nominally time-invariant filter into a time-varying system. We will identify the block structures that have low coefficient sensitivity, and develop high-speed structures that are immune to the time-varying problems caused by coefficient quantization.

Pipelined recursive filter with minimum order augmentation

Pipelining is an efficient way for improving the average computation speed of an arithmetic processor. However, for an M-stage pipeline, the result of a given operation is available only M clock periods after initiating the computation. In a recursive filter, the computation of y(n) cannot be initiated before the computations of y(n-1) through y(n-N) are completed. H.B. Voelcker and E.E. Hartquist (1970) and P.M.Kogge and H.S. Stone (1973) independently devised augmentation techniques for resolving the dependence problem in the computation of y(n). However, the augmentation required to ensure stability may be excessively high, resulting in a very complex numerator realization. A technique which results in a minimum order augmentation is presented. The complexity of the resulting filter design is very much lower. Various pipelining architectures are presented. It is demonstrated by an example that when compared to the prototype filter, the augmented filter has a lower coefficient sensitivity and better roundoff noise performance. >

Optimal synthesis of multidimensional state-space digital filters: A general analysis

The optimal synthesis of a single-input single-output (SISO) multidimensional (M-D) digital filter with fixed-point arithmetic is investigated. The necessary and sufficient conditions for optimal realizations for both optimal and equal wordlength registers are established. It is shown that these optimality conditions always can be satisfied for an arbitrary M-D filter. It is proven that optimal structures possess some favorable properties such as low coefficient sensitivity. It is found that the optimal realizations of a multidimensional filter demonstrate a remarkable property in needed number of multipliers per sample output is comparison to one dimensional (1-D) optimal structures. Two numerical examples are presented to illustrate the design procedure and usefulness of the proposed scheme.

Multichannel IIR filter banks composed of all‐pass filters as construction elements

AbstractFilter banks are being used in many areas, e.g., voice processing in communication systems; and active research has been on‐going in this field in recent years.This paper describes a method of realizing multichannel IIR filter banks which could divide the frequency range into an arbitrary number of uniform bands. In this method, filter banks are formed by shifting the low‐pass characteristics with the help of variable transformation with respect to ω and a π/2 phase shifting with the help of a Hilbert transformer. Hence, this design procedure becomes similar to the design of linear‐phase all‐pass filters.This IIR filter including the Hilbert transformer can be implemented with the help of an all‐pass filter, and thus low coefficient sensitivity property can be realized. Moreover, the transition band is narrower compared to the FIR structure. Other than the forementioned merits, the design is comparatively simple; and all the coefficients can be obtained in an analytical way using Fourier series expansion.

VLSI system compiler for digital signal processing: modularization and synchronization

An overview of a VLSI system compiler that generates a highly parallel and fast processor array on a VLSI chip for general digital signal processing algorithms is described. The modularization and the synchronization of general digital signal processing algorithms in order to convert them into suitable forms for implementation by a processor array on a VLSI chip are described. Signal processing algorithms are modularized into the minimum number of inner-product modules by the proposed modularization procedure. Modularizing digital signal processing algorithms with low coefficient sensitivity parameters is also proposed. These modules are assigned to inner product processors. After processors have been placed and communication paths between them have been routed on a VLSI chip, the synchronization procedure derives a schedule for this VLSI system. The scheduling, which is free of both data conflict on interprocessor data links and inner-product operation execution conflict on processors, is investigated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Construction of 2‐D digital filters using all‐pass networks with complex coefficients

AbstractSeveral methods have been presented recently for constructing the one‐dimensional IIR digital filter by combining all‐pass networks. It is known that the filter composed of the all‐pass networks has a better computational efficiency and also low coefficient sensitivity due to the structural boundaries. In addition to the one‐dimensional filters, a construction of the two‐dimensional filter based on the all‐pass network has also been proposed. A problem in that method, however, is the restriction on the realizable characteristics.This paper attempts to overcome that problem, and proposes a new construction of the two‐dimensional digital filter using the all‐pass network. The new approach employs the complex coefficient all‐pass network instead of the conventional real‐coefficient all‐pass network. By this approach, the degree of freedom in the design is enhanced, and the characteristics which have been difficult or impossible to realize in the case of the real coefficient filters, are now made realizable.

Complex linear prediction method based on positive frequency domain

AbstractThis paper proposes a linear prediction method using the analytic signal which occupies half the bandwidth of the real signal. Consequently, the order is halved in the proposed method, thereby reducing drastically the computational complexity. The proposed method gives a stable solution for a finite word‐length operation, and the obtained reflection coefficient has a low coefficient sensitivity. These are both useful properties in the synthesis of speech.

On the design of second-order state-space digital filter sections

A simplified parametric representation is introduced for the exploration of all real-scaled state-space realizations of a second-order transfer function having complex-conjugate poles. It is found that all real-scaled realizations can be represented as a function of a limited range of two real angles. It is shown that this representation can be used to obtain computationally efficient realizations with low roundoff noise and realizations which are roundoff-noise-optimal subject to L/sub infinity /-norm scaling. This latter class of realizations, which has not previously been synthesized, is found to be very similar to the realizations obtained by simply rescaling an optimal L/sub 2/-norm-scaled realization for L/sub infinity / scaling. An algebraic technique is introduced for the synthesis of second-order state-space realizations. This technique provides realizations that are as computationally efficient as possible, subject to preserving low roundoff noise, low coefficient sensitivity, and freedom from limit cycles.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Synthesis of leapfrog‐type digital filters based on the distributed circuitsimulation

AbstractIt is known that a leapfrog‐type digital filter obtained by simulating an LC ladder filter terminated with resistors on both ends is a digital filter with a low coefficient sensitivity. In this paper, an analog circuit to be simulated is chosen as a distributed circuit in which the real frequency and the discrete variable correspond rigorously. By means of an equivalent transformation, a leapfrog‐type digital filter is constructed in which no delay free loop is generated. In this method, an LC ladder circuit expressed in terms of the Richard variable p is transformed to the circuit expressed in terms of the LDI variable γ. the digital filter is configured by simulation of the relationship between the node voltage and series branch current in each element of LC ladder circuit. However, if the configuration is based on general distributed LC ladder circuits, a delay‐free loop is always generated and configuration becomes unstable. As a solution to this problem, unit elements are introduced in this paper. It is shown that a realizable signal‐flow graph can always be obtained if stub circuits are used as the original circuit. the basic section necessary to circuit configuration is presented. Finally, as a practical example, the present method is used for design of a fourth‐order bandpass filter. the results are described and compared with those by other configurations.

Design of minimum phase FIR digital filters

Minimum phase FIR filters are known to have certain practical advantages, e.g. minimum group delay, reduced order for given gain specifications, and lower coefficient sensitivity, when compared with the more common linear phase filters. In the paper, a new adaptive method for designing such filters is presented. The algorithm requires a gain specification in a manner identical to the linear phase case. Conditions for optimality are investigated in terms of the zeros' configuration, equiripple characteristics, minimax and LMS criteria. The result is a very flexible minimum phase FIR filter design technique, with the potential to accommodate a number of different filter structures and types. It is thought to be the second, after the transformation of linear to minimum phase approach, able to guarantee optimum Chebyshev solutions.

Tunable digital frequency response equalization filters

Tunable digital frequency response equalization filters, which feature adjustable gain at specified frequencies while leaving the remainder of the spectrum unaffected, are advanced. The filter structure is such that the frequency response parameters are independently related to the multiplier coefficients, which permits simple frequency response adjustment by varying the coefficient values. The resulting structure exhibits low coefficient sensitivity characteristics.

Wave digital filters based on extracting two‐wire lines

AbstractIt is well known that wave digital filters (WDF's) imitating the behavior of doubly terminated reactance circuits have low coefficient sensitivity properties. Based on the Darlington synthesis procedure, a cascade synthesis of WDF's realizing arbitrary transfer functions has been shown. They are constituted with cascading basic WDF sections corresponding to basic reactance sections. The cascade synthesis procedure, however, is rather complicated in that transmission zeros have to be found by calculating the roots of an algebraic equation.

Realization method of approximate wave‐digital filter d‐section based on lumped/distributed network

AbstractThis paper proposes a reduction method for the D‐section which realizes the complex attenuation poles in the wave digital filter (WDF) design. The reduction is based on the lumped/distributed network. First, an approximate lumped network (called A2‐section) is introduced for the transmission line (UE) with the length T where Richard's variable u = tanh TS is replaced by the rational function qrs/(p2 + t2S2) (p ± 1.6, q ± 2.8). The A2‐section has a set of complex attenuation poles if the values t, p, q are chosen so far as the attenuation pole s = (± y ± j ± ‐ y2)/2(y = q/t, ± = p/t) is complex. In this case, the A2‐section is called the A2‐section. Then it can be shown that the cascade connection 2‐port of two GA2‐sections and series coils is equivalent to the D‐section, and the D‐section is also approximately equivalent to the 2‐port composed of two UE's and LC elements: By applying the well‐known WDT realization method by Fettweis and Swammy, simultaneously, an approximate but very simple D‐section of WDF is obtained. When the length of UE is small, the deviation of WDF response from the design specification is small. As an example, the design of the WDF bandpass filter is shown and the low coefficient sensitivity property compared to the conventional cascade synthesis method is verified.

Low multiplier coefficient sensitivity block digital filters

Block ladder filters, based upon a ladder analog, are developed. A general procedure for removing delay free loops from digital filters is presented. Using the procedure, vector delay free loops of block ladder filters are eliminated. The multiplier coefficient sensitivities of the resulting block ladder based filters are considerably better than the corresponding sensitivities of previously developed block filters.

Computationally efficient second-order digital filter sections with low roundoff noise gain

A class of second-order recursive digital filter realizations is described that provides near-optimal roundoff noise performance, low-coefficient sensitivity, and freedom from overflow limit cycles. The number of multiplications required, per output sample, is one more than the canonical direct form realization. This class of realizations provides an attractive compromise between the computationally intensive optimal realization and the finite-word-sensitive direct form. Explicit design procedures are provided, and a numerical design example is presented that illustrates the near-optimal performance of this new class of realizations.

New digital notch filter structures with low coefficient sensitivity

For narrow-band digital notch filters, poles are near the unit circle. Also, when the sampling rate is increased, the poles approach the point Z = + 1 . The usual realizations of digital notch filters are highly sensitive to coefficient quantization. Three new digital notch filter structures are proposed, and their coefficient sensitivities are derived.