Logic Pipeline Research Articles

Current approaches in UAV Operational Risk Assessment and Practical Considerations

The expansion of Unmanned Aircraft Systems (UAS) is creating new markets, particularly in Urban Air Mobility (UAM), which presents unique challenges. Beyond the risk of mid-air collisions, UAM services in urban areas introduce ground risks to buildings, traffic routes, and pedestrians. This research explores trends in Ground Risk models for different operation planning stages: strategic, pre-tactical, and tactical. It offers a logical pipeline for UAS operators, emphasizing detailed analysis and data source considerations, along with the importance of model interoperability. Using a Naples case study, the research provides practical steps for national authorities to streamline the UAS authorization process.

Development of Mathematical Logic Pipeline Tools (Pilogmath) for Learning Mathematical on Logic Material

This development research aims to determine the feasibility of using Mathematical Logic Pipe teaching aid (Pilogmath) on mathematical logic material at SMA Negeri 1 Tanah Luas in terms of validity, practicality, and attractiveness. The development model used is the ADDIE development model which consists of the stages of analysis (analysis), design (design), development (development), implementation (implementation), evaluation (eveluation). The subjects of this research are class X SMA Negeri 1 Tanah Luas. The feasibility of learning media refers to the results of the assessment of teaching aids by experts, teachers and small group students. Feasibility can be seen from the results of the validator's assessment where all validators stated very valid, the results of the percentage of product ratings by media experts were 81% in the “Very Valid” category, the results of the percentage of product ratings by material experts were 87% in the “Very Valid” category, the results of the percentage of product assessment by the teacher were 92% in the “Very Practical” category, and the results of the percentage of product assessment by 6 small group students were 93 .6 % in the “Very Interesting” category. Based on product assessment by all validators who stated that it was very valid, the teachers assessment stated that it was very practical, and student assessment stated that it was very interesting, the Mathematical Logic Pipe teaching aid (Pilogmath) that was developed meeting the criteria of being very feasible to use for class X students of SMA Negeri 1 Tanah Luas.

A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver

Practical realization of decision feedback equalizers (DFEs) has to date been limited to at most two taps in 100-Gb/s long-reach (LR) wireline applications due to significant power, area, and timing costs. This article presents a systolic many-tap low-complexity sliding-block decision feedback equalizer (SB-DFE) that overcomes the implementation challenges of conventional DFEs with no performance loss. A nine-tap configuration is demonstrated in a 112-Gb/s analog-to-digital converter (ADC)-digital signal processing (DSP) four-level pulse amplitude modulation (PAM-4) LR wireline receiver implemented in 7-nm FinFET. The architecture partitions the received signal into overlapping but computationally independent blocks thereby breaking the feedback loop of the DFE and allowing logic pipelining. Unlike existing feedback-breaking techniques, the computational overhead of the SB-DFE can be made arbitrarily small for any tap count—indeed, we show the practicality of SB-DFE implementations exceeding 30 taps. Optimized pipeline cuts are employed to minimize the latency through the SB-DFE while maintaining timing margin. The nine-tap SB-DFE is paired with a five-precursor tap feedforward equalizer (FFE) and compared to a two-tap-DFE 15-tap-FFE reference DSP implemented in the same receiver. A bit error rate of 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> is measured over a 36-dB loss channel—at least an order-of-magnitude reduction compared to the reference DSP. Power is reduced by 0.33 pJ/b. DSP gate area is reduced by 30%. Noise tolerance is improved by 0.2-mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> . Error-free operation is demonstrated on an RS(544,514) KP4 forward error correction (FEC)-encoded link even when the DFE tap values are manually stressed. Techniques for further reduction in complexity are described.

The 3M Concept: Biomedical Translational Imaging from Molecules to Mouse to Man

Abstract Imaging keeps pervading biomedical sciences from the nanoscale to the bedside. Connecting the hierarchical levels of biomedicine with relevant imaging approaches, however, remains a challenge. Here we present a concept, called “3M”, which can deliver a question, formulated at the bedside, across the wide-ranging hierarchical organization of the living organism, from the molecular level, through the small-animal scale, to whole-body human functional imaging. We present an example of nanoparticle development pipeline extending from atomic force microscopy to pre-clinical whole body imaging methods to highlight the essential features of the 3M concept, which integrates multi-scale resolution and quantification into a single logical process. Using the nanoscale to human clinical whole body approach, we present the successful development, characterisation and application of Prussian Blue nanoparticles for a variety of imaging modalities, extending it to isotope payload quantification and shape-biodistribution relationships. The translation of an idea from the bedside to the molecular level and back requires a set of novel combinatorial imaging methodologies interconnected into a logical pipeline. The proposed integrative molecules-to-mouse-to-man (3M) approach offers a promising, clinically oriented toolkit that lends the prospect of obtaining an ever-increasing amount of correlated information from as small a voxel of the human body as possible.

A robust multi-objective optimisation model for natural gas supply chain design under uncertainty: a case study

The appropriate design of a complex natural gas supply chain becomes a critical issue for both academics and practitioners. To deal with the design of complicated natural gas supply chain, a mixed integer nonlinear programming model is developed in this paper. Two conflicting objectives including the minimisation of the total cost and the maximum unfulfilled demands are considered subject to technical and logical pipeline and compressor constraints. Since a number of critical parameters are tainted with imprecision in the proposed model, a robust possibilistic programming approach is applied to handle the inherent uncertainty. A natural gas network in Iran is used as a case study to verify and validate the developed model. [Received: October 08, 2019; Accepted: May 27, 2020]

Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders

SummaryThis work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high‐performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high‐capacity hybrid (HC‐hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC‐180 nm and UMC‐65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns.

Design Requirements for a Spintronic MTJ Logic Device for Pipelined Logic Applications

Spintronic devices have been spotlighted due to their nonvolatility and potential for low-voltage operation. However, their potential performance and energy efficiency require greater scrutiny. In this paper, a circuit-level energy-performance analysis is used to derive the design requirements for a spintronic magnetic tunnel junction logic device, mLogic , for pipelined logic applications. An analytical equation for the domain wall mobility of mLogic is derived to predict the performance of future designs and used to point to key directions for further device improvement. We show that the energy dissipation of a logic pipeline under delay constraints is a convex function of the write/read-path resistance ratio and the supply voltage. Scaling the supply voltage can reduce the energy dissipation at the expense of switching speed, but is limited by an extrinsic pinning effect and thermal noise. The energy reduction by maximizing the tunnel magnetoresistance (TMR) will be saturated for TMR larger than 100. But maximizing TMR can mitigate the thermal noise limit of scaling the supply voltage. The energy gap between MOSFETs and mLogic gets smaller for more advanced technology nodes. With 32-nm technology, a future mLogic design can be more optimal than MOSFETs in low-power and low-performance applications, such as emerging Internet-of-Things devices.

16x16 Multiplier Design Using Asynchronous Pipeline Based On Constructed Critical Data Path

Asynchronous domino logic pipeline design is a latchless high throughput and low power design. In this design dual-rail domino gates are used to construct the stable critical data path and single-rail domino gates are used in non critical data paths. An 8x8 array style multiplier is used to evaluate this pipeline design. This proposed technique is general and can be used in all domino logic circuit designs. Now this can be implemented for higher order multipliers like 16x16.

Exploring Spin-Transfer-Torque Devices for Logic Applications

As CMOS nears the end of the projected scaling roadmap, significant effort has been devoted to the search for new materials and devices that can realize memory and logic. Spintronics, is one of the promising directions for the Post-CMOS era. While the potential of spintronic memories is relatively well known, realizing logic remains an open and critical challenge. All Spin Logic (ASL) is a recently proposed logic style that realizes Boolean logic using spin-transfer-torque (STT) devices based on the principle of non-local spin torque. ASL has advantages such as density, non-volatility, and low operating voltage. However, it also suffers from drawbacks such as low speed and static power dissipation. Recent work has shown that, in the context of simple arithmetic circuits (adders, multipliers), the efficiency of ASL can be greatly improved using techniques that utilize its unique characteristics. An evaluation of ASL across a broad range of circuits, considering the known optimization techniques, is an important next step in determining its viability. In this work, we propose a systematic methodology for the synthesis of ASL circuits. Our methodology performs various optimizations that benefit ASL, such as intra-cycle power gating, stacking of ASL nanomagnets, and fine-grained logic pipelining. We utilize the proposed methodology to evaluate the suitability of ASL implementations for a wide range of benchmarks viz. random combinational and sequential logic, digital signal processing circuits, and the Leon SPARC3 general-purpose processor. Based on our evaluation, we identify (i) the large current requirement of nanomagnets at fast switching speeds, (ii) the static power dissipation in the all-metallic devices, and (iii) the short spin flip length in interconnects as key bottlenecks that limit the competitiveness of ASL.

Circuit Level Defences Against Fault Attacks in Pipelined NCL Circuits

As a type of side-channel attack, fault attacks on the hardware implementation of cryptographic algorithms has been widely studied, and has been successfully applied to a variety of ciphers. So far, many hardware countermeasures against fault attacks have been proposed. However, most of them are tailored to a specific cryptographic algorithm and cannot provide a comprehensive level of protection against all possible faults. In this paper, we present a novel, secure and generic framework based on the robustness of null convention logic pipelines and dual-rail encoded systems, which is resistant to fault attacks at the circuit level by implementing technologies such as rail synchronization, maximum delay matching, error-detecting monitors, and self-feedback mechanisms. Both the theoretical analysis and simulation results show that all faults at the output of computational blocks can be fully detected and corrected. The new framework gives us the ability to detect and correct the faults induced in the register.

Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path

This paper presents a high-throughput and ultralow-power asynchronous domino logic pipeline design method, targeting to latch-free and extremely fine-grain OR gate-level design. The data paths are composed of a mixture of dual-rail and single-rail domino gates. Dual-rail domino gates are limited to construct a stable critical data path. Based on this critical data path, the handshake circuits are greatly simplified, which offers the pipeline high throughput as well as low power consumption. Moreover, the stable critical data path enables the adoption of single-rail domino gates in the noncritical data paths. This further saves a lot of power by reducing the overhead of logic circuits. An 8 $\,\times\,$ 8 array style multiplier is used for evaluating the proposed pipeline method. Compared with a bundled-data asynchronous domino logic pipeline, the proposed pipeline, respectively, saves up to 60.2% and 24.5% of energy in the best case and the worst case when processing different data patterns.

Dual-Core FFT Processor Based on a High-Speed Real-Time Floating-Point Butterfly Processing Element

This paper presents a dual-core floating-point FFT processor. The internal butterfly unit of the processor based on CORDIC algorithm, and uses an iterative computation process instead of two computation process which is the complex multiplication and the evaluation of trigonometric function. The butterfly unit has nothing to do with the external memory size, so it can handle large quantities of data. Based on this unit, the processor uses two logical processing core and pipeline system to improve the throughput and instantaneity. So the design has large scope of input and high-precision operation features. Finally, we make a timing simulation for the Alteras chip of EP2C20F484C6, which can run correctly under the 100MHz system clock.

A FPGA-Based Design of Floating-Point FFT Processor with Dual-Core

This paper presents a dual-core floating point FFT processor design based on CORDIC algorithm, enabling high-speed floating-point real-time FFT computation, and its time complexity is (N / 4) Log (N / 2). The design unifiesthe floating complex multiplication and the evaluationof twiddle factors into an iteration, which not only reduces the complexity of complex multiplication but also reduces the difficulty when the butterfly unit deals with floating-point in fast Fourier transform. The butterfly unit unaffected by the size of external memory can handle the Fourier transform with high sample number, both having wider handling range and high handling precision. It uses two logical cores and pipeline technology to improve overall system throughput, with simple hardware structure and system stability.At the end, it does the post-simulation on the Altera chip EP2C35F672C6, and its timing simulation can be run properly under the 50 MHz clock frequency.

Field Programmable Stateful Logic Array

Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. The proposed architecture mapped to the field programmable nanowire interconnect fabric produces a field programmable stateful logic array, in which general-purpose computation functions can be implemented by configuring only nonvolatile nanowire crossbar switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely, material implication, cannot fan out, a new basic AND operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. The fine-grain ultradeep constant-throughput pipeline properties pose new design automation problems. We address some of the issues, in particular logic representation using OR-inverter graphs, two-level optimization synthesis strategy, data synchronization with data forwarding, stall-free pipelined finite state machines, and constraints for synthesis and mapping onto the fabric.

Intelligent Interring Route Control in Bridged Resilient Packet Rings

In this paper, intelligent interring route control is proposed for bridges that connect two resilient packet rings (RPRs). The intelligent interring route controller (IIRC) is designed according to the load-balancing principle, where the IIRC considers not only the congestion degree of both bridge and its downstream nodes but also the service rate and the number of hops to destination. It contains three functional blocks implemented by fuzzy logic systems or pipeline recurrent neural networks (PRNNs). A fuzzy bridge-node congestion indicator (FBCI) is to detect the congestion degree of the bridge, a PRNN downstream-node fairness predictor (PDFP) is to predict the mean received fairRate from downstream nodes, and a fuzzy route controller (FRC) is to determine a preference value of route according to the congestion indication, the predicted mean received fairRate, the service rate of the bridge, and the number of hops to destination. Simulation results show that the IIRC improves the performance by about 10% and 220% in packet-dropping probability, by about 13% and 18% in average packet delay, and by about 6% and 19% in throughput over the queue-length threshold route controller (QTRC) and the shortest path route controller (SPRC), respectively. Moreover, IIRC achieves higher throughput by 7% than IIRC itself but without considering the prediction of the mean received fairRate.

ARCHITECTURES AND FPGA IMPLEMENTATIONS OF THE 64-BIT MISTY1 BLOCK CIPHER

In this paper, we present two alternative architectures and FPGA implementations of the 64-bit NESSIE proposal, MISTY1 block cipher. The first architecture is suitable for applications with high-performance requirements. A throughput of up to 12.6 Gbps can be achieved at a clock frequency of 168 MHz. The main characteristic of this architecture is that uses RAM blocks embedded in modern FPGA devices in order to implement the S-boxes defined in the block cipher algorithm. The second architecture can be used in implementing applications on area-constrained systems. It utilizes feedback logic and inner pipeline with negative edge-triggered register. This technique shortens the critical path, without increasing the latency of the MISTY1 algorithm execution. Compared with an implementation without inner pipeline, performance improvement of 97% is achieved. The measured throughput of the second architecture implementation is 561 Mbps at 79 MHz.

Area efficient FIR filters for high speed FPGA implementation

A new algorithm that synthesises multiplier blocks with low hardware requirement suitable for implementation as part of full-parallel finite impulse response (FIR) filters is presented. Although the techniques in use are applicable to implementation on application-specific integrated circuit (ASIC) and Structured ASIC technologies, analysis is performed using field programmable gate array (FPGA) hardware. Fully pipelined, full-parallel transposed-form FIR filters with multiplier block were generated using the new and previous algorithms, implemented on an FPGA target and the results compared. Previous research in this field has concentrated on minimising multiplier block adder cost but the results presented here demonstrate that this optimisation goal does not minimise FPGA hardware. Minimising multiplier block logic depth and pipeline registers is shown to have the greatest influence in reducing FPGA area cost. In addition to providing lower area solutions than existing algorithms, comparisons with equivalent filters generated using the distributed arithmetic technique demonstrate further area advantages of the new algorithm.

A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system

A single-chip rendering engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three dedicated network schemes, virtual page mapping, memory-coupled logic pipeline, low-power operation, 7.1-GB/s memory bandwidth, and 11.1-Mpolygon/s drawing speed. The 56-mm/sup 2/ prototype die integrating one edge processor, eight pixel processors, eight frame buffers, and a RISC core are fabricated using 0.35-/spl mu/m CMOS embedded memory logic (EML) technology with four poly layers and three metal layers. The fabricated test chip, 590 mW at 100 MHz 3.3 V operation, is demonstrated with a host PC through a PCI bridge.

CPC (cyclic pipeline computer)-an architecture suited for Josephson and pipelined-memory machines

Describes a novel computer architecture, called a cyclic pipeline computer (CPC), which is especially suited for Josephson technologies. Since each Josephson logic device acts as a latch, it is possible to use high-pitch and shallow logic pipelining without any increase in delay time and cost. Hence, both the processor and the main memory can be built from the Josephson devices and can be pipelined with the same pipeline pitch time. The CPC supports multiple instruction/multiple data stream (MIMD) by time-sharing the processor and the main memory among multiple instruction streams. In addition, it employs advanced control to speed up the computation for each instruction stream.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>