Local Oxidation Of Silicon Isolation Research Articles

Analysis of Hump Effect Induced by Positive Bias Temperature Instability in the Local Oxidation of Silicon n-MOSFETs

In this study, the degradation of the subthreshold swing (S.S.) and the hump effect are observed in the local oxidation of silicon (LOCOS) metal-oxide-semiconductor field-effect transistors (MOSFETs) under short-and long-term positive bias temperature instability tests, respectively. S.S. collapse is considered to be caused by anode hot-hole injection, and the hump effect occurs because the geometric structure from LOCOS isolation forms parasitic transistors on both sides of the channel, which can be verified by a Silvaco Technology computer-aided design (TCAD) simulation. In addition, the body effect measurement method is proposed to elucidate the mechanism of the hump effect for further confirmation of hump formation.

Modeling and Characterization of the Narrow-Width Effect of 4H-SiC MOSFETs With Local Oxidation of SiC Isolation

In this article, the narrow-width effect (NWE) of 4H-SiC MOSFETs with local oxidation of SiC (LOCOSiC) isolation is reported. A channel width-dependent current hump was observed in the subthreshold region for n-type 4H-SiC MOSFETs with LOCOSiC, and a channel width-dependent threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{th}$ </tex-math></inline-formula> ) shift was observed for p-type 4H-SiC MOSFETs with LOCOSiC. This unusual NWE arises from the increase in the gate oxide thickness from the channel center toward the isolation edge and is different from the conventional NWE found in local oxidation of silicon (LOCOS) technology, which arises from the charge stored in the parasitic field oxide (FOX) capacitor and lateral dopant encroachment. A H2O diffusion and oxidation model is proposed in this article to explain the growth of a long bird’s beak in 4H-SiC MOSFETs with LOCOSiC. Technology computer-aided design (TCAD) simulations were executed to explore the H2O diffusion behavior of these MOSFETs, and an analytical formula was derived to predict the oxide layer thickness and length of bird’s beak along the diffusion path in the H2O diffusion and oxidation model. The problems caused by the long bird’s beak and unusual NWE can be overcome by increasing the overetching time of the pad oxide removal and marginally decreasing the thickness of the FOX layer. Therefore, the NWE of the LOCOSiC isolation is expected to be weaker than that of the LOCOS isolation because field implantation is unnecessary, and thus, dopant encroachment does not occur in the LOCOSiC technology.

Comparison of holes trapping and protons transport induced by low dose rate gamma radiation in oxide on different SiGe processes

Space-related electronics contain different types of oxide isolations which are the crucial factor resulting in device degradation and failure. Previous studies show that the local oxidation of silicon (LOCOS) isolation Silicon‑germanium heterojunction bipolar transistor (SiGe HBT) experience more significantly low dose rate sensitivity than that of shallow trench (STI) isolation SiGe HBTs and behave a “true” dose rate effect. In our work, the electron-hole pairs (EHPs) generation, holes trapped and protons transport inside oxide are simulated in LOCOS and STI isolation SiGe HBTs to explanation the different response t enhanced low dose rate sensitivity (ELDRS). The simulation results show that LOCOS oxide has a larger generation of EHPs than that of STI oxide leading to more surviving holes and protons release within oxide.

Characterization of LOCOS Field Oxide on 4H-SiC Formed by Ar Preamorphization Ion Implantation

In this letter, the electrical properties of local oxidation of silicon (LOCOS) field oxide formed on 4H-SiC are reported. Moreover, unlike the conventional Si LOCOS process, a simpler method based on Ar preamorphization implantation is proposed. In addition to direct characterization of the field oxide, device properties achieved using LOCOS isolation are compared with those achieved using the conventional chemical vapor deposition oxide isolation to clarify the impact of isolation technology. The results of this letter would be insightful for silicon-carbide-based very-large-scale integration technology.

Radiation hardening technology in SOI materials and devices

Based on the great success of silicon material and silicon integrated circuit, the silicon-on-insulator (SOI) technology occurs as a new technology with unique advantages to break the limitation of traditional bulk silicon technology. The existence of the buried oxide (BOX) can fundamentally eliminate the latch-up effect of the bulk CMOS technology. The sensitive volume of charge collection in SOI device is smaller than in bulk one, potentially making SOI devices much more hardened to dose rate effect and single-event upset, the upset cross section is nearly two orders of magnitude smaller. These inherent advantages of SOI technology make it very important in military and space applications. However, the existence of the thick buried oxide also makes the total ionizing dose (TID) effect of the SOI devices more complicated. The radiation-induced trapped charge in the buried oxide can lead to serious degradations of the SOI devices and circuits in the space and nuclear radiation environment, such as the increases of the off-state leakage current in the partially-depleted devices and the decreases of the front-gate threshold voltage in the fully-depleted NMOS devices. Meanwhile, the relatively thick field oxide is also very soft to ionizing radiation. Two common types of field oxide isolation are local oxidation of silicon (LOCOS) and shallow trench isolation (STI). LOCOS isolation has been replaced by STI to reduce spacing between adjacent devices in the advanced submicron technology node. STI induced leakage after TID radiation has become a dramatic problem in modern technologies. Both the STI oxide and the buried oxide can potentially impact the total dose tolerance in SOI transistors. This limits the application of SOI technology in radiation hardening. It is only by solving the problem of the total dose hardening that the SOI technology can better fulfill its military applications. In addition, the single-event effect and dose rate effect of the SOI circuits become more complicated due to the less critical charge for upset, higher operating frequency and enhanced parasitic bipolar effect for the deep submicron technology. All these factors challenge the hardening design technique of the SOI devices and circuits. In this paper, the difference of ionizing radiation effects between bulk-silicon devices and SOI devices is compared. In order to enhance the radiation hardness of single event effect and dose rate effect in SOI device, the method of suppressing the parasitic bipolar transistor effect is proposed. Furthermore, the radiation hardened methods for TID effect in SOI technology is investigated from two levels: radiation hardened by material and process, radiation hardened by layout. The development of an independent SOI radiation hardening technology will contribute to solve the problem in military electronics, such as radiation hardening, high reliability, and to promote the sustainable development of national defense construction and national security.

0.5 μm工艺CMOS有源像素传感器的总剂量辐射效应

In order to evaluate the effects of space radiation on the imaging function of a CMOS active pixel sensors(APS) manufactured in a 0. 5 μm CMOS N-well technology,60Co-γ radiation experiment was conducted for the overall circuit and pixel unit of the device,and the effects of the total dose on the main parameters of the device were analyzed. When the total dose of irradiation reached a certain value and during annealing,the dark signal,saturated output signal and pixel unit output signal were measured quantitatively off line. The mean dark signals dramatically increase with the total dose. The saturation output signal decreases with the total dose,being consistent with the output signal of the pixel unit saturation. It is found that the degradation of the device parameters is caused mainly by the radiation induced charge in LOCOS(Local oxidation of silicon) isolation oxide layer.

Research on dark signal degradation in 60Co γ-ray-irradiated CMOS active pixel sensor

A study of ionizing radiation effects is presented for CMOS active pixel sensors manufactured in a 0.5-μm CMOS (complementary metal oxide semiconductor)by n-well technology. The basic mechanisms that may cause failure are also presented. After exposure in γ-rays, the most sensitive parts to radiation-dark signals and dark signal non-uniformity are discussed, i.e. the physical mechanism of the degradation by irradiation. One can see from the experiment that the mean dark signals are dramatically increased with total dose for both operated and static devices. Static device seems more affected by irradiation than operated device. We find that most part of the total dark signal in a pixel comes from the depletion of the photodiode edge at the surface and the rest part is caused by the leakage of the source region of the reset transistor. Dark signal non-uniformity follows the dark current evolution with total dose. Further study of photodiode and LOCOS (local oxidation of silicon) isolation behaviors under irradiation should be done so as to correctly use this qualification techniques on MOS sensors manufactured in CMOS n-well technology process.

Modeling and Simulation of Charge-Pumping Characteristics for LDD-MOSFET Devices With LOCOS Isolation

We propose a model for the so-called constant-amplitude charge-pumping (CP) characteristics, giving the Elliot Gaussian-like CP current curve (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CP</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> ) of lightly doped drain (LDD) MOSFET with local oxidation of silicon (LOCOS). This method is based on modulation of the contributing active-channel area (A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) to the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CP</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> curve, depending on the position of the high and low levels of the gate signal voltage. In addition, it allows to separate and clarify the contribution of all MOSFET regions (such as the effective channel, LDD, LOCOS, and LDD subdiffusion under the LOCOS) to the amount of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CP</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> curves. We have simulated this model and compared with experimental CP data. The model shows a very good correlation with experimental I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CP</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> curves, particularly for transistors with short channel gate lengths (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ≤ 1 μm). However, as the channel gate length increases, the model matches only for rising and falling I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CP</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> curve edges, corresponding to the contribution of LDD and LOCOS regions, respectively. Moreover, we have demonstrated that the deviation, which was observed between the CP model and experimental data at the maximum plateau of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CP</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> characteristics, depends on the gate pulse fall time and vanishes for large fall time. This difference has been found to behave like a geometric component, since it depends on gate length and fall time and disappears for both short gate lengths and long fall times.

Radiation Effect Evaluation in Effective Short and Narrow Channels of LDD Transistor With LOCOS Isolation Using OTCP Method

In this paper, we have presented a new methodology to take out the local oxidation of silicon (LOCOS) and lightly doped drain (LDD) subdiffusion effects from charge-pumping (CP) curves, leaving only the CP current of the effective channel, in narrow- and short-channel MOSFET transistors. First, we have clarified the contribution of LDD-subdiffusion and LOCOS regions to the CP characteristics by studying the spatial distributions of CP threshold and flatband voltages. We have shown that the maximum CP current is the contribution of pumped current in the effective-channel, LOCOS, and LDD-subdiffusion regions. Second, we have successfully used the oxide-trap CP (OTCP) to extract the radiation-induced oxide trap (?N ot) and interface trap (?N it) in effective short- and narrow-channel transistors. Finally, we have performed a comparison between the OTCP and the capacitance-versus-voltage method.

Bird's Beak and Thermally Induced Stress Defects Evaluations of LOCOS Structures Fabricated Using ECR-CVD SiNx Without Pad Oxide

Silicon Nitrides were deposited on the silicon substrates by ECR-CVD (electron cyclotron resonance chemical vapor deposition), without using the pad oxide in LOCOS (LOCal Oxidation of Silicon) isolation technology. The SiNx/Si structure was used to substitute the SiNx/SiO2/Si. The study of this type of the structure was motivated by the possibility to reduce the length of the bird's beak. Defects were created on silicon because the high temperature (1000ºC) applied on SiNx/Si. The Dash wet chemical etch was used to etch the defect on silicon. Optical and SEM microscopy analysis were used to investigate the bird's beak in the obtained LOCOS structures and the defects (dislocations) on silicon performed after high temperature process.

Diode Analysis of High-Energy Boron Implantation-Induced P-Well Defects

The use of a p-n junction diode as a tool for the assessment of the p-well quality is demonstrated, by analyzing in detail the current-voltage and capacitance-voltage characteristics of junctions surrounded by either shallow trench isolation or polysilicon encapsulated local oxidation of silicon. As a reference, diodes fabricated in a p-type substrate and defined by a local oxidation of silicon isolation have been used. Particular emphasis is on the lifetime properties and leakage current activation energy of the p-well region, which has been fabricated by a deep (200 keV) and a shallow (55 keV) boron ion implantation. That the leakage current of large area diodes is governed by electric field-assisted generation of carriers from residual, unannealed deep B-implantation damage is demonstrated. The presence of such defects is confirmed by deep level transient spectroscopy analysis. The generation lifetime profile in the depletion region and the reverse current activation energy are extracted by taking account of the electric field enhancement factor of the thermal generation. Finally, it is shown that the generation lifetime and residual defects depend mainly on the global thermal budget and little on the isolation scheme used. © 2001 The Electrochemical Society. All rights reserved.

Defects in planar Si pn junctions studied with electrically detected magnetic resonance

We report electrically detected magnetic resonance (EDMR) measurements on planar Si pn junctions which were isolated via local oxidation of silicon (LOCOS). The investigations of the as-fabricated diodes show the presence of various defects. We observe Pb centers at the boundary to the LOCOS isolation and an isotropic Si dangling bond related signal which is assumed to be a consequence of ion implantation. The E′H center—a hydrogen-complexed oxygen vacancy in the SiO2 device isolation—is also detected via EDMR. The EDMR detection mechanism, which is based on resonant changes of the device current, restricts the detected oxide defects to those which are close to the interface.

Junction leakage characteristics in modified LOCOS isolation structures with a nitride spacer

Junction leakage characteristics in modified local oxidation of silicon (LOCOS) isolation structures have been studied when a nitride spacer was used to prevent bird's beak encroachment. Junction leakages with very low activation energy and strong voltage dependence were observed in the nitride spacered LOCOS. Comparative studies on the junction leakages of nonrecessed and recessed LOCOS have revealed that an additional silicon recess process after nitride spacer formation reduces the junction leakage current.

High Temperature Local Oxidation of Silicon Field Isolation Morphological Characterization

The morphological characterization of local oxidation of silicon (LOCOS) isolation has been carried out by using steam oxidation in the temperature range 1050 to 1180°C and as‐grown field oxide thickness between 150 and 600 nm. A bird's beak minimum is observed between 100 and 1140°C, corresponding to a change in the bird's beak growth mechanism from a diffusion type to a regime dependent on silicon surface oxidation and nitride oxidation rates. For the first time on LOCOS isolation, the improvement of field oxide thinning by reducing field oxide thickness is reported: that enables a possible scaling for subquarter micrometer design rules.

Nano‐Trenched Local Oxidation of Silicon Isolation Using Island Polysilicon Grains

A new isolation structure which is named as nano‐trenched local oxidation of silicon (NTLOCOS) is proposed. In NTLOCOS process, island polysilicon grains (IPG) are used for making very slender trenches in silicoin substrate. Preliminary results have shown fast oxidation rate due to enchanced surface area exposed to an oxidizing ambient, high volume ratio, and less field oxide thinning effect. For process optimization, two‐dimensional simulation in NTLOCOS with focusing on the effect of nano‐trench width is discussed.

A Novel LOCal Oxidation of Silicon (LOCOS)-Type Isolation Technology Free of the Field Oxide Thinning Effect

A novel LOCal Oxidation of Silicon (LOCOS)-type isolation technology free of the field oxide thinning effect, named POlysilicon (poly-Si) Spacer LOCOS (POS-LOCOS), has been developed. After the first field oxidation, poly-Si is deposited and etched anisotropically. Then, at the narrow field region, substantial amount of poly-Si remains after etching, while only spacers are formed at the ends of the field region for the wide region, and then the second oxidation is performed by oxidizing poly-Si. POS-LOCOS eliminates the field oxide thinning effect. Devices with POS-LOCOS show less variation in the isolation size, lower peripheral junction leakage current, and higher field transistor threshold voltages at narrow isolation region compared to the conventional LOCOS isolation. Almost the same N+/N+ punchthrough characteristics are obtained with POS-LOCOS and conventional LOCOS, and transistors with POS-LOCOS show low leakage current and normal drain current (I d)-gate voltage (V g) characteristic. It is expected that POS-LOCOS will help extend the lifetime of the LOCOS-type isolation to the next generation of the integrated circuit (IC) technology.

Generation Current Reduction at Local Oxidation of Silicon Isolation Edge by Low-Temperature Hydrogen Annealing

The effect of low temperature hydrogen annealing (LTHA) in reducing the generation current at the local oxidation of silicon (LOCOS) isolation edge can be successfully investigated by C-t measurement of metal-oxide-semiconductor (MOS) capacitors with varying periphery-to-area ratio. The generation current, at the LOCOS isolation edge, can then be measured by the separation of the generated peripheral current and the surface and bulk current generated under the gate electrode. As a result, it becomes clear that the generation current is strongly reduced by annealing at a temperature below 400°C, but at 450°C the reduction is rather small.

Microstructural characterization of implanted LOCOS + trench-isolated structures

As device dimensions decrease and circuit densities increase, conventional LOCOS (Local-Oxidation of Silicon) isolation presents a limitation due to lateral encroachment of the isolation-oxide. Variations in LOCOS, including poly-buffered LOCOS have been of interest as means to limit lateral encroachment of the field-oxide into the active device-region. Deep-trench isolation provides a means to support device scaling and in this work is integrated with poly-buffered LOCOS to create self-aligned shallow fieldoxide elements with minimal encroachment into active regions. Use of these technologies however requires an understanding of the behavior of the materials and structures being used and their interactions under different processing conditions. The effect of fabrication-related stresses in the structures is of interest because extended-defects, if formed, could electrically degrade devices.

Defect-Characterization in Implanted Locos + Trench-Isolated Structures

ABSTRACTAs device dimensions decrease in silicon integrated-circuits, conventional LOCOS (local-oxidation of silicon) isolation becomes inadequate to meet dimensional demands. Variations on LOCOS are therefore being explored for further miniaturization of devices. One such variation involves poly-buffered LOCOS + trench-isolation (PBLT). In this study, PBLT structures were characterized using TEM. Wright-etched cross-section SEM micrographs showed etch-pits associated with a combination of high-dose (&gt; 5E14 cm-2) phosphorous implants and PBLT isolation. TEM characterization showed that dislocations were formed in the structures for a combination of high-dose (1E15 cm-2) phosphorous implants (followed by an anneal) and PBLT isolation. Structures exposed to lower-dose (1E14 cm-2) implants showed no defects and neither did 1E15 implanted structures prior to annealing. The results are modelled in terms of the stress configurations present in the structures, and in terms of dislocation-sources resulting from implantation-related dislocation-loops. The dislocation-sources operate in the presence of stresses associated with the isolation-trenches. Glide-loops form, which then grow in response to stresses in the structures and dislocations result on glide planes.

Electrical limitations of advanced LOCOS isolation for deep submicrometer CMOS

Limitations to advanced local oxidation of silicon (LOCOS) based dielectric isolation of the poly buffer type are examined by fabricating CMOS devices with active area widths and spaces to 200 nm. Measured results show that device width scaling to 400 nm is possible using the retrograde-well process. The impact of narrow-channel effects, field oxide thinning, and drain-induced barrier lowering (DIBL) of the field oxide transistors on deep submicrometer CMOS has been quantified. For a retrograde-well process the narrow-channel effect is minimal for active device widths to 0.4 mu m. DIBL is shown to limit the active device spacing to about 0.8 mu m. SUPREM-4 and PISCES-2B simulations are utilized to illustrate the mechanism for the loss of isolation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>