Local Clock Generator Research Articles

CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop

CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop

A Review of Innovative Comparator Designs

Three papers on the optimal design of comparator circuits are further analyzed in this work. Each paper presents a method to improve the performance of comparators. Floating inverter amplifier applied an independent capacitor as the source of the preamplifier, which improves the overall performance of the circuit. In another design, a special local clock generator is proposed to control the input of both of the latch stage and the preamplifier, which makes it possible to adjust the speed and improve the energy efficiency. In dynamic bias circuit design, stabilized common-mode voltage is realized by adding a capacitor to the tail of the pre-amplifier of a latch-type comparator, optimizing the power and noise performance successfully.

Broadband linearity enhancement method for a 1.3 GHz–2.5 GHz digitally-assisted oscillator in a 55-nm CMOS technology

At the L/S band, the digital array radars with digital beam-forming characteristics require a compact RF module for a plane array. Such an RF module would require a small-sized local clock generation to synchronize with the central distributed clock signal. This paper proposes a 0.04 mm2, broadband local clock generation for the RF module in digital array radar. In such a multi-band digital array radar, the linearity of the clock generator is a bottleneck. A linearity enhanced algorithm for switched-capacitor digitally-assisted oscillators is proposed in this paper. In this linearity enhancement technique, a calibration resistor array is used to improve frequency-tuning characteristics. The digitally-assisted oscillator has a highly linearized frequency tuning curve without demanding much more power and silicon area. A prototype is fabricated using a 55-nm CMOS process. From measurement, it has a frequency tuning range from 1.3 GHz to 2.5 GHz while occupying 225 × 180 μm2. The measured coarse bank tuning maximum DNL is 0.39 LSB, and the maximum INL is 4.64 LSB, which has been reduced to 43% of the other state-of-art work. The maximum power consumption is 15.8 mW from a 1.2 V supply voltage.

Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations

We introduce a new clocking approach for digital systems to achieve better resilience to process, voltage, and temperature (PVT) variations. The proposed scheme is based on elastic clock methodology that uses locally generated clocks and elastic handshaking control, thereby achieving efficient and fast adaptation to the variations. However, the elastic clock-based design still requires a significant amount of timing margins due to delay mismatch between the critical path and the replica path for local clock generation, thus reducing the advantages of the elastic clock. We propose a timing error correction scheme tailored to the elastic clock methodology to eliminate such an extra timing margin. We implement an encryption/decryption core in 28-nm CMOS technology for silicon verification. Measurement results show that the proposed scheme reduces energy consumption by 35% and achieves 3.86 × higher performance over the margined baseline design.

Modeling and Simulation of Asynchrony in Neuromorphic Computing

Neuromorphic computing is a non-von Neumann architecture which is also referred to as artificial neural network and that allows electronic system to function in the same manner as that of the human brain. In this paper we have developed neural core architecture analogous to that of the human brain. Each neural core has its own computational element neuron, memory to store information and local clock generator for synchronous functioning of neuron along with asynchronous input-output port and its port controller. The neuron model used here is a tailor-made of IBM TrueNorth’s neuron block. Our design methodology includes both synchronous and asynchronous circuit in order to build an event-driven neural network core. We have first simulated our design using Neuroph studio in order to calculate the weights and bias value and then used these weights for hardware implementation. With that we have successfully demonstrated the working of neural core using XOR application. It was designed in VHDL language and simulated in Xilinx ISE software.

A Low-Power High-Speed Comparator for Precise Applications

A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, process–VDD–temperature corners, and Monte Carlo simulations along with silicon measurements in $0.18~\mu \text{m}$ . The tests confirm that the proposed circuit reduces the power consumption by 50% and provides 30% better comparison speed at the same offset and almost the same noise budgets. Moreover, the comparator provides a rail-to-rail input $V_{\text {cm}}$ range in $f_{\text {clk}} = 500$ MHz.

A Wideband Injection Locked Quadrature Clock Generation and Distribution Technique for an Energy-Proportional 16–32 Gb/s Optical Receiver in 28 nm FDSOI CMOS

We present a novel frequency tracking method that exploits the dynamics of injection locking in a quadrature ring oscillator to increase the effective locking range from 5% (7–7.4 GHz) to 90% (4–11 GHz). The quadrature phase error between I and Q phases of an injection locked ring oscillator is derived and shown to contain frequency error information, both inside and outside the locking range. This error is utilized to form a first-order frequency tracking quadrature locked loop (QLL). This loop generates accurate clock phases for a 4-channel parallel optical receiver using a forwarded clock at quarter-rate. The QLL drives an ILO at each channel without any repeaters for local quadrature clock generation. Each local ILO has deskew capability for phase alignment. The receiver maintains a constant energy-per-bit consumption across 16–32 Gb/s by adaptive body biasing in a 28 nm FDSOI technology.

A new local clock generator for globally asynchronous locally synchronous MPSoCs

The evolution of technology into deep sub-micron domains leads to increasingly complex timing closure problems to design multiprocessor systems. One natural alternative is to resort to the globally asynchronous, locally synchronous paradigm. This work proposes a generic architecture for very low power- and area-overhead local clock generators (LCGs) to drive processors, network-on-chip routers and other intellectual properties (IPs). As one original contribution, the article details the design of a digitally controlled oscillator (DCO) which is the core of the LCG architecture. This DCO was designed using a CMOS 65 nm technology. It produces at least 16 distinct frequencies from 117 MHz to 1 GHz and supports clock gating and glitch-free frequency changes. The DCO design is robust to process, voltage and temperature variations, takes 850.6 µm2 and dissipates up to 197 µW. The article also proposes an LCG controller to improve frequency accuracy for IPs which require more accurate timing. Designed in the same technology, the controller takes 2250 µm2 and consumes 130 µW in typical conditions, or 160 µW, under worst-case conditions.

A Performance Comparison of CMOS Voltage-Controlled Ring Oscillators for its Application to Generation and Distribution Clock Networks

In this work, a performance comparison of expanded CMOS voltage-controlled ring oscillators for non-resonant local clock generation and distribution networks is presented. Several differential and single-ended ring oscillators are designed and fabricated using long interconnection lines to achieve wide coverage chip. A test chip containing the several oscillators was fabricated using an Austria Microsystems (AMS) 0.35 μm CMOS technology. Experimental results show that it is possible to generate and distribute high frequency signals (GHz range) on a relativity large area (coverage) and low phase noise using non-resonant ring oscillators. This represents an attractive alternative for the design and implementation of local Clock Generation and Distribution Networks for systems on chip.

Evaluation of Digital Crosstalk Noise on Differential Input Voltage Controlled Oscillator

With an increase in the operation frequency of complimentary metal oxide semiconductor (CMOS) circuits, a radio-frequency system-on-a-chip (RF-SOC) that integrates GHz-RF and large-scale digital circuits becomes a key device for wireless systems and high-speed networks. To develop high-performance RF-SOCs, high quality voltage controlled oscillators (VCOs) are required as local oscillators or clock generators, which operate in noisy environments suffering from crosstalk noise generated by digital circuits. A 0.25 µm CMOS test chip for a new differential-input VCO and a conventional single-input VCO was designed with on-chip CMOS logic noise sources and substrate noise detectors. The jitter and phase noise of the VCOs were measured to investigate the effect of substrate crosstalk noise. We confirmed that the differential-input VCO is robust to low-frequency noise in comparison with a conventional single-input VCO.

Design and component test of a tiny processor based on the SFQ technology

An eight-bit SFQ processor has been designed and some key components have been tested to confirm feasibility of the large-scale SFQ digital circuit. The designed processor is composed of a one-bit ALU, two eight-bit registers with local clock generators, an instruction register, a five-bit program counter, a state controller, and a 32-byte register file. A bit-serial architecture and a distributed local clock architecture, where each register has its own local clock generator, have been employed in order to increase the local clock frequency. The target clock frequency is 16 GHz and 10 GHz for the NEC 2.5 kA/cm/sup 2/ and Hypres 1 kA/cm/sup 2/ Nb processes. On the circuit design level, we have used a data-driven self-timed architecture and a binary decision diagram, which reduce the timing design difficulty in high frequency operation. The processor, which contains 7,300 Josephson junctions, has been designed by using a cell-based design methodology with the assistance of a top-down CAD environment. We have successfully tested some important circuit blocks, including a one-bit ALU, eight-bit registers, and a demultiplexer for register files.