LNA Design Research Articles

Design of Concurrent Dual Band Low Noise Amplifier for WLAN Applications

This paper presents a dual band LNA CMOS designed for a Wireless Local Area Network (WLAN) application using CMOS 0.13-µm Silterra technology. The proposed design incorporates forward body bias technique with cascode and notch filter configuration to achieve both low power consumption and high gain. The simulation results demonstrate a total power consumption of 2.39 mW at a low supply voltage of 0.5 V, with a gain of 16 dB at 2.4 GHz and 12 dB at 5.2 GHz. Additionally, input return loss of -12.3 dB and -14.2 dB with noise figures of 2.93 dBm and 4.23 dBm were obtained at 2.4 GHz and 5.2 GHz, respectively. Overall, this research contributes to the development of dual band LNA designs for WLAN applications.

Design of a broadband LNA with multifunction Circuitry based on composite right /left handed transmission lines for impedance matching and suppression of unwanted frequencies

This article presents a low-noise amplifier based on the use of a composite right-left handed transmission line consisting of a single microstrip line and a split ring resonator at the transistor input and output. This design ensures optimum matching over a wide frequency range while eliminating an unwanted frequency band. The circuit is designed to operate at a center frequency of 2.4 GHz while simultaneously eliminating the frequency band around 4.8 GHz, meeting key performance criteria including improved gain, better stability, and significant noise reduction. To achieve these objectives, the transistor used undergoes precise biasing via a DC power supply. In this process, a specifically selected capacitor is arranged in series with a λ/4 transformer. This transformer, in turn, is connected in series to a radial line section. The dimensions of the proposed amplifier are 70 × 34 mm2.For validation purposes, the proposed method was implemented through design, manufacture, and testing. The results obtained show that the proposed low noise amplifier achieves a high gain of 15.27 dB, an input reflection loss S11 of −16.26 dB, an output reflection loss S22 of −13.94 dB, and an inverse isolation S12 of −22.82 dB at 2.4 GHz, with a resonance peak at 4.8 GHz allowing the surrounding frequency band to be eliminated with an attenuation of 77 dB at 4.8 GHz. What's more, the noise figure is kept below 2 dB, with unconditional stability in the desired frequency band.

Highly Linear and Low Noise Shell Doped GaN Junctionless Nanotube TeraFET for the Design of Ultra-Wideband LNA in 6G Communications

Highly Linear and Low Noise Shell Doped GaN Junctionless Nanotube TeraFET for the Design of Ultra-Wideband LNA in 6G Communications

An efficient mm‐wave LNA impedance match synthesis methodology with coordinate descent method

AbstractIn this paper, a novel synthesis methodology for LNA impedance matching is proposed, which consists of two main phases: database generation and parameter optimization. In the former phase, a large‐scale sweep of electromagnetic simulations of passive components is performed to speed up parameter optimization. In the latter phase, the coordinate descent method is used as the optimizer of this methodology. Since frequently dozens of parameters need to be optimized in synthesize LNAs, the coordinate descent method can temporarily fix some parameters in each iteration, thus convert the optimization problem into multiple simple low or even one‐dimensional optimizations, which can eventually obtain high‐quality LNAs quickly in fewer descent iterations. This methodology is applied to a Ka‐band two‐stage differential LNA design using 65 nm CMOS technology, and the synthesis time is only 3 min, which is tens of times faster compared to existing synthesis methods. The proposed LNA circuit is fabricated and the measured results verify the feasibility of the synthesis method.

2.4 GHz Active Inductor Based Single to Differential LNA for WLAN Applications

This paper presents a source degenerated cascode low noise amplifier (LNA) design using a regulated cascode active inductor (AI). The AI has an inductance value of up to 6.28 nH, a Q-value of up to 4750, and a resonant frequency of up to 9.758 GHz. The proposed AI replaces the passive source degenerated inductor and load inductor in the LNA. Further, an active balun is used to have a differential signal at the LNA output to support the mixer stage. The gain and noise figure of the LNA is 22.2 and 5.6 dB respectively. The 3rd order input intercept (IIP3) value is 1.92 dBm and the return losses at the input port and two output ports are less than −10 dB. The power consumption of the circuit is 27 mW at a 1.8 V supply and the figure of merit (FoM) is 9.17. The area occupied by the AI is 39 × 72 µm2 and balun-LNA is 0.872 × 0.62 mm2. The complete proposed circuit is meant for wireless local area network (WLAN) applications in the 2.4 GHz frequency band.

A Hybrid GA/ML-Based End-to-End Automated Methodology for Design Acceleration of Wireless Communications CMOS LNAs

A new methodology for the RF/mmWave analog design process, automation and acceleration, is presented in this work. The proposed framework was implemented so as to accelerate the design cycle of analog/RF circuits by creating a dataset in a fully automated manner and training a combination of machine learning models for the optimal design parameters’ prediction. machine learning polynomial regression was adopted to accelerate the design process, predicting the optimal design parameters’ values while genetic algorithm optimization was exploited for the dataset creation automation. To evaluate the efficiency of the proposed methodology, the framework was implemented for the design of a common source Low-Noise-Amplifier, using a 65 nm CMOS process node. The proposed methodology successfully tackles the design cycle speed-up, automation, and acceleration, utilizing machine learning prediction for the design parameters and genetic algorithm for the dataset creation automation instead of the classical, simulation-based, standard design methodology. The provided experimental results have shown the effectiveness of the proposed hybrid approach, creating very precise RF matching networks for LNA designs and achieving >99.9% wave transmission efficiency while reaching >99% accuracy on the parameters’ prediction task.

Design of a Low Cost X-Band LNA with Sub-1-dB NF for SATCOM Applications

In this article, we demonstrate a low-cost 7.25-7.75 GHz two-stage low noise amplifier with sub-1-dB noise figure for satellite communication applications. The microstrip technology on Rogers RT5880 substrate with the dielectric constant of 2.2 and thickness of 0.508 mm were utilized to develop a low noise amplifier. The printed-circuit-board technology offers a variety of profits such as being low-cost, lighter-weight and re-configurability after the manufacturing process make this technology charming for satellite communication systems for both commercial and military applications. Since the monolithic microwave integrate circuit technology provide much smaller sized circuits and high electrical performance especially at the millimeter-wave frequencies, the printed microstrip technology can be a significant rival to integrated-circuit technology with its proven reliability, easier, cheaper and faster manufacturing process, compactible electrical performance in X-band applications. Moreover, the proposed amplifier was developed with utilizing California Eastern Laboratories’ CE3512K2 transistor on Rogers-RT5880 and surface mount devices were utilized in the matching networks to reduce the size. In addition, the source-generation and interstage matching topologies were implemented to simplify the matching complexity to enhance the noise and gain. The prototype was manufactured with utilizing LPKF prototyping machine. The developed LNA exhibits a measured gain of 23.5±0.5 dB with the noise figure of less than 0.9 dB and input/output return loss better than 11.5 dB in the operating frequency bandwidth. Furthermore, the developed amplifier has a measured carrier to interference of -59 dBc and P1dB of 13 dBm at the center frequency while consuming a total DC power of 50 mW.

Design of a Low-Voltage LNA with Considering Reliability and Variability Issues

Design of a Low-Voltage LNA with Considering Reliability and Variability Issues

LNA Design and Implementation for Passive Millimeter Wave Imaging System in Ka Band

Wydawnictwo SIGMA-NOT wydaje czasopisma fachowe informujące swoich czytelników o najnowszych osiągnięciach naukowych i nowoczesnych rozwiązaniach technicznych w Polsce i na świecie, popularyzuje problemy techniczne oraz poszerza wiedzę i kulturę techniczną.

A High-Gain CNTFET-Based LNA Developed Using a Compact Design-Oriented Device Model

Recently, carbon nanotube field-effect transistors (CNTFETs) have attracted wide attention as promising candidates for components in the next generation of electronic devices. In particular CNTFET-based RF devices and circuits show superior performance to those built with silicon FETs since they are able to obtain higher power-gain and cut-off frequency at lower power dissipation. The aim of this paper is to present a compact, design-oriented model of CNTFETs that is able to ease the development of a complete amplifier. As a case study, the detailed design of a high-gain CNTFET-based broadband inductorless LNA is presented.

Design and performance analysis of low power LNA with variable gain current reuse technique

This paper presents a CMOS low power Variable Gain Low Noise Amplifier for 26–34 GHz in 45 nm process technology, which composes of cascaded complimentary common gate (CCG) stage and digital current steering amplifier. First stage is CCG stage, which helps in achieving the low power consumption and less area. Second stage is variable gain amplifier, uses current reuse technique as well as gm-boost technique and has constant dc current to make the input impedance stable. Source degeneration technique cancel out MOS parasitic capacitance help in achieving linearity. Simulated maximum peak gain is 13.139 dB at 30.57 GHz and lowest peak gain is 7.75 dB at 26 GHz i.e. approximately flat over the entire band. Lowest NF is 3.08 dB at 32.6 GHz. Process corner simulation has been done for all four corners (S–S, S–F, F–S, F–F) showing robustness of LNA. Input return loss has value less than − 9.58 dB while output return loss has less than − 2.6 dB showing good matching; power consumption is 16 mW for dc current of 16 mA at 1 V. MOS active chip area is 76.727 µm2.

The Design and Simulation of Dual-band Beidou Navigation Receiver LNA

The Beidou satellite navigation receiver requires receiving multi-band signals to ensure more accurate and reliable positioning and navigation. According to the working frequency bands B3I and L1 of the system, we propose a low-noise amplifier which is based on Infineon’s BFP740FESD transistor. We employ the ADS software to simulate and optimize the low-noise amplifier input, and adopt the conjugate matching two-stage amplifier circuit. The simulation results show that the gain Gain ≧ 30dB in the L1 and B3 dual frequency band, the input and output standing wave ratio VSWR < 1.5, the noise coefficient < 1.0dB, and the out-of-band suppression is more than -40dB, which effectively reduces the out-of-band noise interference.

CMOS series-shunt single-pole double-throw transmit/receive switch and low noise amplifier design for internet of things based radio frequency identification devices

The incompatibility between current RFID standards has led to the need for universal and Wi-Fi compatible RFID for IoT applications. Such a universal RFID requires an SPDT and an LNA to direct and amplify the received raw signal by the antenna. The SPDT suffers from low isolation, high insertion loss and low power handling capacity whereas the LNA suffers from bulky die area, lesser Q factor, limited tuning flexibility etc. because of passive inductor usage in current generation of devices. In this research, nano-CMOS inductorless SPDT and LNA designs are proposed. The SPDT adopts a series-shunt topology along with parallel resonant circuits and resistive body floating in order to achieve improved insertion loss and isolation performance whereas the LNA design is implemented with the gyrator concept in which the frequency selective tank circuit is formed with an active inductor accompanied by the buffer circuits. The post-layout simulation results, utilizing 90nm CMOS process of cadence virtuoso, exhibit that our SPDT design accomplishes 0.83dB insertion loss, a 45.3dB isolation, and a 11.3dBm power-handling capacity whereas the LNA achieves a peak gain of 33dB, bandwidth of 30MHz and NF of 6.6dB at 2.45GHz center frequency. Both the SPDT and LNA have very compact layout which are 0.003mm 2 and 127.7 μm 2 , respectively. Such SPDT and LNA design will boost the widespread adaptation of Wi-Fi-compatible IoT RFID technology.

Design of Low-Power Reconfigurable LNA for Multi-Standard Receiver

Design of Low-Power Reconfigurable LNA for Multi-Standard Receiver

Design of Low Noise Amplifier for WLAN using pHEMT

The low power consumption devices are frequently focused in design and manufacturing wireless communication system. This paper gives a systematic design of a low noise amplifier for WLAN application aimed to obtain minimum noise figure. The simulation result shows that the noise figure is in the appreciable level (1.67 dB). The maximum gain is greater than 10 dB. These are the predominant requirements of an LNA. Also it posses good stability and the LNA design uses pHEMT for its appreciable noise performance. Â

Design of a tunable LNA and its variability analysis through surrogate modeling

AbstractIn this paper, a tunable low noise amplifier (LNA), which provides a bandwidth of 1 GHz, has been designed. The tunability of the LNA has been achieved by employing MOS varactors in accumulation mode. A shift in the LNA performance has been observed with the change in the total capacitance of the varactors through the control voltage. Starting from 2 to 3 GHz, the proposed tunable LNA provides a noise figure (NF) of less than 3 dB, a voltage gain of 12 dB and higher, while maintaining input and output power matching (S11 and S22) metrics at least below −12 dB. The total power consumption of the circuit is 23 mW. Moreover, two case studies that demonstrate the usage of surrogate modeling in RF circuit design have been described. Three‐ and six‐dimensional surrogate models have been built to illustrate the effect of bondwires on the variability of several LNA design metrics.

Pareto Optimal Characterization of a Microwave Transistor

Herein, noise, gain and port mismatchings of a microwave small-signal transistor are expressed as all the set of acceptable Pareto optimal solutions and trade-off relations within the device operation ( $\text{V}_{\mathrm {DS}}$ , $\text{I}_{\mathrm {DS}}$ , $f$ ) domain without any need of expert knowledge of microwave device. In this multi-objective optimization problem, non-dominated sorting genetic algorithm (NSGA) -III is applied to an ultra-low noise amplifier (LNA) transistor NE3511S02 (HJ-FET) where the noise $\text{F}_{\mathrm {req}}\ge \text {F}_{\mathrm {min}}$ and output mismatching $\text{V}_{\mathrm {outreq}} \ge 1$ are preferred as the reference points, while the input mismatching $\text{V}_{\mathrm {inopt}} \ge 1 $ and gain $\text{G}_{\mathrm {Tmax}}$ are optimized with respect to source $\text{Z}_{\mathrm {S}}$ and load $\text{Z}_{\mathrm {L}}$ within the unconditionally stable working area. Thus, diverse set of the Pareto optimal (the required noise $\text{F}_{\mathrm {req}}$ , the optimum input $\text{V}_{\mathrm {inopt}}$ , the required output $\text{V}_{\mathrm {outreq}}$ , the maximum transducer gain $\text{G}_{\mathrm {Tmax}}$ ) quadruples are resulted from a fast search of the solution space. Furthermore, the optimum bias condition ( $\text{V}_{\mathrm {DS}}$ , $\text{I}_{\mathrm {DS}}$ ) and sensitivities of the terminations to fabrication tolerances are also determined using the cost analysis in the operation domain for the required $\text{P}_{\mathrm {max}}$ , $\text{I}_{\mathrm {DSmax}}$ and performance quadruple. Finally, this work is expected to enable a designer to provide the feasible design target space (FDTS) consisting of all trade-off relations among all the transistor’s performance ingredients to be used in the challenging LNA designs.

Full flexible performance characterization of a feedback applied transistor with LNA applications

SummaryIn this paper, the full flexible performance characterization of a transistor with series inductive/parallel capacitive feedback is carried out in terms of LNA applications. For this purpose, the input VSWR Vin–maximum available gain GTmax variations are constructed for a high technology low‐noise transistor that is subject to the required noise figure Freq(f) ≥ Fmin(f) along the device's operation band depending on the feedback. These Vin–GTmax variations result in the application of a design chart that indicates which value of feedback can be applied within which region of the operation band with the improvable trade‐off between the Vin and output VSWR Vout for the Freq(f) ≥ Fmin(f). Following this, the optimum trade‐off between Vin and Vout is made for the necessary operation frequency regions using the load impedance ZL as an instrument with the predetermined source impedance ZS. Finally, the LNA applications of a series inductive/parallel capacitive feedback applied transistor with the optimum Vin, Vout, and GT subject to Freq(f) ≥ Fmin(f) ≥ are also presented as distributed across the entire bandwidth in the different operation bands. It can be concluded that this rigorous work will enable a designer to utilize the entire operation frequency band of transistor through using only a single series inductive/parallel capacitive feedback for the LNA designs of Freq(f) ≥ Fmin(f) with the optimum trade‐offs among its performance measures.

Design of High Stability Factor Lna using Cascade Mosfet at 850MHz Rf Frequency

Controlling noise is the primary effort in any amplifier. LNA (Low Noise Amplifier) will control the noise in front panel of amplifier stage as per FRISS law. Instead of single MOS in LNA , cascaded the MOS generates the stability factor in a better way in 850MHz RF frequency at load impedance of 50Ω. But additionally capacitor inserted cascaded MOS will pull down the stability factor. Cascasded MOS LNA have a stability factor of 1.387 and Noise Figure(dB) of 0.518

Design of Differential LNA and Double Balanced Mixer using 180 nm CMOS Technology

The RFICs plays an important role in wireless communication systems due to their effective operation in the 2.4 GHz frequency, popularly known as ISM (Industrial, Scientific and Medical) band. LNA and Mixers are the major components used in transceivers for the purpose of amplification and frequency translation. Such LNAs and mixers are of different kinds and various techniques are used for their optimization. The paper describes the design of a differential LNA with two single stranded source degenerate LNAs with greater increase in gain. differential LNA is combined with Double balanced mixer with a current mirror circuit and BALUN with the bias controlling MOSFETs are used to show the better performance at 2.4 GHz frequency range. CMOS has become a viable technology for the design of high-performance receivers in the Radio Frequency (RF) regime. The conversion gain of 22.28 dB and IF of 595 MHz of Differential LNA with Double Balanced mixer are higher than the cross comparison results of the other methods at 180 nm technology. CMOS implementation of the design is done using the Cadence Virtuoso tool of 180 nm technology at 2.4 GHz frequency and 1.8 V of supply voltage.