Node Lithography Research Articles

Advances in laboratory-scale ptychography using high harmonic sources [Invited

Extreme ultraviolet microscopy and wavefront sensing are key elements for next-generation ultrafast applications, such as chemically-resolved imaging, focal spot diagnostics in pump-and-probe experiments, and actinic metrology for the state-of-the-art lithography node at 13.5 nm wavelength. Ptychography offers a robust solution to the aforementioned challenges. Originally adapted by the electron and synchrotron communities, advances in the stability and brightness of high-harmonic tabletop sources have enabled the transfer of ptychography to the laboratory. This review covers the state of the art in tabletop ptychography with high harmonic generation sources. We consider hardware options such as illumination optics and detector concepts as well as algorithmic aspects in the analysis of multispectral ptychography data. Finally, we review technological application cases such as multispectral wavefront sensing, attosecond pulse characterization, and depth-resolved imaging.

Hexagonal Superalignment of Nano-Objects with Tunable Separation in a Dilute and Spacer-Free Solution.

Manipulating building-block nanomaterials to form an ordered superstructure in a dilute and spacer-free solution phase challenges the existing 5-nm node lithography and nanorobotics. The cooperative nature of nanocrystals, polymers, and cells can lead to superarrays or colloidal crystals. For known highly ordered systems, the characteristic length of materials, defined as the shortest dimension of objects, is generally larger than their separations. A spacer (small-molecule surfactant or polymer) is typically required to diminish short range van der Waals attraction, which results in a glassy or liquid state. Herein we propose a new concept of achieving highly ordered nano-objects in a dilute and spacer-free system via the synergistic effects of excellent solvation and appropriate constraints on rotational motion. As a proof of concept, this study demonstrates that aluminosilicate nanotubes (AlSiNTs) suspended in water under dilute conditions (e.g., 1.0wt%) can spontaneously form hexagonal arrays with an intertubular distance as large as tens of nanometers. The separation distance of the ordered superstructure is also tunable via controlling the concentration and length of nanotubes. These superaligned structures are probed using small-angle x-ray scattering and cryo-TEM characterizations, with underlying mechanisms investigated at an atomic level using molecular dynamics simulations. The concept and discovery of this work can open up opportunities to a variety of applications including visible-UV photonics and nanolithography, and may be generalizable to other nano-object systems that fulfill similar requirements.

Plasmonic Interference Lithography for Low-Cost Fabrication of Dense Lines with Sub-50 nm Half-Pitch

Limited by the cost and complexity, a sub-50 nm lithography node is hard to achieve through the traditional interference lithography. In this paper, the dense lines with half-pitch of 32 nm (∼λ/11) and 22 nm (∼λ/16) are first achieved at the wavelength of 365 nm by simple plasmonic interference lithography. Through selecting the high spatial frequency plasmonic modes in Al/Photoresist (Pr)/Al waveguide and allowing interference with each other, the deep subwavelength plasmonic interference field could be obtained in Pr film. Moreover, the lithography structure is separated from the mask, so etch transfer process from Pr to substrate after lithography is easy to attain, and the mask with high cost could be used multiple times. Meanwhile, a near-field lithography setup was developed, and we experimentally realized the comparatively distinct lithography fringes with the half-pitch of 32 and 22 nm when there is an air gap smaller than ∼20 nm between mask and the lithography films. Compared with the imaging li...

Mark van de Kerkhof: Enabling sub-10nm node lithography: presenting the NXE:3400B EUV scanner with improved overlay, imaging, and throughput

Mark van de Kerkhof: Enabling sub-10nm node lithography: presenting the NXE:3400B EUV scanner with improved overlay, imaging, and throughput

Three-dimensional integration: An industry perspective

Abstract

(Invited) Towards 0.7 Terahertz Silicon Germanium Heterojunction Bipolar Technology – The DOTSEVEN Project

DOTSEVEN is a very ambitious 3.5 year R&D project targeting the development of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) technologies with cut-off frequencies (fmax) of around 700 GHz. The project is publically funded within the European Union's Seventh Framework Program for Research (FP7). It started in October 2012 and is now at the beginning of its second year. 10 out of the 12 DOTSEVEN participants were already partnering in the predecessor FP7 project DOTFIVE which succeeded for the first time to push fmax of SiGe HBTs (at room temperature) into the 500 GHz region thus setting a new world-wide benchmark.For a given lithography node, SiGe HBTs provide much higher cut-off frequencies compared to CMOS transistors while offering higher power density and better analog performance. Although ITRS roadmaps [1] predict ever increasing cut-off frequencies for CMOS transistors up to the THz region, there are indications [2,3] that at least fmax will saturate around the 28 nm node at 300-400 GHz (depending on the extraction methodology) and will even drop beyond that node due to parasitic gate resistance [Figure 1]. Thus SiGe HBT technology and SiGe HBT enhanced CMOS (SiGe BiCMOS) will be key enablers for demanding mm-wave systems requiring more than a few µWatts of RF output power (which limits the applicability of even very advanced CMOS) and also offer high integration levels at low cost which precludes expensive and less integrated III-V solutions. Physics based simulations predict “balanced” fT/fmax limits of well above 1 THz for SiGe HBTs [4]. In DOTFIVE the practical performance limits of lateral and vertical scaling of standard HBT topologies which are in use in 200-300 GHz production processes at STM and IFX have shown up clearly. With these conventional DPSA (double poly self aligned) emitter / base structures incorporating an external poly-silicon base-contact which is vertically linked to the SEG (selectively grown) SiGe:C base layer, we were not able to surpass a “400 GHz” limit of fmax significantly [5]. Reaching 500 GHz was only possible with two new transistor architectures realized by IHP employing novel “lateral base-link” [6] or “epitaxial external base-contact” concepts [7] which will be utilized in DOTSEVEN as starting point as they have potential to overcome a basic weakness of conventional DPSA structures: their relatively high-resistive external base-link region [8,9].Within the project the capabilities and benefits of >500 GHz SiGe HBT technology will be demonstrated by benchmark circuits and advanced system applications in the 0.1 to 1 THz range like THz imaging and sensing, wireless Gb/s communications and millimeter-wave radar. Process development will be strongly supported by TCAD and physics-based modeling including 3D, nanoscale and thermal effects where as "first-time-right" circuit design will be enabled by accurate compact device modeling including electro-thermal, substrate and other parasitic effects. Of course these models have to be based on accurately extracted parameter sets for which in turn accurate and reliable characterization and extraction methodologies are mandatory. High current densities, excessive self-heating and operation at collector-emitter voltages above the open-base VCE breakdown limit might impose considerable reliability risks in downscaled HBTs and limit their practical application. Therefore in-depth reliability modeling and investigations will be undertaken in the project too.

Compact-sized high-modulation-efficiency silicon Mach-Zehnder modulator based on a vertically dipped depletion junction phase shifter for chip-level integration.

We present small-sized depletion-type silicon Mach-Zehnder (MZ) modulator with a vertically dipped PN depletion junction (VDJ) phase shifter based on a CMOS compatible process. The fabricated device with a 100 μm long VDJ phase shifter shows a VπLπ of ∼0.6 V·cm with a 3 dB bandwidth of ∼50 GHz at -2 V bias. The measured extinction ratios are 6 and 5.3 dB for 40 and 50 Gb/s operation under 2.5 Vpp differential drive, respectively. On-chip insertion loss is 3 dB for the maximum optical transmission. This includes the phase-shifter loss of 1.88 dB/100 μm, resulting mostly from the extra optical propagation loss through the polysilicon-plug structure for electrical contact, which can be readily minimized by utilizing finer-scaled lithography nodes. The experimental result indicates that a compact depletion-type MZ modulator based on the VDJ scheme can be a potential candidate for future chip-level integration.

Progress in Extending Immersion Lithography for the 32 nm Node and Beyond

Optical lithography has met the challenge of the Semiconductor Industry's increasing resolution and the tighter overlay requirements by progressively: increasing the optics numerical aperture; shortening the illumination wavelength; and supporting low-k factor processing. This trend continued with the wavelength being shortened to 13 nm for extreme ultraviolet (EUV) lithography tools, and with numerical apertures increased to 1.35 for water-based immersion lithography tools. Currently, water-based, 193 nm, immersion tools are capable of printing at <40 nm (half pitch) resolutions with <6 nm overlay accuracy. For the next lithographic nodes, water-based immersion lithography will be used with double patterning techniques, and this will pushdown to below the 32 nm node. The major challenges for the exposure tools are the tightening of the specifications required with double pattering, while dealing with shrinking process windows. The specifications requirements include increased throughput, tighter overlay, and tighter critical dimension control. New high-speed systems are being developed at ASML to meet these requirements. This paper reviews the possibility of using double patterning to extend immersion lithography tools, beyond the 32 nm node while production EUV lithography is coming on line.

On the Performance Limits of Cryogenically Operated SiGe HBTs and Its Relation to Scaling for Terahertz Speeds

The goal of achieving terahertz (THz) transistors within the silicon material system has generated significant recent interest. In this paper, we use operating temperature as an effective way of gaining a better understanding of the performance limits of SiGe HBTs and their ultimate capabilities for achieving THz speeds. Different approaches for vertical profile scaling and reduction of parasitics are addressed, and three prototype fourth-generation SiGe HBTs are compared and evaluated down to deep cryogenic temperatures, using both dc and ac measurements. A record peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 463/618 GHz was achieved at 4.5 K using 130-nm lithography (309/343 GHz at 300 K), demonstrating the feasibility of reaching half-THz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> simultaneously in a silicon-based transistor. The BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> of this cooled SiGe HBT was 1.6 V at 4.5 K (BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CBO</sub> = 5.6 V), yielding a record f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> times BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> product of 750 GHzldrV (510 GHzldrV at 300 K). These remarkable levels of transistor performance and the associated interesting device physics observed at cryogenic temperatures in these devices provide important insights into further device scaling for THz speeds at room temperature. It is predicted in a new scaling roadmap that f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of room-temperature SiGe HBTs could potentially achieve 782/910 GHz at a BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> of 1.1 V at the 32-nm lithographic node.

Modelling strategies for the incorporation and correction of optical effects in EUVL

Extreme ultraviolet lithography (EUVL) is a leading candidate for the 22 nm node lithography and beyond. However, there are still some critical problems before EUVL may be deployed in high-volume manufacturing. One of the critical problems is to estimate the EUVL aerial image formation for optical proximity correction (OPC) in order to compensate for EUVL effects such as shadowing and flare. This study discusses aerial image formation through modeling of optical transfer function to assimilate optical diffraction, long range layout dependent flare effects, and shadowing effects due to non-telecentric imaging optics in the EUV case. Hence, after optimizing optical process parameters to model the EUV aerial image, this study will investigate OPC modeling methods employed to compensate these optical effects in the mask design flow.

Novel method for characterizing resist performance

The use of a single figure of merit to judge resist performance with respect to resolution, linewidth roughness LWR, and sensitivity is proposed and evaluated. Chemically amplified photoresists used in advanced lithography nodes need to fulfill stringent requirements for a considerable number of resist and process characteristics. Along with resolution, linewidth roughness and resist sensitivity are important examples where the specifications have become very tight. Previously, it has been shown that resolution, linewidth roughness, and resist sensitivity are fundamentally interdependent. Hence, when evaluating or optimizing resist performance, it is very important to take these three characteristics into consideration simultaneously. We propose to combine these characteristics into a single photoresist figure of merit KLUP. This figure of merit, which is determined from sizing dose, imaging wavelength, resist thickness, exposure latitude, acid diffusion length, linewidth roughness, and pitch, allows for a direct comparison of very different resist formulations independent of the exposure tool used. Thus, KLUP has great potential to assist in evaluating resist performance for the next lithography nodes, for both ArF and for EUV wavelengths.

The role of MEMS in maskless lithography

The challenges for maskless lithography at several wafers per hour at the 45–32 nm lithography node are analyzed. The conclusion is that such speed is only obtainable with systems based on massive parallelism, whether the principle is based on light optics, electron optics or atomic force microscopes. The construction of such systems demands the use of micro-electro-mechanical systems (MEMS). Different concepts employing MEMS are reviewed. Typical requirements for the manufacturing of the MEMS components are analyzed for a multi-column electron beam concept such as the MAPPER system. Examples of successfully fabricated array structures are shown.

Projection mask-less lithography (PML2): First results from the multi beam blanking demonstrator

A proof-of-concept multi beam blanking device (“blanking demonstrator”) has been fabricated for the projection mask-less lithography project. It comprises a Si chip with approx. 4000 openings (each has a size of 8 × 8 μm 2) etched through with adjacent blanking electrodes fabricated by electroplating. The parameters of the blanking demonstrator such as electrode layout and density of openings are identical to the blanking device of the final production tool. The demonstrator is being tested within a dedicated broad beam electron beam teststand, which has proven to resolve <2 μrad angular deviation. First experiments with the demonstrator showed a blanking sensitivity of 145–165 μrad/V which is best suited for the driving voltage of CMOS circuits. Cross talk through individual switching of nearest neighbor openings has been determined to be <(1.3 ± 0.1) μrad/V electrode potential. This is well below the cross talk target specified for 45 nm node lithography.

Development of new resist materials for 193-nm dry and immersion lithography

We have earlier developed mono cyclic fluoropolymers, FPRs and FUGUs, for the base resin of the resist for 157-nm lithography. However, considering the fact that the semiconductor industry is marching toward 193-nm immersion lithography for the next generation lithography node in place of 157-nm lithography, we have begun to apply 157-nm fluoropolymer materials to 193-nm applications. The major problem to use fluoropolymer backbones for 193 nm is their poor dry etching resistance. In this paper, we describe a new series of fluorinated copolymers for 193-nm lithography, a combination of FUGU monomer and several types of acrylates. We found that dry etching resistance of them was improved while keeping excellent transparency and these polymers show high sensitivity toward exposure light and good dissolution behavior.

Resist effects at small pitches

The ITRS roadmap and Moore’s law are driving us to print ever smaller features and ever tighter pitches. For these ultrasmall features and pitches, resist effects are expected to play a dominant role in limiting the overall lithographic process capability. To study the impact of resist parameters such as acid diffusion and quencher level on the lithographic performance, we have designed and formulated a matrix of 14 extreme ultraviolet (EUV) resists. In this article, we discuss results that we have obtained from EUV exposures of those resists on the 0.3 numerical aperture EUV Micro Exposure Tool at the Advanced Light Source at Lawrence Berkeley National Laboratories. In addition to exposure latitude and line edge roughness, acid diffusion lengths were characterized using a modification of the extended Nijboer–Zernike theory for each photoresist. A simple theory for the drop in resist contrast as function of the diffusion length is tested and leads to a verified correlation between exposure latitude and diffusion length. This theory gives guidelines to predict what acid diffusion lengths should be used for a certain lithography node. Line edge roughness analysis showed that shot noise statistics are present, and also points out that acid diffusion effects come into play. From the experimentally observed tendencies in this unique matrix of EUV photoresists, fundamental understanding was gained about prominent resist effects that will determine the lithographic performance of resist processes in future lithography nodes.

Predicting electron projection lithography mask membrane image placement errors

Electron projection lithography (EPL) has been identified as a viable candidate of the next-generation lithography technologies for moderate-volume production of systems-on-a-chip for the sub-65nm nodes. EPL is especially suited for the fabrication of contact structures. The development of a low-distortion mask is essential for meeting the stringent requirements at these lower nodes. This research focuses on quantifying in-plane distortions (IPDs) due to mask fabrication and the effects of different mounting schemes in the e-beam writer and exposure tools for a 200mm EPL stencil mask. In order to quantify the IPD of the freestanding membranes, three-dimensional finite element (FE) models have been developed and benchmarked with experimentally measured data. Metrology measurements in both the membrane-side up and membrane-side down configurations can be used to correct for image placement errors (due to the fabrication and chucking of the mask) by compensating for IPD during the exposure process. To correct for higher order distortions associated with pattern specific errors, FE models were generated to simulate the entire process flow, including chucking. As a sample test case, a stencil pattern was replicated uniformly over the membrane arrays. The actual mask was fabricated and metrology measurements were taken. Selected membranes were experimentally measured to compare with FE results and the data correlated well in both direction and magnitude. Results illustrate that FE modeling and simulation can be used to predict mask distortions due to fabrication. Such techniques can be instrumental in meeting the stringent error budget required at the lower lithographic nodes.

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Water-based immersion lithography using ArF illumination is able to provide optical solutions as far as the 45-nm node, but is not able to achieve the 38- or 32-nm nodes as currently defined. Achieving these lithographic nodes will require new, higher refractive index fluids to replace the water used in first-generation immersion systems. We have developed a number of such second-generation high-index fluids for immersion lithography at 193 nm. These highly transparent fluids have 193-nm indices up to 1.664. To understand the behavior and performance of different fluid classes, we use spectral index measurements to characterize the index dispersion, coupled with Urbach absorption edge analysis and Lorentz Oscillator modeling. Interference imaging printers have long been available, and they now have a new use: a rapid, cost-effective way to develop immersion lithography, particularly at extremely high resolutions. Although interference printers will never replace classical lens-based lithography systems for semiconductor device production, they do offer a way to develop resist and fluid technology at a relatively low cost. Their simple image-forming format offers easy access to the basic physics of advanced imaging. Issues such as polarization of the image-forming light rays, fluid/resist interaction during exposure, topcoat film performance, and resist line edge roughness (LER) at extremely high resolutions, can all be readily studied. 32-nm 1:1 line/space (L/S) imaging is demonstrated using two of the second-generation fluids. These resolutions are well beyond current lens-based system capabilities. Results on the performance of various resists and topcoats are also reported for 32-nm L/S features.

Optical Lithography for the 32nm Node

The 32nm lithography node is the next major target for optical lithography on the Semiconductor Industry Roadmap. The recently developed water-based immersion lithography using ArF illumination will be able to provide an optical solution for lithography at the 45nm node, but it cannot achieve the 32nm node as currently defined. EUV is the main solution for the 32nm node, but the evolution of immersion lithography does represent an opportunity to extend ArF lithography down to the 32nm node.This paper reports progress towards achieving 32nm lithography using immersion lithography. To achieve this next lithographic node will require new, very high refractive index fluids to replace the water used in current immersion systems.Testing and experiments to develop key technology for the 32nm node are reported. These experiments were run using interference immersion lithography.Interference imaging printers have been available for years, and with the advent of immersion lithography have a new use. Interference immersion image printing offers the user a rapid, cost-effective way to develop immersion lithography, particularly at extremely high resolutions. Although it can never replace classical lens-based lithography systems for semiconductor device production, it does offer a way to develop resist and fluid technology at a relatively low cost. Its simple, image-forming format offers easy access to the basic physics of advanced imaging. Issues such as: fluid/resist interaction during exposure; topcoat film performance; line edge roughness of resists at extremely high resolutions; and the polarization of the image-forming light rays can all be readily studied.Experiments are described and results are provided for work on: 32nm imaging tests; high refractive index fluid testing using ArF wavelength at resolutions well beyond current lens-based system capabilities; and polarization configuration testing on both 32nm and 45nm L/S features.

Electron-beam-based photomask repair

High-resolution electron-beam-assisted deposition and etching is an enabling technology for current and future generation photomask repair. NaWoTec in collaboration with Carl Zeiss NTS (formerly LEO Electron Microscopy) has developed a mask repair tool capable of processing a wide variety of mask types, such as quartz binary masks, phase shift masks, extreme ultraviolet masks, and e-beam projection stencil masks. Specifications currently meet the 65nm device node requirements, and tool performance is extendible to 45nm and below. The tool combines LEO’s ultra-high-resolution Supra scanning electron microscope platform with NaWoTec’s proprietary e-beam deposition and etching technology, gas delivery system, and mask repair software. In this article, we focus on tool performance results; that is, the reproducibility and accuracy of repair of clear and opaque programmed defects on Cr binary and MoSi phase shift masks. These masks have in the past been difficult to repair due to beam position instability caused by charging of the insulating quartz areas. We have found and implemented a solution to this charging problem and have demonstrated in spec repair of various defect types. The extendibility of e-beam-based repair technology to future lithography nodes, both in terms of the required resolution and the ability to repair next generation lithography mask types, will also be addressed.

Ultrathin membrane masks for electron projection lithography

Electron projection lithography (EPL) is one of the leading candidates for next-generation lithography at the 65-nm lithography node, particularly for contact levels. EPL has traditionally employed either an open stencil mask with a single patterned (perforated) scattering layer or a continuous membrane mask with a patterned scattering layer supported by an un-perforated membrane. This article reports on an experimental study of a type of EPL mask developed by Team Nanotec that employs a continuous ultrathin membrane (UTM) comprised of a trilayer of carbon, silicon nitride, and carbon. These UTM masks combine all of the benefits of continuous membrane masks with the higher energy throughput (and the smaller chromatic aberration) of an open stencil mask.