Literal Circuit Research Articles

Design of SRAM with CNFET based on ternary literal circuit

Design of SRAM with CNFET based on ternary literal circuit

Design and Implementation of Hybrid Multiple Valued Logic Error Detector using Single Electron Transistor and CMOS at 120nm Technology

Hybridization of single electron transistor with MOSFET using quaternary logic for the design of Down Literal circuits are introduced here due to which the number of components as well as interconnection complexity will gets reduced just by designing the proper values of components of individual SET such as capacitor and resistors and by changing the values of W/L ratio of MOSFETS. This DLC’s are used for the design of hybrid quaternary logic error detector and verified by CADENCE Tool.

Design of ternary counter based on adiabatic domino circuit

By researching the ternary counter and low power circuit design method, a novel design of low power ternary Domino counter on switch-level is proposed. Firstly, the switch-level structure expression of ternary loop operation circuit with enable pin is derived according to the switch-signal theory, and the one bit ternary counter is obtained combining the ternary adiabatic Domino literal operation circuit and buffer. Then the switch-level structure expression of enable signal circuit is derived, and the four bits ternary counter is obtained by cascade connection. Finally, the circuit is simulated by Spice tool and the output waveforms transform in proper order indicating that the logic function is correct. The energy consumption of the four bits ternary adiabatic Domino counter is 63% less than the conventional Domino counterpart.

Voltage-Mode Multi-Valued Schmitt Trigger with Neuron-MOS Transistors

A novel design scheme of multiple-valued Schmitt trigger using neuron-MOS transistors is presented. By controlling the voltages of the multiple-input gates, the neuron-MOS literal circuits with hysteresis characteristics are firstly designed. Then, the transmission switches used to pass quaternary signal are controlled by the outputs of these literal circuits to realize three hysteresis loops of quaternary Schmitt circuit. The benefit of the proposed quaternary Schmitt trigger is that the circuit can be fabricated by standard CMOS process with a 2-ploy layer. The three hysteresis loops are fully adjustable by sizing the ratio of capacitive coupling coefficients. The effectiveness of the proposed Schmitt trigger has been validated by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology, and the discrepancy of hysteresis values between the simulated and theoretical results is smaller than 6%.

A novel ternary JK flip-flop using the resonant tunneling diode literal circuit

A literal circuit with a three-track-output structure is presented based on resonant tunneling diodes (RTDs). It can be transformed conveniently into a single-track-output structure according to the definition and properties of the literal operation. A ternary resonant tunneling JK flip-flop is created based on the RTD literal circuit and the module-3 operation, and the JK flip-flop also has two optional types of output structure. The design of the ternary RTD JK flip-flop is verified by simulation. The RTD literal circuit is the key design component for achieving various types of multi-valued logic (MVL) flip-flops. It can be converted into ternary D and JK flip-flops, and the ternary JK flip-flop can also be converted simply and conveniently into ternary D and ternary T flip-flops when the input signals satisfy certain logical relationships. All these types of flip-flops can be realized using the traditional Karnaugh maps combined with the literal and module-3 operations. This approach offers a novel design method for MVL resonant tunneling flip-flop circuits.

Design of a Capacitive Detection Circuit using MUX and DLC based on a νMOS

This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

A Study of a High Performance Capacitive Sensing Scheme Using a Floating-Gate MOS Transistor

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 μm standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit

The problems existing in the binary logic system and the advantages of multiple-valued logic (MVL) are introduced. A literal circuit with three-track-output structure is created based on resonant tunneling diodes (RTDs) and it has the most basic memory function. A ternary RTD D flip-flop with pre-set and pre-reset functions is also designed, the key module of which is the RTD literal circuit. Two types of output structure of the ternary RTD D flip-flop are optional: one is three-track and the other is single-track; these two structures can be transformed conveniently by merely adding tri-valued RTD NAND, NOR, and inverter units after the three-track output. The design is verified by simulation. Ternary flip-flop consists of an RTD literal circuit and it not only is easy to understand and implement but also provides a solution for the algebraic interface between the multiple-valued logic and the binary logic. The method can also be used for design of other types of multiple-valued RTD flip-flop circuits.

All-optical quaternary Galois field sum of product (GFSOP) circuits

Quaternary Galois field (QGF) arithmetic has a great contribution in future computation in the field of multi-valued logic (MVL). Any multi-valued logical function having many input variables express Galois field sum of product (GFSOP) expression easily. In this paper, all-optical circuits of two Galois field arithmetical operations (addition and product) are proposed and described. All-optical basic reversible quaternary literal circuits using GFSOP expression is also proposed. In this present scheme the different quaternary logical states are represented by different polarized state of light. Terahertz Optical Asymmetric Demultiplexer (TOAD) based interferometric switch takes an important role in this manuscript.

Arithmetic Operations in Multi-Valued Logic

This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.

Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits

A fine-grain bit-serial multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed for effective use of the hardware resources. In logic-in-control architecture, the control circuits can be merged with the arithmetic/logic circuits, where the control and arithmetic/logic circuits are constructed by using one or multiple logic blocks. To implement the control circuit, only one state in a state transition diagram is allocated to one logic block, which leads to reduction of the complexity of interconnections between logic blocks. The fine-grain logic block is implemented based on multiple-valued current-mode circuit technology. In the fine-grain logic block, an arbitrary 3-variable binary function can be programmed by using one multiplexer and two universal literal circuits. Three-variable binary functions are used to implement the control circuit. Moreover, the hardware resources can be utilized to construct a bit-serial adder, because full-adder sum and carry can be realized by programming in the universal literal circuit. Therefore, the logic block can be effectively reconfigured for arithmetic/logic and control circuits. It is made clear that the hardware complexity of the control circuit in the proposed reconfigurable VLSI can be reduced in comparison with that of the control circuit based on a typically sequential circuit in the conventional FPGA and the fine-grain field-programmable VLSI reported until now.

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation

A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit-serial reconfigurable computation is proposed. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a simple logic block can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple-valued signaling, where superposition of serial data bits and a start signal which indicates heading of one-word is introduced. Differential-pair circuits are also effectively employed for current-output replication, which leads to high-speed signaling to adjacent cells The evaluation is done based on 90 nm CMOS design rule, and it is made clear that the area of the proposed cell can be reduced to 78% in comparison with that of the CMOS implementatiuon. Moreover, its area-time product becomes 92% while the delay time is increased by 18%.

Multiple-valued signed digit adder using negative differential resistance devices

The paper describes a signed digit full adder (SDFA) circuit consisting of resonant tunneling diodes (RTDs) and metal oxide semiconductor field effect transistors (MOSFETs). The design is primarily based on a multiple valued logic literal circuit that utilizes the folded back I-V (or negative differential resistance, NDR) characteristics of RTDs to compactly implement its gated transfer function. MOS transistors are configured in current mode logic, where addition of two or more digits is achieved by superimposing the signals of individual wires being physically connected at the summing nodes. The proposed SDFA design uses redundant arithmetic representation and therefore, the circuit can perform addition of two arbitrary size binary numbers in constant time without the need for either carry propagation or carry look-ahead. The SDFA cell design has been verified through simulation by an augmented SPICE simulator that includes new homotopy based convergence routines to tackle the nonlinear device characteristics of quantum devices. From the simulation result, the SDFA cell has been found to perform addition operation in 3.5 nanoseconds, which is somewhat superior to other multivalued redundant arithmetic circuits reported in the literature. The SDFA cell requires only 13 MOS transistors and one RTD, as opposed to the state of the art CMOS redundant binary adder requiring 56 transistors, and to the conventional multivalued current mode adder consisting of 34 MOS transistors. In order to verify the simulation result, a prototype SDFA cell has been fabricated using MOSIS 2-micron CMOS process and GaAs based RTDs connected externally to the MOSFET circuit.

Mask-programmable multiple-valued logic gate using resonant tunnelling diodes

The design of a 1-input and a 2-input 4-valued logic gate is described. These gates can be used to implement cells of a gate array, with the benefit of having programmable functionality and multiple-valued logic input and output lines. Programmable functionality allows any of the four billion functions of a 2-input 4-valued logic gate to be implemented by the same cell, and multiple-valued logic signal lines can reduce the area needed to be reserved for intercell routing. A key component of these cells is the resonant tunnelling diode, an ultrafast and small quantum electronic device that can be used in conjunction with HBTs to make compact literal circuits and decoders. So far as non-gate-array implementations are concerned, compactness can be improved further by a simple algorithm, also presented by the authors, to discard redundancies in the gate structure.

An optimization technique for the design of multiple valued PLA's

An optimization technique for the design of two types of multiple-valued PLAs is described. In a type-I PLA, the multiple-valued function is realized directly, whereas in a type-II PLA, output encoding is used to encode the binary output of the PLA. In both types, multiple function literal circuits are used for the purpose of minimization. It is shown that the proposed technique leads to a considerably reduced size of PLA when compared to the earlier techniques. >

Design and evaluation of a current-mode multiple-valued PLA based on a resonant tunnelling transistor model

A resonant tunnelling transistor (RTT) model is defined. The current-voltage characteristic of the model can have multiple peaks, and the widths of each peak and valley can be set to any value. A multiple-valued universal literal (MVUL) circuit using the RTT model is presented as a basic building block in a multiple-valued programmable logic array (MVPLA). An MVPLA structure based on MVUL, AND, MIN, and linear sum operators is proposed for the implementation of multiple-valued systems. Since the MVUL circuit is designed using only one transistor, and the other basic building blocks are implemented by simple current-mode circuits, the proposed MVPLA becomes very compact. The layouts and SPICE simulations show that the proposed MVPLA is superior to other types of PLA in terms of size, delay and dynamic power dissipation if the RTT model is realised by an actual device.

Design of a low‐power universal literal circuit

AbstractIn the universal literal circuit (ULC) previously proposed, since the two threshold values of the literal circuit are variable by external control signals, four‐valued logic circuits have attracted considerable attention. However, to realize LSI, there was room for improvement from the viewpoint of power consumption.In this paper, as a literal, with the other characteristics remaining the same, a new low‐power ULC circuit with power consumption decreased by 1/285 is proposed. Also, the threshold voltage variation due to the body‐effect of MOS transistors, having a critical influence on the level discrimination characteristics of the circuit, is solved by introducing body‐effect compensating transistors. Moreover, by SPICE simulation, it is verified that the low‐power ULC works satisfactorily.

A current‐mode multivalued logic circuit based on by Bi‐CMOS transistors

AbstractThis paper proposes a Bi‐CMOS current‐mode multivalued logic circuit enabling high‐accuracy computation, high‐speed computation, and high integration. In conventional current‐mode multivalued logic circuits using I2L and CMOS configurations, the realization of high‐radix multivalued logic circuits was difficult due to the calculation errors in the basic circuits, such as a current mirror or subthreshold detector.As a result of simulations of the basic circuits proposed in this paper using an electronic circuit analysis program SPICE2, a 16‐valued logic circuit has been shown to be possible with 0.8‐m̈m process even considering the variation in device parameters. As an application of these basic circuits, MIN, MAX circuits, and literal circuit are shown. These circuits have a simple configuration and high speed.

A universal literal circuit and its application to quaternary logic networks

A new type of universal literal circuit, in which two thresholds of the circuit are variable and controlled by external signals, is proposed herein. The circuit is designed with CMOS-FETs, and both computer simulation by FSPICE and experiments on bread-board with discrete elements confirm its correct operation. A new type of basic quaternary operator, quaternary U-gate, is also introduced. The U-gate comprises a pair of CMOS pass transistors driven by the output of the universal literal circuit. Mathematical properties of the U-gate are derived, and synthesis procedures of quaternary logic functions using U-gates are given. The quaternary U-gate and quaternary constants form a complete set of quaternary operators and its mathematical properties implicate those of CP-gates and SCP-gates.

Quaternary logic circuits in 2- mu m CMOS technology

Novel quaternary logic circuits, designed in 2- mu m CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-to-binary decoder, and the quaternary register are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra has been designed and fabricated. The prototype chip occupies an area of 4.84 mm/sup 2/, is timed with a 2.2-MHz clock, and consumes 93 mW of power. >